CN104572385B

CN104572385B - Memory fault detection system and method

Info

Publication number: CN104572385B
Application number: CN201410849720.5A
Authority: CN
Inventors: 冯颖俏; 杨辉
Original assignee: Zhongxing Technology Co ltd; Vimicro Corp
Current assignee: Zhongxing Technology Co Ltd; Vimicro Corp
Priority date: 2014-12-29
Filing date: 2014-12-29
Publication date: 2021-04-09
Anticipated expiration: 2034-12-29
Also published as: CN104572385A

Abstract

The invention discloses a memory fault detection system, which is applied to detecting a double-rate synchronous dynamic random access memory (DDR), and comprises the following components: the detection device comprises a Printed Circuit Board (PCB), a detection Socket, a development test board and a detection module, wherein the PCB is connected to the development test board, the detection Socket is connected to the PCB, a Double Data Rate (DDR) is arranged on the detection Socket, and the detection module is connected with the development test board; the detection module is used for detecting the DDR. According to the invention, DDR can be welded on the socket by adopting the detection socket, and DDR is detected, so that the traditional mode of directly welding on a detection plate is not adopted, the limitation that both cpu and DDR adopt BGA package can be broken, the utilization rate of detection hardware can be improved for multiple use by adopting the detection socket, and the cost for detecting DDR is greatly reduced.

Description

Memory fault detection system and method

Technical Field

The invention relates to the field of computers, in particular to a system and a method for detecting faults of a memory.

Background

At present, in an embedded system, besides a CPU chip, a DDR dynamic memory is often used for program running, storage, and data caching. At present, DDR in the field is generally directly welded on a PCB, because a CPU and a DDR chip are in a BGA packaging format, once the DDR is welded on the PCB, waveforms of signals such as control signals, address/data signals and clocks which cannot directly measure the DDR cause that the control signals of the DDR cannot be directly observed, and once the DDR has a problem, the DDR usually takes a very long time and has high cost to locate the problem.

An effective solution to the problems in the related art has not been proposed yet.

Disclosure of Invention

Aiming at the problems in the related art, the invention provides a system and a method for detecting faults of a memory, which can quickly, simply and conveniently locate the fault position of a DDR and can save the cost.

The technical scheme of the invention is realized as follows:

according to one aspect of the invention, a memory failure detection system is provided.

The system comprises:

the detection device comprises a Printed Circuit Board (PCB), a detection Socket, a development test board and a detection module, wherein the PCB is connected to the development test board, the detection Socket is connected to the PCB, a Double Data Rate (DDR) is arranged on the detection Socket, and the detection module is connected with the development test board;

the detection module is used for detecting the DDR.

Wherein, this system can also include:

and the detection terminal PC is connected with the detection module and used for sending the detection instruction to the detection module.

Wherein, this system can also include:

and the oscilloscope is connected with the DDR and used for testing the DDR.

The socket is characterized in that the socket is provided with a plurality of test pin interfaces, wherein part or all of the plurality of test pin interfaces correspond to the pin types of the DDR, and the pins of the DDR are led out.

According to another aspect of the present invention, there is also provided a memory failure detection method, which is applied to the memory failure detection system, and includes:

the detection terminal PC sends the detection information to the test module;

and the test module detects the DDR according to the detection information.

Wherein the detection information includes:

detecting step information and parameter information of the register.

The detection module detects the DDR according to the detection information, and the detection module comprises:

and detecting the DDR according to the parameter of the serial port for detecting the DDR.

And when the initialization state is abnormal, the parameter information of the register is configured.

And when the initialization state is normal and the parameters are abnormal, detecting the DDR by testing the read-write timing of the pins of the DDR led out from the detection socket.

In addition, the detection module can be a main control CPU and is used for analyzing and displaying the collected detection information.

According to the invention, DDR can be welded on the socket by adopting the detection socket, and DDR is detected, so that the traditional mode of directly welding on a detection plate is not adopted, the limitation that both cpu and DDR adopt BGA package can be broken through, and the utilization rate of detection hardware can be improved for multiple use by adopting the detection socket, thus the cost of detecting DDR is greatly reduced, and fault location can be rapidly and effectively carried out on the DDR with fault.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic block diagram of a memory failure detection system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory failure detection system according to an embodiment of the invention;

FIG. 3 is a flow chart of a memory failure detection method according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.

According to an embodiment of the present invention, there is provided

As shown in fig. 1, a memory failure detection system according to an embodiment of the present invention includes:

the detection device comprises a printed circuit board PCB11, a detection Socket12, a development test board 13 and a detection module 14, wherein the PCB11 is connected to the development test board 13, the detection Socket12 is connected to the PCB11, the DDR is arranged on the detection Socket12, and the detection module 14 is connected with the development test board 13;

the detection module 14 is used for detecting the DDR.

Wherein, this system can also include:

and a detection terminal PC (not shown) connected to the detection module 14 for sending a detection instruction to the detection module 14.

Wherein, this system can also include:

and the oscilloscope (not shown) is connected with the DDR and used for testing the DDR.

The detection socket12 has a plurality of test pin interfaces, and part or all of the plurality of test pin interfaces correspond to the pin types of the DDR and lead out the pins of the DDR.

Fig. 2 is a schematic diagram showing a specific composition of the system of the present invention, wherein the detection system comprises: PC + cpu chip + DDR (with socket, test pin).

The design method comprises the following steps:

manufacturing a test PCB, welding a socket on the test PCB, and leading out test points of DDR signals through the socket;

soldering the test PCB to the development board;

when DDR test is needed, the DDR chip to be tested is installed on the DDR socket, and then the test operation can be started.

The embodiment of the invention also provides a fault detection method of the memory, and the method can carry out fault location detection on the DDR through the system.

As shown in fig. 3, the memory failure detection method according to the embodiment of the present invention includes:

step S301, the detection terminal PC sends detection information to a test module;

step S303, the test module detects the DDR according to the detection information.

Wherein the detection information includes:

detecting step information and parameter information of the register.

The test module detects the double-rate synchronous dynamic random access memory DDR according to the detection information, and further comprises:

When the parameter is abnormal, the parameter information of the register can be checked to determine the initialization state of the DDR, and when the initialization state is abnormal, the parameter information of the register is configured.

After all the parameter information of the register is configured correctly, if the initialization state is normal and the parameters are abnormal, the DDR can be detected through testing the read-write timing of the pins of the DDR led out from the detection socket.

In order to clearly understand the technical scheme of the invention, the invention is described in detail by using a specific embodiment.

Referring to fig. 2, a system structure diagram of the present invention is shown, and the detailed test steps are as follows:

the test software is loaded into the cpu through the PC, and the cpu starts the test of the DDR through the instruction of the test code.

The DDR register and the printing information of the testing step are arranged in the testing code, and the running state of the DDR is analyzed by observing the printing information of the serial port after the chip is powered on. Once the printing information shows that the DDR operates abnormally, the values of all registers can be checked to determine the DDR initialization state, if the initialization state is abnormal, whether the configuration of the registers is correct or not is checked, the registers are configured to be correct, and then the program observation result is operated again;

if the initialization state is normal and still DDR data read-write errors exist, the hardware connection problem of the DDR particles and the PCB is mainly checked, at the moment, a test point led out by the DDR particles can be observed by an oscilloscope to analyze the read-write time sequence of the DDR at the moment, and therefore the hardware problem is judged. Therefore, the detection system can quickly locate the DDR problem.

The system software can also be provided with DDR data lines, address lines, single detection of all control signal lines and DDR full-space scanning test, and relevant printing information is output through serial ports. Through the operation of the software, the function and the performance of the DDR can be comprehensively and deeply verified, the position of DDR error is quickly positioned, and the reason of the DDR error is judged.

In summary, by means of the above technical solution of the present invention, the hardware part of the system is provided with the test point satisfying the DDR routing requirement, so that the tester can visually observe the timing sequence of each control signal line, read/write signal line, and the like of the DDR, and thus the fault problem of the DDR can be quickly located. In addition, the system is also provided with a DDR socket, so that the utilization rate of the test board can be improved when the DDR compatibility is tested, and the cost for manufacturing a plurality of test boards is greatly saved.

The detection system comprising the software and hardware system can change the signal detection of DDR on the development board from 'undetectable' to 'practical operation and realization'; the DDR related problems can be positioned and solved in an 'accelerated' way; and the DDR compatibility test is convenient to continue.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A memory failure detection system for DDR (double data rate synchronous dynamic random access memory) detection, the system comprising:

the DDR is arranged on the detection socket, the detection module is connected with the development test board, and the detection terminal is connected with the detection module;

the detection module is a main control CPU and is used for detecting the DDR; and the number of the first and second groups,

the detection terminal is a PC and is used for sending detection information to the detection module.

2. The memory fault detection system of claim 1, comprising:

and the oscilloscope is connected with the DDR and used for testing the DDR.

3. The memory fault detection system of claim 1, wherein the detection socket has a plurality of test pin interfaces, wherein part or all of the plurality of test pin interfaces correspond to pin types of the DDR and lead out pins of the DDR.

4. A memory failure detection method applied to the memory failure detection system according to any one of claims 1 to 3, the method comprising:

the detection terminal sends the detection information to the detection module;

and the detection module detects the DDR according to the detection information.

5. The memory failure detection method of claim 4, wherein the detection information comprises:

detecting step information and parameter information of the register.

6. The memory fault detection method of claim 4, wherein the detecting module detects the DDR according to the detection information, and comprises:

and detecting the DDR according to the parameter for detecting the serial port of the DDR.

7. The method as claimed in claim 6, wherein when the parameter is abnormal, looking up parameter information of a register to determine the initialization state of the DDR, and when the initialization state is abnormal, configuring the parameter information of the register.

8. The method according to claim 7, wherein when the initialization state is normal and the parameter is abnormal, the DDR is detected by testing a read/write timing of a pin of the DDR led out from a detection socket.

9. The method according to claim 4, wherein the detection module is configured to analyze and display the collected detection information.