CN104572385A

CN104572385A - System and method for detecting memory faults

Info

Publication number: CN104572385A
Application number: CN201410849720.5A
Authority: CN
Inventors: 冯颖俏; 杨辉
Original assignee: Vimicro Corp
Current assignee: Zhongxing Technology Co Ltd; Vimicro Corp
Priority date: 2014-12-29
Filing date: 2014-12-29
Publication date: 2015-04-29
Anticipated expiration: 2034-12-29
Also published as: CN104572385B

Abstract

The invention discloses a system for detecting memory faults. The system is applied to detecting a double-data rate synchronous dynamic random memory (DDR); the system comprises a printed circuit board (PCB), a detection socket, a development test board and a detection module, wherein the PCB is connected to the development test board; the detection socket is connected to the PCB; the DDR is arranged on the detection socket; the detection module is connected with the development test board and used for detecting the DDR. According to the system for detecting the memory faults, the detection socket is adopted and the DDR can be welded on the socket and then is detected, and therefore, the traditional way of directly welding on the test board is avoided, the limitation that both CPU and DDR are packaged in a BGA can be broken through; besides, due to the adopted detection socket, the utilization rate of detection hardware can be increased and the cost of detecting the DDR is greatly reduced.

Description

Storage failure detection system and method

Technical field

The present invention relates to computer realm, specifically, relate to a kind of storage failure detection system and method.

Background technology

At present, in embedded systems, except cpu chip, DDR dynamic storage often can be adopted for the operation of program, store and data buffer storage.In current this area, DDR is welded direct on pcb board usually, because CPU and DDR chip is all BGA package form, once being welded on PCB is the control signal directly cannot measuring DDR, address/data signal, the waveform of the signals such as clock causes the control signal directly cannot observing DDR, once DDR goes wrong and often expends very long-time and high cost and go orientation problem.

For the problem in correlation technique, at present effective solution is not yet proposed.

Summary of the invention

For the problem in correlation technique, the present invention proposes a kind of storage failure detection system and method, the abort situation orienting DDR that can be fast and convenient and can be cost-saving.

Technical scheme of the present invention is achieved in that

According to an aspect of the present invention, a kind of storage failure detection system is provided.

This system comprises:

Printed-wiring board (PWB) PCB, test socket Socket, developing and testing board, detection module, wherein, PCB is connected in developing and testing board, and test socket is connected on PCB, and DDR is arranged in test socket, and detection module is connected with developing and testing board;

Detection module is used for detecting DDR.

Wherein, this system can also comprise:

Sense terminals PC, PC are connected with detection module, for detection instruction is sent to detection module.

Wherein, this system can also comprise:

Oscillograph, oscillograph is connected with DDR, for testing DDR.

Wherein, there is multiple test pin interface in test socket, and wherein multiple test pin interface is partly or entirely corresponding with the pin type of DDR, and is drawn by the pin of DDR.

According to a further aspect in the invention, additionally provide a kind of storage failure detection method, the method is applied in above-mentioned storage failure detection system, and the method comprises:

Detection Information is sent to test module by sense terminals PC;

Test module detects Double Data Rate synchronous DRAM DDR according to Detection Information.

Wherein, Detection Information comprises:

The parameter information of detecting step information, register.

Wherein, test module detects Double Data Rate synchronous DRAM DDR according to Detection Information, comprising:

Parameter according to the serial ports detecting DDR detects DDR.

Wherein, when abnormal parameters, check that the parameter information of register is in order to determine the init state of DDR, when initialization state is abnormal, the parameter information of configuration register.

Wherein, when the normal and abnormal parameters of initialization state, the read-write sequence of the pin of the DDR drawn by test test socket is detected DDR.

In addition, detection module can be master cpu, for analyzing the Detection Information collected and showing.

DDR can be welded on this socket by adopting test socket by the present invention, DDR is detected, thus traditional mode be directly welded on check-out console can not be adopted, the restriction that cpu and DDR all adopts BGA package can be broken, and the utilization factor that the present invention can improve detection hardware by test socket repeatedly uses, greatly reduce the cost when detecting DDR, and fast and effeciently can carry out localization of fault to the DDR broken down.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the schematic block diagram of the storage failure detection system according to the embodiment of the present invention;

Fig. 2 is the schematic diagram of the storage failure detection system according to the embodiment of the present invention;

Fig. 3 is the process flow diagram of the storage failure detection method according to the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain, all belongs to the scope of protection of the invention.

According to embodiments of the invention, provide

As shown in Figure 1, comprise according to the storage failure detection system of the embodiment of the present invention:

Printed-wiring board (PWB) PCB11, test socket Socket12, developing and testing board 13, detection module 14, wherein, PCB11 is connected in developing and testing board 13, and test socket 12 is connected on PCB11, DDR is arranged in test socket 12, and detection module 14 is connected with developing and testing board 13;

Detection module 14 is for detecting DDR.

Wherein, this system can also comprise:

Sense terminals PC (not shown), PC is connected with detection module 14, for detection instruction is sent to detection module 14.

Wherein, this system can also comprise:

Oscillograph (not shown), oscillograph is connected with DDR, for testing DDR.

Wherein, there is multiple test pin interface in test socket 12, the plurality of test pin interface partly or entirely corresponding with the pin type of DDR, and drawn by the pin of DDR.

One that is illustrated in figure 2 system of the present invention specifically forms schematic diagram, and this detection system is: PC+cpu chip+DDR (band socket, has test pin).

Method for designing is as follows:

Make a test PCB, above socket is welded on, and by socket, the test point of each for DDR signal is drawn;

This test PCB is welded on above development board;

When needs carry out DDR test, be installed on needing the DDR chip of test after on DDR socket and just can start test job.

Additionally provide a kind of storage failure detection method according to the embodiment of the present invention, the method can carry out localization of fault detection by said system to DDR.

As shown in Figure 3, the storage failure detection method of the embodiment of the present invention comprises:

Step S301, Detection Information is sent to test module by sense terminals PC;

Step S303, test module detects Double Data Rate synchronous DRAM DDR according to Detection Information.

Wherein, Detection Information comprises:

The parameter information of detecting step information, register.

Wherein, test module detects Double Data Rate synchronous DRAM DDR according to Detection Information, comprises further:

Parameter according to the serial ports detecting DDR detects DDR.

Wherein, when abnormal parameters, can by checking that the parameter information of register is in order to determine the init state of DDR, when initialization state is abnormal, the parameter information of configuration register.

When the parameter information of register is all configured correct after, if the normal and situation of abnormal parameters of init state, can be detected DDR by the read-write sequence of the pin of the DDR of test test socket extraction.

Technical scheme for a more clear understanding of the present invention, describes in detail to the present invention with a specific embodiment below.

Please refer to the system architecture schematic diagram of the present invention shown in Fig. 2, DCO step is as follows:

Testing software is loaded in cpu by PC, and cpu starts the test of DDR by the instruction of test code.

Be provided with the type information of DDR register and testing procedure in test code, after chip powers on, analyzed the running status of DDR by observation serial printing information.Once type information display DDR operation exception, first can check that the value of each register determines DDR init state, if init state will check that the configuration of register is whether correct extremely, be rerun routine observed result after correct value by register configuration;

If init state normally but still have DDR reading and writing data mistake, emphasis is wanted to investigate the signal wiring problem of DDR particle and pcb board, the test point now DDR particle can being observed to draw by oscillograph analyzes the read-write sequence of now DDR, thus judges the problem of hardware aspect.Said detecting system can quick position DDR problem place as can be seen here.

Native system software can also with DDR data line, address wire, the simple detection of each control signal wire and the sweep test of the DDR total space, and exports relevant type information by serial ports.By the operation of this software can be comprehensively deep the function of checking DDR and performance, rapidly the location DDR position of makeing mistakes, judge that DDR makes mistakes reason.

In sum, by means of technique scheme of the present invention, by native system hardware components with the test point meeting the requirement of DDR cabling, tester can be allowed to observe each control signal wire of DDR intuitively, the sequential of reading writing signal line etc., therefore can carry out quick position to the failure problems of DDR.In addition, native system is also with DDR socket, and this can improve the utilization factor of test board when testing DDR and being compatible, thus has greatly saved the cost for making many pieces of test boards.

The input of DDR on development board can be become from " can not detect " by the detection system comprising above software and hardware system " can practical operation and realization "; The relevant issues locating and solve DDR " can be accelerated "; The convenient compatibility test continuing DDR.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a storage failure detection system, is characterized in that, be applied to and detect Double Data Rate synchronous DRAM DDR, described system comprises:

Printed-wiring board (PWB) PCB, test socket Socket, developing and testing board, detection module, wherein, described PCB is connected in described developing and testing board, and described test socket connects on the pcb, described DDR is arranged in described test socket, and described detection module is connected with described developing and testing board;

Described detection module is used for detecting described DDR.

2. system according to claim 1, is characterized in that, comprising:

Sense terminals PC, described PC is connected with described detection module, for detection instruction is sent to described detection module.

3. system according to claim 1, is characterized in that, comprising:

Oscillograph, described oscillograph is connected with described DDR, for testing described DDR.

4. system according to claim 1, is characterized in that, described test socket exists multiple test pin interface, wherein said multiple test pin interface partly or entirely corresponding with the pin type of described DDR, and is drawn by the pin of described DDR.

5. a storage failure detection method, is characterized in that, be applied to as arbitrary in Claims 1-4 as described in storage failure detection system in, described method comprises:

Detection Information is sent to test module by sense terminals PC;

Described test module detects Double Data Rate synchronous DRAM DDR according to described Detection Information.

6. method according to claim 5, is characterized in that, described Detection Information comprises:

The parameter information of detecting step information, register.

7. method according to claim 5, is characterized in that, described test module detects Double Data Rate synchronous DRAM DDR according to described Detection Information, comprising:

Parameter according to the serial ports detecting described DDR detects described DDR.

8. method according to claim 7, it is characterized in that, when described abnormal parameters, check that the parameter information of described register is in order to determine the init state of described DDR, when described init state is abnormal, configure the parameter information of described register.

9. method according to claim 8, is characterized in that, when the normal and described abnormal parameters of described init state, the read-write sequence of the pin of the DDR drawn by test test socket is detected described DDR.

10. method according to claim 5, is characterized in that, described detection module is master cpu, for analyzing the Detection Information collected and showing.