CN101354673B

CN101354673B - SPD chip error information simulation apparatus of memory

Info

Publication number: CN101354673B
Application number: CN200710029418A
Authority: CN
Inventors: 陈浩彬
Original assignee: Mitac Computer Shunde Ltd; Mitac International Corp
Current assignee: Mitac Computer Shunde Ltd; Shunda Computer Factory Co Ltd; Mitac International Corp
Priority date: 2007-07-27
Filing date: 2007-07-27
Publication date: 2010-05-26
Anticipated expiration: 2027-07-27
Also published as: CN101354673A

Abstract

An SPD chip error message simulation device for an internal memory is used for transferring the internal memory to an internal memory slot of a computer motherboard to be tested. The device comprises a plurality of memory units, and clock input pins of the memory units are all electrically connected with an SPD clock input pin of the internal memory. The simulation device also comprises a multi-path diverter switch and an I2C interface, wherein one end of the multi-path diverter switch is respectively connected with data input/output pins of the plurality of memory units and SPD data input/output pins of the internal memory, and the other end of the multi-path diverter switch is electrically connected with the SPD data input/output pins of the internal memory slot, and data pins of the I2C interface. The simulation device also comprises a signal transfer circuit which is respectively electrically connected with other pins corresponding to the internal memory and the internal memory slot except the SPD data input/output pins. The simulation device does not need reading and modifying data from a signal line welded with pins of the SPD chip, thereby preventing damages to an internal memory circuit board and the SPD chip.

Description

SPD chip error information simulation apparatus of memory

Technical field

The invention relates to a kind of simulator, and particularly relevant for a kind of SPD chip error information simulation apparatus of memory.

Background technology

Internal memory PCB (Printed Circuit Board, printed circuit board (PCB)) also has on the limit that volume is less (to be approximately the chip of 3mm * 4mm * 1.5mm), Here it is SPD (Serial Presence Detect, serial exists to be surveyed) chip, it is EEPROM (the Electrically ErasableProgrammable ROM of one 8 pin, EEPROM (Electrically Erasable Programmable Read Only Memo)), the related data that this internal memory has mainly been preserved in the inside is as capacity, chip manufacturer, memory modules manufacturer, operating rate etc.The content of SPD is generally write by memory modules manufacturer, supports the mainboard of SPD to detect the data among the SPD automatically when starting, and with the running parameter of this set memory.Behind the launch computer, mainboard BIOS will directly go to read the information among the SPD, and the mainboard north bridge chipset will dispose corresponding internal memory work schedule and control register automatically according to these parameter informations, thereby can give full play to the performance of memory bar.When mainboard can not detect SPD information from internal memory, it just can only provide a comparatively conservative configuration.If the parameter value in the SPD is provided with unreasonablely, not only can not play the effect of optimizing internal memory, also can cause the system works instability on the contrary, even crash.Therefore, a lot of common memory or compatible internal memory manufacturer generally all are provided with the internal memory running parameter among the SPD comparatively conservative, thereby have limited giving full play to of internal memory performance for fear of compatibility issue.What is more, and some illegal manufacturers go to change SPD information by special read-write equipment, with the detection of the computer of out-tricking, draw and actual inconsistent data, thus the deception consumer.

Therefore, need the checking computer motherboard whether normal to the error detection and the recovery function of internal memory, yet carrying out this kind checking need carry out the SPD chip of internal memory as capacity, internal storage datas such as speed are made amendment, make its data different with original memory modules (DDR2), again memory modules (DDR2) being inserted to mainboard starting verifies, and this action, needing to come out to carry out data with I2C (Inter-IC) interface from the EEPROM welding coherent signal line that memory modules (DDR2) is gone up reads, carry out writing once more behind the data modification, not only consuming time, the consumption worker, need welding and tip-off external circuit repeatedly, and often write outage and other mistake that can not expect unexpected when reading because of failure welding or data, and cause damaging of memory modules (DDR2) itself, very not convenient.

Summary of the invention

In view of this, purpose of the present invention is providing a kind of SPD chip error information simulation apparatus of memory exactly, its alternative this SPD chip offers the error message of the multiple difference of computer motherboard to be measured, thereby can avoid revising all drawbacks that the information of SPD chip-stored is brought.

For reaching above-mentioned purpose, the present invention adopts following technical scheme: a kind of SPD chip error information simulation apparatus of memory, in order to transfer this internal memory to the memory bank of computer motherboard to be measured, this simulator comprises some storeies, those storeies and this SPD chip all are the EEPROM (Electrically Erasable Programmable Read Only Memo) of identical eight pins, and the clock input pin of those storeies all electrically connects with the SPD clock input pin of this internal memory; This simulator also comprises a multi-channel switch and an I2C interface, this multi-channel switch one end connects the data I/O pin of those storeies and the SPD data I/O pin of this internal memory respectively, and this multi-channel switch other end all is electrically connected to the SPD data I/O pin of this motherboard memory bank and the data pin of this I2C interface; This simulator also comprises a signal converting circuit, and except the SPD data I/O pin of this internal memory and this memory bank, this signal converting circuit is electrically connected this internal memory and pairing other pin of this memory bank one by one.

Than routine techniques, the present invention is by being provided with this SPD chip error information simulation apparatus of memory, need not be from SPD pin of chip welding signal line so that this SPD chip be carried out reading and revising of data, thereby can prevent to cause damage to memory circuit board and SPD chip, and this simulator can provide the error message of many groups to computer motherboard to be measured to carry out corresponding test, need not repeat this SPD chip is carried out the modification of data, save testing procedure and time greatly.

Description of drawings

Fig. 1 is the circuit diagram of SPD chip error information simulation apparatus of memory of the present invention.

Embodiment

For describing technology contents of the present invention, structural attitude in detail, illustrated in detail below in conjunction with embodiment and conjunction with figs..

As shown in Figure 1, SPD chip error information simulation apparatus of memory 1000 of the present invention is used for the SPD chip (not shown) of substitute memory to offer computer motherboard error message to be measured, thereby test detecting and the recovery function of this computer motherboard to be measured at the error message of SPD chip, these simulator 1000 switchable these internal memories (not shown) to the memory bank of computer motherboard to be measured, this simulator 1000 comprises four storeies 1100, the SPD chip of this four storer 1100 and this internal memory is all the EEPROM (Electrically Erasable Programmable Read Only Memo) of eight identical pins, in present embodiment, those storeies 1100 are all selected AT34C02 for use, and the SPD clock input pin M_SCL of clock input pin SCL and this internal memory electrically connects in this four storer 1100.

This simulator 1000 also comprises a multi-channel switch 1200 and an I2C interface 1300, this multi-channel switch 1200 is to advance five change-over switches that go out the First Five-Year Plan, five interfaces of these multi-channel switch 1,200 one ends connect the SPD data I/O pin M_SDA12 of this internal memory and the data I/O pin SDA of this four storer 1100 respectively, five interfaces of these multi-channel switch 1200 other end correspondences all are electrically connected to the SPD data I/O pin M_SDA11 of this memory bank, and the data pin of this I2C interface, in addition, the clock pin also connects clock input pin SCL in this four storer 1100 in this I2C interface.

This simulator 1000 also comprises a signal converting circuit (not shown), except the SPD data I/O pin M_SDA11 of the SPD data I/O pin M_SDA12 of this internal memory and this memory bank, this signal converting circuit is electrically connected this internal memory and pairing other pin of this memory bank one by one.

So, when needs are tested computer motherboard to be measured and provided the detecting of error message and recovery function at the SPD chip of this internal memory, at first this internal memory is inserted on this simulator 1000; Then this multi-channel switch 1200 is connected the data pin of this I2C interface 1300 and the SPD data I/O pin M_SDA12 of this internal memory, be connected with another computer by this I2C interface 1300, thereby by this I2C interface 1300, this computer-readable is got the information code of the SPD chip-stored of this internal memory, this information code mainly is the related data of this internal memory, as capacity, chip manufacturer, memory modules manufacturer, operating rate etc., and then can on this computer, revise those data, for example, this memory size 256MByte, during speed 533MHz, the capacity that can change into is 512M Byte or 1G Byte, speed is many data such as 667MHz; And then being connected between the SPD data I/O pin M_SDA12 of the data pin of cutting off this I2C interface 1300 on this multi-channel switch 1200 and this internal memory, and connect the data pin of this I2C interface 1300 and the data I/O pin SDA of a storer 1100 wherein; Again next, can pass through this I2C interface 1300, the information code of the SPD chip-stored revised is stored on one of them storer 1100; Afterwards, disconnect being connected of this computer and this I2C interface 1300, and in the memory bank with these simulator 1000 these computer motherboards to be measured of insertion, so, this wherein the data I/O pin SDA of a storer 1100 will connect the SPD data I/O pin M_SDA11 of this memory bank, start this computer to be measured, the SPD chip information sign indicating number of the internal memory through revising of these storer 1100 storages will be sent in this computer motherboard to be measured, thereby can test.

Certainly, in present embodiment, other three storeies 1100 also can also be stored different SPD chip information sign indicating numbers through revising, thereby in test process, switching by this multi-channel switch 1200 is selected, can provide this computer motherboard to be measured four groups of different error messages altogether, thereby can better test this computer motherboard to be measured provides error message at the memory SPD chip detecting and recovery function.

The above only is a preferable possible embodiments of the present invention, is not so promptly limits to claim of the present invention, so the equivalent structure that every utilization instructions of the present invention and accompanying drawing content are done changes, all is contained in protection scope of the present invention.

Claims

1. SPD chip error information simulation apparatus of memory in order to transfer this internal memory to the memory bank of computer motherboard to be measured, is characterized in that this simulator comprises:

Four storeies, the clock input pin of those storeies all electrically connect with the SPD clock input pin of this internal memory;

One multi-channel switch, this multi-channel switch one end connects the data I/O pin of those storeies and the SPD data I/O pin of this internal memory respectively, and this multi-channel switch other end all is electrically connected to the SPD data I/O pin of this motherboard memory bank;

One I2C interface, the other end of this multi-channel switch also electrically connects the data pin of this I2C interface, and the clock pin also connects the clock input pin of those storeies in this I2C interface;

One signal converting circuit, this signal converting circuit are electrically connected this internal memory and pairing other pin except that SPD data I/O pin of this memory bank one by one.

2. SPD chip error information simulation apparatus of memory according to claim 1 is characterized in that, those storeies and this SPD chip all are the EEPROM (Electrically Erasable Programmable Read Only Memo) of identical eight pins.

3. SPD chip error information simulation apparatus of memory according to claim 1 is characterized in that described storer is selected AT34CO2 for use.

4. SPD chip error information simulation apparatus of memory according to claim 1 is characterized in that, described multi-channel switch is to advance five change-over switches that go out the First Five-Year Plan.