CN114461479A - Method and device for debugging multimedia processing chip, storage medium and electronic equipment - Google Patents
Method and device for debugging multimedia processing chip, storage medium and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application discloses a method, a device, a storage medium and electronic equipment for debugging a multimedia processing chip, wherein an application processing chip is connected with an external interface of the multimedia processing chip, the application processing chip receives an interrupt signal from the multimedia processing chip, and the interrupt signal indicates that a communication bus of the multimedia processing chip is suspended; simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and determining an abnormal IP core in the multimedia processing chip based on the debugging signal. By the mode, when the communication bus of the multimedia processing chip cannot normally run, the application processing chip connected with the multimedia processing chip can simulate a debugging signal through the connected peripheral interface, and the abnormal IP core is positioned in time based on the debugging signal.
Description
Technical Field
The present application relates to the field of electronic device technologies, and in particular, to a method and an apparatus for debugging a multimedia processing chip, a storage medium, and an electronic device.
Background
As the functions of electronic devices become more abundant, some electronic devices are provided with a plurality of chips in order to improve processing capacity. When a communication bus is hung (bushang) in the operation process of one of the chips, the chips cannot normally operate, and at the moment, an abnormal IP core needs to be positioned to recover the normal operation of the electronic equipment.
Disclosure of Invention
The embodiment of the application provides a method, a device, a storage medium and electronic equipment for debugging a multimedia processing chip, which can locate an abnormal IP core in time when a communication bus of the multimedia processing chip is hung.
In a first aspect, an embodiment of the present application provides a method for debugging a multimedia processing chip in an application processing chip, where the application processing chip is connected to an external interface of the multimedia processing chip, and the method includes:
receiving an interrupt signal from the multimedia processing chip, the interrupt signal indicating that a communication bus of the multimedia processing chip is suspended;
simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and
and determining an abnormal IP core in the multimedia processing chip based on the debugging signal.
In a second aspect, an embodiment of the present application further provides a method for debugging a multimedia processing chip in the multimedia processing chip, where an external interface of the multimedia processing chip is connected to an application processing chip, and the method includes:
and when the communication bus is detected to be hung, sending an interrupt signal to the application processing chip.
In a third aspect, an embodiment of the present application further provides a method for debugging a multimedia processing chip, where an external interface of the multimedia processing chip is connected to an application processing chip, and the method includes:
when the multimedia processing chip detects that a communication bus is hung, the multimedia processing chip sends an interrupt signal to the application processing chip;
after the application processing chip receives the interrupt signal, the debugging signal of the debugging interface of the multimedia processing chip is simulated through the peripheral interface; and
and the application processing chip determines the abnormal IP core in the multimedia processing chip based on the debugging signal.
In a fourth aspect, an embodiment of the present application further provides an apparatus for debugging a multimedia processing chip in an application processing chip, where the application processing chip is connected to an external interface of the multimedia processing chip, and the apparatus includes:
the signal receiving module is used for receiving an interrupt signal from the multimedia processing chip, wherein the interrupt signal indicates that a communication bus of the multimedia processing chip is suspended;
the signal simulation module is used for simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and
and the abnormal positioning module is used for determining the abnormal IP core in the multimedia processing chip based on the debugging signal.
In a fifth aspect, an embodiment of the present application further provides an apparatus for debugging a multimedia processing chip in the multimedia processing chip, where an external interface of the multimedia processing chip is connected to an application processing chip, and the apparatus includes:
and the signal sending module is used for sending an interrupt signal to the application processing chip when the communication bus is detected to be hung.
In a sixth aspect, an embodiment of the present application further provides an apparatus for debugging a multimedia processing chip, where an external interface of the multimedia processing chip is connected to an application processing chip, and the apparatus includes:
the signal sending module is used for sending an interrupt signal to the application processing chip when the communication bus is detected to be hung;
the signal simulation module is used for simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface after receiving the interrupt signal; and
and the abnormal positioning module is used for determining the abnormal IP core in the multimedia processing chip based on the debugging signal.
In a seventh aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute the method for debugging a multimedia processing chip in an application processing chip as provided in any embodiment of the present application; alternatively, when the computer program runs on a computer, the computer is caused to execute the method for debugging a multimedia processing chip in a multimedia processing chip as provided in any embodiment of the present application.
In an eighth aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes the apparatus for debugging a multimedia processing chip provided in any embodiment of the present application.
According to the technical scheme provided by the embodiment of the application, the application processing chip is connected with the peripheral interface of the multimedia processing chip, when the communication bus of the multimedia processing chip cannot normally run, an interrupt signal is sent to the application processing chip connected with the application processing chip, the application processing chip can simulate a debugging signal through the connected peripheral interface, and the abnormal IP core of the multimedia processing chip is positioned based on the debugging signal.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a diagram illustrating a scenario for debugging a multimedia processing chip using an external device.
Fig. 2 is a flowchart illustrating a method for debugging a multimedia processing chip in an application processing chip according to an embodiment of the present application.
Fig. 3 is an interaction diagram of a method for debugging a multimedia processing chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an apparatus for debugging a multimedia processing chip in an application processing chip according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a first electronic device according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a second electronic device according to an embodiment of the present application.
Fig. 7 is a third schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic view illustrating a scenario for debugging a multimedia processing chip by using an external device. The electronic equipment comprises an application processing chip and a multimedia processing chip, wherein the application processing chip is connected with an external interface of the multimedia processing chip. The multimedia processing chip also has a debugging interface, which can be used to debug the electronic device in the testing phase, for example, the multimedia processing chip is debugged by connecting an external debugging device through the debugging interface. Generally, the debugging interface is closed during mass production, which results in that a user can only return to a factory to dismount if the communication bus of the multimedia processing chip is hung when using the electronic device, and re-welds the debugging interface, and then connects the debugging interface through the external debugging device to debug the communication bus. The debugging efficiency is low, and inconvenience is brought to the use of a user.
In order to solve this problem, embodiments of the present application provide a method for debugging a multimedia processing chip in an application processing chip. The execution main body of the method can be a device for debugging the multimedia processing chip in the application processing chip provided by the embodiment of the application, wherein the device for debugging the multimedia processing chip can be realized in a hardware or software mode. Referring to fig. 2, fig. 2 is a flowchart illustrating a method for debugging a multimedia processing chip in an application processing chip according to an embodiment of the present disclosure. The specific process of the method for debugging the multimedia processing chip in the application processing chip provided by the embodiment of the application can be as follows:
in 101, an interrupt signal is received from the multimedia processing chip, the interrupt signal indicating that a communication bus of the multimedia processing chip is suspended.
In the embodiment of the present application, the multimedia Processing chip may be a Pre-ISP (Pre-Image Signal Processing), and the Pre-ISP may be used to perform some Image Processing, such as dead pixel calibration, linearization, and the like on the original Image data output by the camera, or may also perform backlight shooting in RAW (unprocessed and uncompressed format) domain, high dynamic range shooting, and the like.
The multimedia Processing chip may include a processor, a Memory, an NPU (Neural-network Processing Unit), an image signal processor, and an IP core (also referred to as an Intellectual Property core or an Intellectual Property module) such as a DDR (Double Data Rate Synchronous Dynamic Random Access Memory). The IP cores are connected through a communication bus to communicate.
In general, when the multimedia processing chip is in use, if some IP core runs abnormally, the IP core with abnormal log information can be located by acquiring the log information through a communication bus. However, in some cases, an exception of some IP cores may cause a communication bus to hang (BusHang), and at this time, the communication bus may not work normally, and thus log information may not be acquired. For example, when a user uses a camera application to take a picture, the multimedia processing chip is started to perform related operations of image processing, and if an IP core is abnormal, which causes the communication bus to be suspended, a picture is blocked or a screen is blacked.
In addition, the multimedia processing chip also comprises a debugging bus and a debugging interface connected with the debugging bus, and each IP core in the multimedia processing chip is also connected with the debugging bus. For example, the Debug interface may be a Joint Test Action Group (JTAG) interface, a Serial Wire Debug (SWD) interface, and the like, and in general, these interfaces are used to Debug the multimedia processing chip in a Test phase, and in a mass production phase, a physical interface used for debugging is closed, so that a user cannot Debug a fault of the multimedia processing chip using these Debug interfaces in a use phase.
The Peripheral Interface may be an SDIO (Secure Digital Input and Output) Interface, an SPI (Serial Peripheral Interface), or the like.
Referring to fig. 3, fig. 3 is an interaction diagram of a method for debugging a multimedia processing chip in an application processing chip according to an embodiment of the present disclosure. And when the communication bus is hung up due to the abnormal IP core, the multimedia processing chip sends an interrupt signal to the application processing chip.
In 102, a debugging signal of a debugging interface of the multimedia processing chip is simulated through the peripheral interface.
In 103, an abnormal IP core in the multimedia processing chip is determined based on the debugging signal.
And when the application processing chip receives the interrupt signal sent by the multimedia processing chip, simulating a debugging signal of the debugging interface through the peripheral interface of the multimedia processing chip.
The scheme of the embodiment of the application is described by taking the external interface as an SDIO interface and the debugging interface as a JTAG interface as an example, the application processing chip simulates debugging signals of the JTAG through the SDIO interface according to a JTAG protocol, that is, the application processing chip simulates a JTAG read-write operation time sequence through the SDIO interface and debugs the multimedia processing chip to determine the abnormal IP core.
For example, in some embodiments, simulating a debug signal of a debug interface of the multimedia processing chip through the peripheral interface comprises: simulating a debug signal of the modulation interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debug interface.
Wherein, the JTAG interface includes four pins, TCK: testing clock input; TDI: inputting test data, wherein the data is input into a JTAG interface through TDI; TDO: outputting test data, wherein the data is output from the JTAG interface through TDO; TMS: and the test mode selection is used for setting the JTAG interface to be in a certain test mode. In this embodiment, an SDIO register is added and recorded as a first preset register, and a preset debug protocol is added in a controller of the SDIO, where the preset debug protocol is matched with a debug interface, for example, if the debug interface is a JTAG interface, the preset debug protocol is a JTAG protocol. The added first preset register is associated with a JTAG interface, for example, the lowest four bit bits of the first preset register correspond to four pins of a JTAG one by one, the electric levels of the TMS/TDI/TCK/TDO four pins of the JTAG are changed by writing the four bit bits of the first preset register, and the read-write time sequence of the JTAG is further simulated. The debugging instruction can be triggered by a signal input through the TDI pin, the debugging instruction instructs a JTAG interface to position an abnormal IP core through a JTAG bus, and debugging result data are output to the application processing chip through the TDO pin.
For example, in an embodiment, the determining, based on the debug signal, an IP core in the multimedia processing chip where an exception occurs includes: reading debugging data from a debugging register corresponding to an IP core of the multimedia processing chip based on the debugging signal; and determining the abnormal IP core according to the debugging data. .
In this embodiment, there is one debug register for each IP core. When a certain IP fails in the operation process, the corresponding debugging register is written with data to record failure information. After the debugging instruction is triggered through the debugging interface, the debugging data of the debugging register of each IP core is read through the debugging bus and transmitted to the application processing chip through the peripheral interface. And the application processing chip determines the abnormal IP core according to all the debugging data. For example, whether a field of the debug register is preset or not is judged, and when the preset value exists, the operation of the IP core corresponding to the debug register is judged to be abnormal.
In an embodiment, the application processing chip may locally analyze the debug data to determine the IP core with the exception.
Or, in another embodiment, the application processing chip sends an abnormal positioning request to the server based on the debugging data; and receiving a positioning result from the server, wherein the positioning result indicates the abnormal IP core.
In this embodiment, the application processing chip sends all the acquired debug data to the server, and the server analyzes the data to determine an abnormal IP core, and returns the result to the application processing chip.
In some embodiments, after the abnormal IP core is determined, the abnormal IP core may be reset through the peripheral interface to restore normal operation of the communication bus of the multimedia processing chip. For example, in one embodiment, the method further comprises: and simulating a reset signal by writing into a second preset register of the peripheral interface and sending the reset signal to the multimedia processing chip, wherein the reset signal indicates an abnormal IP core needing to be reset.
In this embodiment, in addition to the first preset register, another register is added to the peripheral interface and is recorded as a second preset register, and the application processing chip triggers a reset signal for the abnormal IP core by writing data in the second preset register. After the abnormal IP core is determined, the application processing chip writes a specific numerical value into the bit corresponding to the abnormal IP core in the second preset register to trigger a reset signal aiming at the abnormal IP core, the reset signal is transmitted to the abnormal IP core through the debugging bus, and the abnormal IP core is restarted to further recover the operation of the communication bus.
In particular implementation, the present application is not limited by the execution sequence of the described steps, and some steps may be performed in other sequences or simultaneously without conflict.
As can be seen from the above, in the method for debugging a multimedia processing chip in an application processing chip provided in the embodiment of the present application, the application processing chip is connected to an external interface of the multimedia processing chip, and when a communication bus of the multimedia processing chip cannot operate normally, an interrupt signal is sent to the application processing chip connected to the application processing chip, and the application processing chip can simulate a debugging signal through the connected external interface, and locate an IP core of the multimedia processing chip, where an abnormality occurs, based on the debugging signal.
The embodiment of the present application further provides a method for debugging a multimedia processing chip in the multimedia processing chip, where an external interface of the multimedia processing chip is connected to an application processing chip, and the method includes:
and when the communication bus is detected to be hung, sending an interrupt signal to the application processing chip.
In this embodiment, if the multimedia processing chip detects that the communication bus is suspended, an interrupt signal is sent to the application processing chip, and for the application processing chip, after receiving the interrupt signal, a debug signal of a debug interface of the multimedia processing chip is simulated through a connected peripheral interface, and an IP core in which an abnormality occurs in the multimedia processing chip is located based on the debug signal. For the generation process of the debugging signal, please refer to the method for debugging the multimedia processing chip in the application processing chip, which is not described herein again.
Wherein, in some embodiments, the method further comprises: resetting the abnormal IP core in response to a reset signal received from the multimedia processing chip. For the generation process of the reset signal, please refer to the method for debugging the multimedia processing chip in the application processing chip, which is not described herein again.
The embodiment of the present application further provides a method for debugging a multimedia processing chip, including:
when the multimedia processing chip detects that a communication bus is hung, the multimedia processing chip sends an interrupt signal to the application processing chip;
after the application processing chip receives the interrupt signal, the debugging signal of the debugging interface of the multimedia processing chip is simulated through the peripheral interface; and
and the multimedia processing chip determines the abnormal IP core in the multimedia processing chip based on the debugging signal.
The specific implementation process is described in the above embodiment of the method for debugging a multimedia processing chip in an application processing chip, and is not described herein again.
An apparatus for debugging a multimedia processing chip in an application processing chip is also provided in an embodiment. Referring to fig. 4, fig. 4 is a schematic structural diagram of an apparatus 300 for debugging a multimedia processing chip in an application processing chip according to an embodiment of the present application. The device 300 for debugging the multimedia processing chip comprises a signal receiving module 301, a signal simulating module 302 and an abnormal positioning module 303, and comprises the following steps:
a signal receiving module 301, configured to receive an interrupt signal from the multimedia processing chip, where the interrupt signal indicates that a communication bus of the multimedia processing chip is suspended;
the signal simulation module 302 is configured to simulate a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface;
and an exception positioning module 303, configured to determine, based on the debug signal, an IP core in the multimedia processing chip that is abnormal.
In some embodiments, the signal simulation module 302 is further configured to: simulating a debug signal of the modulation interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debug interface.
In some embodiments, the anomaly locating module 303 is further configured to: reading debugging data from a debugging register corresponding to an IP core of the multimedia processing chip based on the debugging signal; and determining the abnormal IP core according to the debugging data.
In some embodiments, the anomaly location module 303 is further configured to: sending an abnormal positioning request to a server based on the debugging data; and receiving a positioning result from the server, wherein the positioning result indicates the abnormal IP core.
In some embodiments, the apparatus 300 for debugging a multimedia processing chip further comprises an exception recovery module, configured to: and simulating a reset signal by writing into a second preset register of the peripheral interface and sending the reset signal to the multimedia processing chip, wherein the reset signal indicates an abnormal IP core needing to be reset.
In some embodiments, the peripheral interface is a secure digital input output interface or a serial peripheral interface; and/or the debugging interface is a joint test working group interface or a serial debugging interface.
It should be noted that the apparatus for debugging a multimedia processing chip in an application processing chip provided in this embodiment of the present application and the method for debugging a multimedia processing chip in an application processing chip in the above embodiment belong to the same concept, and any method provided in the embodiment of the method for debugging a multimedia processing chip in an application processing chip can be implemented by the apparatus.
As can be seen from the above, in the apparatus 300 for debugging a multimedia processing chip in an application processing chip according to the embodiment of the present application, the application processing chip and the multimedia processing chip are connected through the peripheral interface. The device 300 comprises a signal receiving module 301, a signal simulating module 302 and an abnormity positioning module 303; when the bus of the multimedia processing chip is hung, an interrupt signal is triggered, the signal receiving module 301 of the application processing chip receives the interrupt signal sent by the multimedia processing chip, and the signal simulating module 302 simulates a debugging signal of a debugging interface according to an external interface of the multimedia processing chip; the exception locating module 303 determines an abnormal IP core having an exception from the plurality of IP cores of the multimedia processing chip based on the debug signal.
An apparatus for debugging a multimedia processing chip in a multimedia processing chip is also provided in an embodiment. The device for debugging the multimedia processing chip in the multimedia processing chip comprises:
and the signal sending module is used for sending an interrupt signal to the application processing chip when the communication bus is detected to be hung.
An apparatus for debugging a multimedia processing chip is also provided in an embodiment. Wherein, the peripheral interface of the said multimedia processing chip is connected with processing chip of the application, the apparatus includes:
the signal sending module is used for sending an interrupt signal to the application processing chip when the communication bus is detected to be hung;
the signal simulation module is used for simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface after receiving the interrupt signal; and
and the abnormal positioning module is used for determining the abnormal IP core in the multimedia processing chip based on the debugging signal.
The specific implementation process is described in the above embodiment of the method for debugging a multimedia processing chip in an application processing chip, and is not described herein again.
The embodiment of the application also provides the electronic equipment. The electronic equipment comprises the device for debugging the multimedia processing chip in the application processing chip.
The embodiment of the application also provides the electronic equipment. The electronic device can be a smart phone, a tablet computer and the like. Referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 400 includes an application processing chip 401 and a multimedia processing chip 402, where the multimedia processing chip includes a peripheral interface 4021, the application processing chip 401 and the multimedia processing chip 402 are connected through the peripheral interface 4021, and the multimedia processing chip 402 is configured to: when detecting that the communication bus is hung, sending an interrupt signal to the application processing chip; the application processing chip 401 is used to: after receiving the interrupt signal, simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and determining an abnormal IP core in the multimedia processing chip based on the debugging signal.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to a second embodiment of the present disclosure. Application processing chip 401 includes a processor 4011 and a memory 4012. The processor 4011 is electrically connected to the memory 4012.
The processor 4011 is a control center of the electronic equipment 400, connects various parts of the whole electronic equipment using various interfaces and lines, and performs various functions of the electronic equipment and processes data by running or calling a computer program stored in the memory 4012 and calling data stored in the memory 4012, thereby integrally monitoring the electronic equipment.
The memory 4012 can be used to store computer programs and data. The memory 4012 stores a computer program containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 4011 executes various functional applications and data processing by calling a computer program stored in the memory 4012.
In this embodiment, the processor 4011 in the electronic device 4010 loads instructions corresponding to processes of one or more computer programs into the memory 4012 according to the following steps, and the processor 4011 runs the computer programs stored in the memory 4012, thereby implementing various functions:
receiving an interrupt signal from the multimedia processing chip, the interrupt signal indicating that a communication bus of the multimedia processing chip is suspended;
simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and
and determining an abnormal IP core in the multimedia processing chip based on the debugging signal.
In some embodiments, please refer to fig. 7, and fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 400 further comprises: radio frequency circuit 403, display 404, control circuit 405, input unit 406, audio circuit 407, sensor 408, and power supply 409. The processor 401 is electrically connected to the radio frequency circuit 403, the display 404, the control circuit 405, the input unit 406, the audio circuit 407, the sensor 408, and the power source 409.
The radio frequency circuit 403 is used for transceiving radio frequency signals to communicate with a network device or other electronic devices through wireless communication.
The display screen 404 may be used to display information entered by or provided to the user as well as various graphical user interfaces of the electronic device, which may be comprised of images, text, icons, video, and any combination thereof.
The control circuit 405 is electrically connected to the display screen 404, and is configured to control the display screen 404 to display information.
The input unit 406 may be used to receive input numbers, character information, or user characteristic information (e.g., fingerprint), and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control. The input unit 406 may include a fingerprint recognition module.
The audio circuit 407 may provide an audio interface between the user and the electronic device through a speaker, microphone. Wherein the audio circuit 407 comprises a microphone. The microphone is electrically connected to the processor 4011. The microphone is used for receiving voice information input by a user.
The sensor 408 is used to collect external environmental information. The sensors 408 may include one or more of ambient light sensors, acceleration sensors, gyroscopes, etc.
The power supply 409 is used to power the various components of the electronic device 400. In some embodiments, the power source 409 may be logically connected to the processor 4011 through a power management system, so that functions of managing charging, discharging, and power consumption are implemented through the power management system.
Although not shown in the drawings, the electronic device 400 may further include a camera, a bluetooth module, and the like, which are not described in detail herein.
In this embodiment, the processor 4011 in the electronic device 400 loads the instructions corresponding to the processes of one or more computer programs into the memory 402 according to the following steps, and the processor 4011 runs the computer programs stored in the memory 402, so as to implement various functions:
receiving an interrupt signal from the multimedia processing chip, the interrupt signal indicating that a communication bus of the multimedia processing chip is suspended;
simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and
and determining an abnormal IP core in the multimedia processing chip based on the debugging signal.
As can be seen from the above, an electronic device provided in an embodiment of the present application includes an application processing chip and a multimedia processing chip, where the application processing chip and the multimedia processing chip are connected through the peripheral interface; when a bus of the multimedia processing chip is hung, an interrupt signal is triggered, the application processing chip receives the interrupt signal sent by the multimedia processing chip, and the application processing chip simulates a debugging signal of a debugging interface through an external interface of the multimedia processing chip; and determining an abnormal IP core with abnormality from a plurality of IP cores of the multimedia processing chip based on the debugging signal. By the method, when the communication bus of the multimedia processing chip cannot normally run, the application processing chip connected with the multimedia processing chip can simulate a debugging signal through the connected peripheral interface, and the abnormal IP core is positioned based on the debugging signal.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program runs on a computer, the computer executes the method for debugging a multimedia processing chip in an application processing chip provided in any of the above embodiments; alternatively, when the computer program runs on a computer, the computer is caused to execute the method for debugging a multimedia processing chip in a multimedia processing chip as provided in any embodiment of the present application.
It should be noted that, all or part of the steps in the methods of the above embodiments may be implemented by hardware related to instructions of a computer program, which may be stored in a computer readable storage medium, which may include, but is not limited to: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
Furthermore, the terms "first", "second", and "third", etc. in this application are used to distinguish different objects, and are not used to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or modules recited, but rather, some embodiments include additional steps or modules not recited, or inherent to such process, method, article, or apparatus.
The method, the apparatus, the storage medium, and the electronic device for debugging a multimedia processing chip provided in the embodiments of the present application are described in detail above. The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (14)
1. A method for debugging a multimedia processing chip in an application processing chip, wherein the application processing chip is connected to a peripheral interface of the multimedia processing chip, the method comprising:
receiving an interrupt signal from the multimedia processing chip, the interrupt signal indicating that a communication bus of the multimedia processing chip is suspended;
simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and
and determining an abnormal IP core in the multimedia processing chip based on the debugging signal.
2. The method of claim 1, wherein simulating, by the peripheral interface, a debug signal of a debug interface of the multimedia processing chip comprises:
simulating a debug signal of the modulation interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debug interface.
3. The method of claim 1, wherein the determining an IP core in the multimedia processing chip that is anomalous based on the debug signal comprises:
reading debugging data from a debugging register corresponding to an IP core of the multimedia processing chip based on the debugging signal; and
and determining the abnormal IP cores according to the debugging data.
4. The method of claim 3, wherein determining an abnormal IP core that is abnormal based on the debug data comprises:
sending an abnormal positioning request to a server based on the debugging data; and
and receiving a positioning result from the server, wherein the positioning result indicates the abnormal IP core.
5. The method of claim 1, wherein the method further comprises:
and simulating a reset signal by writing into a second preset register of the peripheral interface and sending the reset signal to the multimedia processing chip, wherein the reset signal indicates an abnormal IP core needing to be reset.
6. The method of any one of claims 1 to 5, wherein the peripheral interface is a secure digital input output interface or a serial peripheral interface; and/or the debugging interface is a joint test working group interface or a serial debugging interface.
7. A method for debugging a multimedia processing chip in a multimedia processing chip, wherein a peripheral interface of the multimedia processing chip is connected to an application processing chip, the method comprising:
and when the communication bus is detected to be hung, sending an interrupt signal to the application processing chip.
8. The method of claim 7, further comprising: resetting the abnormal IP core in response to a reset signal received from the multimedia processing chip.
9. A method for debugging a multimedia processing chip, wherein an external interface of the multimedia processing chip is connected with an application processing chip, the method comprising the following steps:
when the multimedia processing chip detects that a communication bus is hung, the multimedia processing chip sends an interrupt signal to the application processing chip;
after the application processing chip receives the interrupt signal, the debugging signal of the debugging interface of the multimedia processing chip is simulated through the peripheral interface; and
and the application processing chip determines the abnormal IP core in the multimedia processing chip based on the debugging signal.
10. An apparatus for debugging a multimedia processing chip in an application processing chip, wherein the application processing chip is connected to a peripheral interface of the multimedia processing chip, the apparatus comprising:
the signal receiving module is used for receiving an interrupt signal from the multimedia processing chip, wherein the interrupt signal indicates that a communication bus of the multimedia processing chip is suspended;
the signal simulation module is used for simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface; and
and the abnormal positioning module is used for determining the abnormal IP core in the multimedia processing chip based on the debugging signal.
11. An apparatus for debugging a multimedia processing chip in a multimedia processing chip, wherein a peripheral interface of the multimedia processing chip is connected to an application processing chip, the apparatus comprising:
and the signal sending module is used for sending an interrupt signal to the application processing chip when the communication bus is detected to be hung.
12. An apparatus for debugging a multimedia processing chip, wherein a peripheral interface of the multimedia processing chip is connected to an application processing chip, the apparatus comprising:
the signal sending module is used for sending an interrupt signal to the application processing chip when the communication bus is detected to be hung;
the signal simulation module is used for simulating a debugging signal of a debugging interface of the multimedia processing chip through the peripheral interface after receiving the interrupt signal; and
and the abnormal positioning module is used for determining the abnormal IP core in the multimedia processing chip based on the debugging signal.
13. A computer-readable storage medium, on which a computer program is stored, which, when run on a computer, causes the computer to perform a method of debugging a multimedia processing chip in an application processing chip according to any of claims 1 to 6;
alternatively, the computer program, when run on a computer, causes the computer to perform the method of debugging a multimedia processing chip in a multimedia processing chip as claimed in claim 7 or 8.
14. An electronic device, characterized in that the electronic device comprises the apparatus according to claim 12.
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