CN114546823B - Method for reproducing debug scenario of logic system design and related equipment - Google Patents
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Abstract
The application provides a method and related equipment for reproducing a debugging scene of a logic system design. The method comprises the following steps: receiving a save request for saving a debug scenario, the debug scenario corresponding to a verification environment when a debug error occurs; providing an interface for receiving scene information of a debug scene to be saved based on the save request; according to the scene information of the debug scene to be saved, saving the scene information of the debug scene; and responding to the received reproduction request for reproducing the debug scene, and reproducing the debug scene according to the saved scene information.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method and related apparatus for reproducing a debug scenario of a logic system design.
Background
A software simulator (simulator) may simulate and debug (debug) a logical system design that includes one or more modules. The logic System design may be, for example, a design for an integrated circuit (Application Specific Integrated Circuit, abbreviated ASIC) or a System-On-Chip (abbreviated SOC) for a specific application. In the process of the simulator simulating the design of the logic system, no tool is used for recording the scene information of the debugging, so that engineers are difficult to restore the scene with errors (bugs) in the debugging process.
Disclosure of Invention
In view of the above, the present application provides a method and related apparatus for reproducing a debug scenario of a logic system design.
In a first aspect of the present application, there is provided a method for reproducing a debug scenario of a logic system design, comprising:
receiving a save request for saving a debug scenario, the debug scenario corresponding to a verification environment when a debug error occurs;
providing an interface for receiving scene information of a debug scene to be saved based on the save request;
according to the scene information of the debug scene to be saved, saving the scene information of the debug scene; and
and responding to the received reproduction request for reproducing the debugging scene, and reproducing the debugging scene according to the saved scene information.
In a second aspect of the present application, there is provided a computing device comprising:
a memory for storing a set of instructions; and
at least one processor configured to execute the set of instructions to cause the computing device to perform the method of the first aspect.
In a third aspect of the application, there is provided a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first aspect.
The method and the related equipment for reproducing the debugging scene of the logic system design can restore the debugging scene with debugging errors more quickly.
Drawings
In order to more clearly illustrate the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only of the application and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 illustrates a schematic diagram of an exemplary system provided by an embodiment of the present application.
Fig. 2 shows a schematic structural diagram of an exemplary electronic device according to an embodiment of the present application.
FIG. 3A shows a schematic diagram of an exemplary interface according to an embodiment of the application.
FIG. 3B shows a schematic diagram of another exemplary interface according to an embodiment of the present application.
Fig. 4 shows a flow diagram of an exemplary method provided by an embodiment of the application.
Detailed Description
The present application will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent.
It is to be noted that unless otherwise defined, technical or scientific terms used herein should be taken in a general sense as understood by one of ordinary skill in the art to which the present application belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Fig. 1 shows a schematic diagram of an exemplary system 100 provided by an embodiment of the present application.
As shown in fig. 1, using a software emulator as an example, the system 100 may include a host computer 200 and terminal devices 302, 304. The system 100 may be used for debug (debug) logic system design (e.g., ASIC or SOC). The design file 502 of the logic system design may run in the host computer 200 and be simulated using a simulation tool in the host computer 200, the terminal devices 302, 304 may send debug instructions to the host computer 200 to debug the logic system design corresponding to the design file 502, and the host computer 200 may respond to the debug instructions and use the simulation tool to complete the corresponding debugging operations. In some embodiments, the terminal devices 302, 304 may run emulation software and the interface provided by the emulation software sends debug instructions to the host computer 200 to debug the logical system design.
Since logic system designs are often bulky, the debugging work on the logic system design is often split into multiple parts for debugging by different engineers and may not be completed in a short time. During longer debugging, some errors (bugs) of the logic system design may be found, but current simulation tools do not provide a convenient way to keep track of these errors found by engineers during the debugging process, making it difficult for engineers to quickly revert to the scenario where the errors occur in later stages of the debugging effort.
In some scenarios, multiple engineers are required to work in concert when debugging a design. For example, as shown in FIG. 1, engineer 402 may debug a design with end device 302 and engineer 404 may debug a design with end device 304. It should be noted that, the scenario of cooperative work is only exemplified here, and is not meant to represent that only two engineers participate in cooperative work when debugging a design. It will be appreciated that the number of engineers and corresponding terminal devices involved in the collaborative work may be arbitrary.
Since a logical system design can generally be divided into many modules, an incorrect output of a certain module during debugging does not necessarily mean that the design of this module itself has errors (bugs). One possible scenario is that the excitation signal of the module (e.g., the input signal of the module) itself is erroneous, resulting in an incorrect output of the module. In this case, an engineer debugging the module is typically required to work in concert with engineers responsible for other modules (e.g., the module providing the input signal).
However, current simulation tools do not provide a convenient way to share errors that engineers find during debugging, nor do they have a convenient tool to enable engineers to quickly share each other's context information and quickly revert to the context in which the error occurred. This means that even if one engineer informs another engineer of a problem found by himself, the other engineer still needs to make a great effort to restore the scene of the error occurrence, which results in a decrease of the overall efficiency of the debugging project.
The above only describes the problem existing at the present time by taking a software simulator as an example, and those skilled in the art will recognize that the above problem also exists when a hardware simulator (simulator) is used for debugging work.
In view of this, the system for reproducing the debug scene of the logic system design provided by the application can record, display or share scene information, and can restore the scene with errors more quickly.
Fig. 2 shows a schematic structural diagram of an electronic device 200 according to an embodiment of the present application. The electronic device 200 may be, for example, a computer host, and the terminal devices 302, 304 may also have a similar structure to the electronic device 200. The electronic device 200 may include: processor 202, memory 204, network interface 206, peripheral interface 208, and bus 210. Wherein the processor 202, the memory 204, the network interface 206, and the peripheral interface 208 are communicatively coupled to each other within the device via a bus 210.
The processor 202 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits. The processor 202 may be used to perform functions related to the techniques described herein. In some embodiments, processor 202 may also include multiple processors integrated as a single logic component. As shown in fig. 2, the processor 202 may include a plurality of processors 202a, 202b, and 202c.
The memory 204 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in fig. 2, the stored data may include program instructions (e.g., program instructions for implementing the aspects of the present application) as well as data to be processed (e.g., memory 204 may store temporary code generated during compilation). The processor 202 may also access stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 204 may include volatile storage or nonvolatile storage. In some embodiments, memory 204 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.
The network interface 206 may be configured to provide communications with other external devices to the electronic device 200 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 206 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.
Peripheral interface 208 may be configured to connect electronic device 200 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.
Bus 210 may be configured to transfer information between the various components of electronic device 200 (e.g., processor 202, memory 204, network interface 206, and peripheral interface 208), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.
It should be noted that although the above-described device only shows the processor 202, the memory 204, the network interface 206, the peripheral interface 208, and the bus 210, in a specific implementation, the device may also include other components necessary to achieve proper operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary for implementing the embodiments of the present application, and not all the components shown in the drawings.
Returning to FIG. 1, a user (e.g., engineer 402) may utilize terminal equipment 302 to debug a logical system design through host 200.
FIG. 3A shows a schematic diagram of an exemplary interface 310 according to an embodiment of the application. The interface 310 may be presented in the terminal device 302 for the engineer 402 to debug the logic system design. As shown in fig. 3A, interface 310 may include a first area 312 for exposing design files (e.g., source code files) of a logical system design currently being debugged. For example, a portion of the contents of a design file system.v is shown in FIG. 3A.
During the debugging process, the engineer 402 may find a debug error (bug) 3122. As shown in FIG. 3A, the error 3122 may be highlighted in the first region 312, for example, by bolding the underlined form, thereby prompting the engineer 402 that an error exists with respect to the module of the logic system design to which the code segment corresponds.
To save the debug scenario in which error 3122 occurred to later be able to reproduce the scenario based on the saved file, engineer 402 may send a save request to host 200 via terminal device 302 to save the current debug scenario. The debug scenario may be a verification environment where debug errors currently occur. It will be appreciated that in order to verify a logical system design, a verification environment needs to be provided. This verification environment may be a software verification environment (e.g., UVM) or a hardware test environment (e.g., a hardware emulator). Thus, the verification environment may be related to software and/or hardware. In some embodiments, the save request may be sent by clicking a button in the interface 310 for sending the save request, or may be triggered by entering a shortcut key, and the specific implementation may be set according to the actual requirement.
After receiving the save request, host 200 may provide terminal device 302 with an interface 320 for receiving scene information of the debug scene to be saved. FIG. 3B shows a schematic diagram of an exemplary interface 320 according to an embodiment of the application.
As shown in fig. 3B, in some embodiments, the interface 320 may provide a scene information input window 322, and at least one of the following input fields may be included in the window 322.
An input field for inputting a title (title) of the debug scene. The engineer 402 sets a corresponding title for the scene information by inputting the title information in the input field, so as to facilitate determination of the scene information by the title when reproducing the debug scene later.
An input field for inputting information of a module (scope). Wherein the module may be a first module and a second module that causes the debug error 3122. In some embodiments, when information of two or more modules needs to be entered in the input field, different modules may be distinguished by "a.
An input field for inputting information of an instance (instance) corresponding to an error of the module.
An input field for inputting information of a file (file) corresponding to the error. The file information may be the file name of a design file corresponding to the logical system design currently being debugged, e.g., system.
An input field for entering the line number (line) of the error in the file. For example, as shown in FIG. 3A, error 3122 corresponds to line number 15.
An input field for inputting a description (description) corresponding to the error. Engineer 402 may enter a detailed description of the error in the input field so that when reproducing the debug scenario, other users may be able to better understand the relevant circumstances of the debug error based on some detailed information of the debug error that the detailed description appears.
Engineer 402 may enter relevant information in the corresponding input field of window 322 and then click the "ok" button to send the scene information associated with the error 3122 to host 200.
In some embodiments, the scenario information sent by engineer 402 to host 200 may include at least one of configuration information of a verification environment corresponding to the debug scenario, a first module in which the debug error 3122 occurred, a second module associated with the first module, an instance of the first module, a filename of a source code file in which the first module is located, or a line number of the debug error 3122 in the source code file. Wherein configuration information of the verification environment may be generated by the terminal device 302 based on the current debug scenario and added to the scenario information. Configuration information of the verification environment may include parameters of the compiler, clock frequency, hardware parameters of the FPGA, etc.
After receiving the scene information, the host 200 saves the scene information for subsequent reproduction of the corresponding debug scene.
In some embodiments, the host 200 may acquire the source code file and the waveform file corresponding to the first module and the time when the debug error 3122 occurs based on the received scene information while saving the scene information, and then package the source code file, the waveform file, and the time when the debug error occurs and the debug scene corresponding to the debug information into a debug data packet (debug) 504 and save in the memory 204 of the host 200, as shown in fig. 1.
In some embodiments, information regarding the scene information saved by engineer 402 may be provided in interface 310 of terminal device 302. As shown in fig. 3A, the interface 310 may further include a second area 314 in which a header of the saved scene information may be displayed, so that the engineer 402 may be prompted about the scene information that it has currently saved in the host 200.
In some embodiments, engineer 402 may send a reproduction request to host 200 to reproduce the corresponding debug scene by clicking on the title of the corresponding scene information in region 314.
After receiving the reproduction request, the host 200 may reproduce the corresponding debug scene according to the saved scene information. In some embodiments, the host 200 may directly call the corresponding debug data packet to re-respond to the debug scenario, and the process of reproducing the debug scenario may be presented in the interface of the terminal device 302.
In this way, the engineer 402 sends the reproduction request of the corresponding error to the host 200 at any time, so that the host 200 can reproduce the debug scene in which the error occurs for the engineer 402 based on the saved scene information, which solves the problem that it is difficult to restore the scene in which the error (bug) occurs in the debug process in the related art.
In some embodiments, the occurrence of error 3122 may be related to another module (second module) that is responsible for debugging by another engineer (e.g., engineer 404 of fig. 1), and thus, engineer 402 may add user information (e.g., an ID of engineer 404) corresponding to the other module in the context information that needs to be maintained to share the debugging process with engineer 404. When the scenario information received by the host 200 includes the user information corresponding to the other module, the host 200 may send a debug scenario prompt to the corresponding user to alert the user that an error occurs in the module that is responsible for debugging.
After receiving the debug scene prompt, engineer 404 may send a replay request to host 200 to replay the debug scene, and host 200 may send saved scene information (e.g., debug data packet 504) to engineer 404, for example, into terminal device 304 of engineer 404. In some embodiments, engineer 404 may find debug packet 504 corresponding to the error in memory 204 (e.g., database) of host 200 and then send a replay request to host 200 to replay the debug scenario by clicking on debug packet 504.
In this way, the responsible engineer 404 of the module associated with the error currently found by the engineer 402 may also participate in the commissioning process of the engineer 402 and may quickly replicate the commissioning scenario encountered by the engineer 402 in which the error associated with the engineer 404 occurred.
The embodiment of the application also provides a method for reproducing the debugging scene of the logic system design, which can restore the debugging scene of the debugging error more quickly. Fig. 4 shows a flow diagram of an exemplary method 600 provided by an embodiment of the application. The method 600 may be implemented by the host 200 of fig. 2 and may further include the following steps.
At step 602, host 200 may receive a save request to save a debug scene. Wherein the debug scenario corresponds to a verification environment when a debug error (e.g. error 3122 of fig. 3A) occurs.
In some embodiments, the save request is from a first user (e.g., engineer 402 of FIG. 1), and the context information may include at least one of configuration information of the verification environment, the first module in which the debug error occurred, a second module associated with the first module, an instance of the first module, a filename of a source code file in which the first module resides, or a line number of the debug error in the source code file. In some embodiments, the second module causes the debug error.
At step 604, based on the save request, host 200 may provide an interface (e.g., interface 320 of fig. 3B) for receiving scene information of the debug scene to be saved.
In some embodiments, the interface may include: an input field for inputting a title of the debug scene; an input field for inputting information of the first module and the second module; an input field for inputting instance information corresponding to an error of the first module; an input field for inputting file information corresponding to the error; an input field for inputting a line number of the error in the file; and an input field for inputting a description corresponding to the error.
At step 606, host 200 may save the context information of the debug context based on the context information of the debug context to be saved.
In some embodiments, saving the context information of the debug context further comprises: acquiring a source code file, a waveform file and the occurrence time of the debugging error, which correspond to the first module; and packaging and saving a source code file, a waveform file, a time when the debug error occurred, and the debug scenario corresponding to the first module into a debug data packet (e.g. debug data packet 504 of fig. 1).
In step 608, in response to receiving the reproduction request for reproducing the debug scene, the host 200 may reproduce the debug scene according to the saved scene information, so that the debug scene in which the debug error occurs may be quickly restored for the user.
In some embodiments, the scene information may further include: as user information of a second user of the recipient (e.g., engineer 404 of fig. 1), the method 600 may further include: and sending a debugging scene prompt to the second user so as to remind the second user that the module responsible for debugging is wrong.
In some embodiments, the method 600 may further include: receiving the reproduction request from the second user; and sending the saved scene information to the second user, so that the second user can quickly restore the scene where the error occurs, and the first user and the second user can cooperatively debug the logic system design.
It should be noted that the method of the present application may be performed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the method of the present application, the devices interacting with each other to complete the method.
It should be noted that the foregoing describes specific embodiments of the present application. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
Based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method according to any of the embodiments above, corresponding to the method according to any of the embodiments above.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The storage medium of the foregoing embodiments stores computer instructions for causing the computer to perform the method of any of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the application, the steps may be implemented in any order and there are many other variations of the different aspects of the application as described above, which are not provided in detail for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the application. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the application, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present application is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the application, it should be apparent to one skilled in the art that the application can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the present application should be included in the scope of the present application.
Claims (6)
1. A method for reproducing a debug scenario of a logic system design, comprising:
receiving a save request for saving a debug scenario, the debug scenario corresponding to a verification environment when a debug error occurs;
providing an interface for receiving scene information of a debug scene to be saved based on the save request;
according to the scene information of the debug scene to be saved, saving the scene information of the debug scene, wherein the scene information comprises a first module in which the debug error occurs and a second module associated with the first module, the second module causes the debug error, the save request is from a first user, and the second module is related to a second user;
in response to receiving a reproduction request for reproducing the debug scene, reproducing the debug scene according to saved scene information, wherein the scene information comprises at least one of configuration information of the verification environment, an instance of the first module, a file name of a source code file in which the first module is located, or a line number of the debug error in the source code file, and the scene information further comprises: user information of the second user as a receiving side; and
and sending a debug scene prompt to the second user.
2. The method of claim 1, further comprising:
receiving the reproduction request from the second user; and
and sending the saved scene information to the second user.
3. The method of claim 1, wherein the interface comprises:
an input field for inputting a title of the debug scene;
an input field for inputting information of the first module and the second module;
an input field for inputting instance information corresponding to an error of the first module;
an input field for inputting file information corresponding to the error;
an input field for inputting a line number of the error in the file; and
an input field for inputting a description corresponding to the error.
4. The method of claim 3, wherein saving the context information of the debug context further comprises:
acquiring a source code file, a waveform file and the occurrence time of the debugging error, which correspond to the first module; and
and packing the source code file, the waveform file, the time of occurrence of the debugging error and the debugging scene corresponding to the first module into a debugging data packet and storing the debugging data packet.
5. A computing device, comprising:
a memory for storing a set of instructions; and
at least one processor configured to execute the set of instructions to cause the computing device to perform the method of any one of claims 1 to 4.
6. A non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of any one of claims 1 to 4.
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