CN111639470A - Simulation test method and system for processor cooperative chip and related components - Google Patents
Simulation test method and system for processor cooperative chip and related components Download PDFInfo
- Publication number
- CN111639470A CN111639470A CN202010469700.0A CN202010469700A CN111639470A CN 111639470 A CN111639470 A CN 111639470A CN 202010469700 A CN202010469700 A CN 202010469700A CN 111639470 A CN111639470 A CN 111639470A
- Authority
- CN
- China
- Prior art keywords
- simulation
- state information
- excitation signal
- signal combination
- excitation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The application discloses a simulation test method of a processor cooperation chip, which comprises the steps of obtaining state information generated by the processor cooperation chip in hardware simulation operation; if the hardware simulation operation has simulation errors, determining a random constraint condition according to the state information, and generating a plurality of excitation signal combinations under the random constraint condition; executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result; and setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination, and executing simulation error positioning operation by using the target excitation signal combination. The method and the device can realize accurate positioning of simulation errors. The application also discloses a simulation test system of the processor cooperating chip, an electronic device and a storage medium, which have the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a simulation test method and system for a processor-cooperating chip, an electronic device, and a storage medium.
Background
With the continuous development of process technology and application fields, on one hand, the complexity of chip design is continuously increased, and on the other hand, the requirements on the development cycle of chips are more and more strict, which requires that various verification operations on chips need to be performed as early and efficient as possible. In order to ensure that the description of the RTL code completely meets the functional requirements of the chip, a simulation test needs to be performed on the chip, that is, the input (test stimulus) of the chip in a real scene is simulated, and the correctness of the RTL logic function is verified.
In the front-end simulation verification of the processor and the chip, most input and output objects are CPUs, and manufacturers cannot completely open the behaviors of the CPUs. In the related art, a real CPU is connected to carry out hardware simulation by building an FPGA prototype system platform, but because the input of excitation cannot be completely clear, only the type of functions and operations executed by the CPU can be determined, but the specific time sequence and the specific content of an input signal cannot be predicted, the site where the hardware simulation has errors cannot be recovered, and error positioning is difficult.
Therefore, how to achieve accurate positioning of simulation errors is a technical problem that needs to be solved by those skilled in the art at present.
Disclosure of Invention
The application aims to provide a simulation test method and system of a processor cooperative chip, an electronic device and a storage medium, which can realize accurate positioning of simulation errors.
In order to solve the above technical problem, the present application provides a simulation test method for a processor-cooperating chip, including:
acquiring state information generated by a processor cooperating with a chip in hardware simulation operation;
if the hardware simulation operation has simulation errors, determining a random constraint condition according to the state information, and generating a plurality of excitation signal combinations under the random constraint condition;
executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result;
and setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination, and executing simulation error positioning operation by using the target excitation signal combination.
Optionally, after obtaining the state information generated by the processor cooperating with the chip in the hardware simulation operation, the method further includes:
performing filtering operation on the state information to obtain target state information, and storing the target state information to a target storage space;
correspondingly, determining the random constraint condition according to the state information includes:
and reading the target state information from the target storage space, and determining a random constraint condition according to the target state information.
Optionally, executing a corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result, including:
determining the hardware simulation effect of each excitation signal combination, and executing clustering operation according to the hardware simulation effect to obtain the excitation signal combination with the hardware simulation effect similarity larger than a preset value;
and executing software simulation operation corresponding to the excitation signal combination with the hardware simulation effect similarity larger than the preset value to obtain the software simulation result.
Optionally, executing a corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result, including:
inputting the excitation signal combination into a machine learning model so as to perform self-adaptive adjustment operation on the excitation signal combination by using the machine learning model to obtain an excitation signal combination to be detected with the highest state similarity; the state similarity is the similarity between the estimated state information generated when the software executes the excitation signal combination and the state information generated in the hardware simulation operation;
and executing software simulation operation corresponding to the excitation signal combination to be detected to obtain the software simulation result. Optionally, determining a random constraint condition according to the state information includes:
and taking the moment when the hardware simulation operation has the simulation error as the moment to be reproduced, and determining the random constraint condition according to the state information in a preset time length before the moment to be reproduced.
Optionally, determining a random constraint condition according to the state information includes:
determining proportion information of excitation information carrying data in all excitation information according to the number of the excitation information in the state information and the size of the cache data;
constructing a random constraint comprising the scale information.
Optionally, generating a plurality of excitation signal combinations under the random constraint condition includes:
generating a plurality of said excitation signal combinations meeting said random constraints based on the N initial random seeds.
The present application further provides a simulation test system of a processor cooperating chip, the simulation test system including:
the state information acquisition module is used for acquiring state information generated by the processor in cooperation with the chip in hardware simulation operation;
the excitation combination generating module is used for determining a random constraint condition according to the state information if the hardware simulation operation has simulation errors, and generating a plurality of excitation signal combinations under the random constraint condition;
the software simulation module is used for executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result;
and the error positioning module is used for setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination and executing simulation error positioning operation by utilizing the target excitation signal combination.
The application also provides a storage medium, on which a computer program is stored, and the computer program realizes the steps executed by the simulation test method of the processor cooperation chip when executed.
The application also provides an electronic device, which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the execution of the simulation test method of the processor cooperation chip when calling the computer program in the memory.
The application provides a simulation test method of a processor cooperation chip, which comprises the steps of obtaining state information generated by the processor cooperation chip in hardware simulation operation; if the hardware simulation operation has simulation errors, determining a random constraint condition according to the state information, and generating a plurality of excitation signal combinations under the random constraint condition; executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result; and setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination, and executing simulation error positioning operation by using the target excitation signal combination.
According to the method, firstly, state information generated by a processor and a chip in the hardware simulation operation is acquired, and if an error occurs in the hardware simulation process, corresponding simulation results can be obtained by operating the operation corresponding to each excitation signal combination through software simulation according to the excitation signal combination which is corresponding to the state information and can cause the state information to occur, which is acquired in advance. If the software simulation result also shows a simulation error in hardware simulation, the combination of the excitation signals input into the CPU in the hardware simulation is the target excitation signal combination corresponding to the software simulation result, and the error site can be recovered when the hardware policy is met after the target excitation signal is determined, so that the accurate positioning of the simulation error is realized. The application also provides a simulation test system of the processor cooperating chip, an electronic device and a storage medium, which have the beneficial effects and are not repeated herein.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of a simulation testing method for a processor-cooperating chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating a large-scale excitation replication method for a processor-cooperation chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a simulation test system of a processor-cooperating chip according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of a simulation testing method for a processor-cooperating chip according to an embodiment of the present disclosure.
The specific steps may include:
s101: acquiring state information generated by a processor cooperating with a chip in hardware simulation operation;
the embodiment can be applied to electronic equipment comprising a processor cooperation chip, wherein the processor cooperation chip is an interconnection interface of a specific CPU chip based on Intel and Power and is used for breaking the limitation of the interconnection interface in a single computing system and expanding the number of CPUs. This step may be preceded by a process of performing hardware emulation operations on the processor in cooperation with the chip. The differences between software simulation and hardware simulation include simulation speed and debuggability. Firstly, in terms of speed, because chip logic is often very complex, all circuit logic needs to be simulated by software, so that the simulation speed is very slow, a simulation time of a week or even a week may be required for operation of a few minutes in an actual chip, and hardware simulation is still far faster than software simulation although being limited by the difference between clock frequencies of an FPGA or an accelerator and an ASIC chip (for example, the clock frequency of the FPGA is generally below 200MHZ, and the clock frequency of the ASIC chip is often 1GHz or even higher) than that of the actual chip. However, the software simulation has the advantages that the states and processing processes of excitation and chip logic are completely visible, test excitation and debugging errors can be designed in a targeted manner, and hardware simulation usually only can record specific state information by presetting some storage units to judge the system state and the error source.
The state information of the processor cooperating with the chip at each moment can be acquired in the hardware simulation process, and the state information may include the working state and the working mode of each port, may also include whether each interface cache is full, and may also include the value of a specific register and a specific signal inside the chip. The present embodiment does not limit the specific content of the above-mentioned status information, as long as the processor cooperates with the chip to generate the status information in the hardware simulation operation.
The state information in this embodiment may include a group of state information detected at a certain time or a certain period of time, and a change of the group of state information over time is often a gradual process, that is, a large number of values of a next group of states and a previous group of states are the same, so the collection of the state information may be: firstly, an initial information collection time point and an interval period are determined, complete state information is recorded at the initial time point and the time point of every other interval period, if the state information is completely different from the last complete state information in the period, the changed state information is recorded, and finally the recorded state information can be stored according to the time sequence.
S102: if the hardware simulation operation has simulation errors, determining a random constraint condition according to the state information, and generating a plurality of excitation signal combinations under the random constraint condition;
before the step, an operation for judging whether the hardware simulation operation has a simulation error may also exist, and if the hardware simulation operation has the simulation error, the related operation in the step is executed. After state information generated by the processor and the chip in cooperation in hardware simulation operation is acquired, filtering operation can be performed on the state information to obtain target state information, and the target state information is stored in a target storage space. Accordingly, the process of determining the random constraint condition according to the state information may include: and reading the target state information from the target storage space, and determining a random constraint condition according to the target state information. Specifically, the process of performing the filtering operation on the state information to obtain the target state information may be: and performing compression coding operation on the state information to obtain target state information.
The site of the simulation error can be recovered according to the state information of a period of time before the simulation error occurs, so that the state information in a specific period of time can be selected to realize the generation of the random constraint condition. Specifically, the process of determining the random constraint condition according to the state information may include: and taking the moment when the hardware simulation operation has the simulation error as the moment to be reproduced, and determining the random constraint condition according to the state information in a preset time length before the moment to be reproduced.
The excitation signal, i.e. the input signal, may be a combination of any number of signals. After the state information sequence of the processor cooperative chip within the target time range (within the preset time length before the time to be reproduced) is obtained, some random constraint standards can be screened by taking the state information sequence as a reference standard to generate limited random excitation, and a plurality of groups of excitation signal combinations similar to the hardware simulation effect are obtained. To improve efficiency, some analysis of the changes in the collected state information may be performed first, so that there is a rough judgment on the characteristics of the target stimulus combination in the hardware simulation. For example, if the status information includes information about the number of received bursts and the size of the buffered data, the ratio of bursts with data can be roughly determined. According to the judgment, a random constraint condition is worked out, and random excitation is generated under the constraint condition.
It will be appreciated that the corresponding state information may be detected for each stimulus signal input by the CPU, and thus one or more stimulus signals that may produce the state information may be inversely determined from the state information, i.e., corresponding combinations of stimulus signals may be randomly generated from the state information. The random constraint condition can be determined according to all the state information, for example, the proportion information of the excitation information carrying data in all the excitation information can be determined according to the number of the excitation information in the state information and the size of the buffer data, and then the random constraint condition including the proportion information is constructed. The actual proportion of excitation information carrying data in any excitation signal combination based on the random constraint condition is within a preset interval corresponding to proportion information included in the random constraint condition.
As a possible implementation, the present embodiment may generate a plurality of excitation signal combinations meeting the random constraint condition based on N initial random seeds.
S103: executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result;
on the basis of obtaining the excitation signal combination, the present embodiment may respectively execute the software simulation operations corresponding to the excitation signal combination, and further obtain the corresponding software simulation results. As a possible implementation manner, the embodiment may perform the screening operation on the excitation signal combination first, and then perform the software simulation operation, so as to improve the efficiency of the software simulation, and the specific process is as follows: determining the hardware simulation effect of each excitation signal combination, and executing clustering operation according to the hardware simulation effect to obtain the excitation signal combination with the hardware simulation effect similarity larger than a preset value; and executing software simulation operation corresponding to the excitation signal combination with the hardware simulation effect similarity larger than the preset value to obtain the software simulation result.
S104: and setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination, and executing simulation error positioning operation by using the target excitation signal combination.
If the same simulation error occurs in the software simulation process as in the hardware simulation process, it indicates that the excitation signal combination used in the software simulation is the same as the excitation signal in the CPU or the similarity of the excitation signal in the CPU is greater than a preset value when the simulation error occurs in the hardware simulation, and at this time, the excitation signal combination in which the software simulation result is the simulation error may be set as a target excitation signal combination, and the field is restored based on the target excitation signal combination, so as to realize the positioning of the simulation error, so as to perform error labeling and modification operations on the RTL (Register Transfer Level) code according to the positioning result of the simulation error.
In the embodiment, state information generated by the processor cooperating with the chip in the hardware simulation operation is firstly acquired, and if an error occurs in the hardware simulation process, a corresponding simulation result can be obtained by operating an operation corresponding to each excitation signal combination through software simulation according to the excitation signal combination which is corresponding to the state information and can cause the state information to occur, which is acquired in advance. If the software simulation result also shows a simulation error in hardware simulation, the combination of the excitation signals input into the CPU in the hardware simulation is the target excitation signal combination corresponding to the software simulation result, and the error site can be recovered when the hardware policy is met after the target excitation signal is determined, so that the accurate positioning of the simulation error is realized.
As a further introduction to the corresponding embodiment of fig. 1, the process of obtaining the software simulation result may include: inputting the excitation signal combination into a machine learning model so as to perform self-adaptive adjustment operation on the excitation signal combination by using the machine learning model to obtain an excitation signal combination to be detected with the highest state similarity; the state similarity is the similarity between the estimated state information generated when the software executes the excitation signal combination and the state information generated in the hardware simulation operation; and executing software simulation operation corresponding to the excitation signal combination to be detected to obtain the software simulation result. The method is characterized in that an adjusting excitation signal combination is generated in a machine learning mode, system state information in a larger range can be analyzed and feature extracted in FPGA prototype platform hardware simulation, then a plurality of random software simulation environments are constructed by taking the features as constraint conditions of random verification, and error fields are tried to be recovered by excitation combinations which can be approximated.
The flow described in the above embodiment is explained below by an embodiment in practical use. Referring to fig. 2, fig. 2 is a schematic diagram illustrating a large-scale excitation replication method for a processor-cooperation chip according to an embodiment of the present disclosure.
Step 1: collecting state information in the hardware simulation.
Wherein, the collecting process of the state information in this step may include: and performing filtering operation on all the state information according to a preset rule to finally obtain key information and mode information associated with the excitation information, wherein the key information can comprise the use condition of each interface cache, the CPU occupancy rate and the starting sequence of each interface, and the mode information can comprise the working mode information of each interface, the information of whether the interface function is normal and the like. It can be understood that not all the status information is related to the excitation information, and therefore, the present embodiment may determine the status information capable of effectively reflecting the excitation type according to the correspondence relationship between the excitation information and the status information, and analyze only the status information related to the excitation information, so as to improve the efficiency of error scene reproduction. For example, the present embodiment may set the preset rule as: and reserving the interface working mode information and the interface cache information, removing other state information, and performing filtering operation on all the acquired state information through the preset rule to obtain the state information comprising the interface working mode information and the interface cache information. In the actual hardware simulation, the excitation information changes much more frequently than the state information, so that the embodiment can store information in a longer time range by using the same storage space compared with the conventional mode.
For the state information, the change of a group of information with time is often a gradual process, i.e. the next group of states and the previous group of states have a large number of values which are the same, so the collection of the state information can be simpler. Firstly, an initial information collection time point and an interval period are determined, complete state information is recorded at the initial time point and the time point of every other interval period, if the state information is completely different from the last complete state information in the period, the information is recorded, and the state information is stored according to the time sequence.
Step 2: and generating an excitation combination which is similar to the hardware simulation effect.
After the system state information sequence in the target time range is obtained, random constraint standards are screened by taking the sequence as a reference standard to generate limited random excitation, and a plurality of groups of excitation combinations similar to the hardware simulation effect are obtained. In order to improve efficiency, some analysis must be performed on the collected system state changes, so that a rough judgment is made on the characteristics of the target excitation combination in the hardware simulation. For example, if the status information includes information about the number of received bursts and the size of the buffered data, the ratio of bursts with data can be roughly determined. Based on these determinations, random constraint conditions are made, and random excitation is generated under the constraints.
And step 3: and performing software simulation.
In the method, a machine learning mode can be introduced, and the similarity between the change of the system state information during software simulation and the similarity during hardware simulation is used as random constraints to perform self-adaptive adjustment and scoring. For example, a first round of excitation may be generated with an initial random constraint according to a fixed-scale excitation combination (generally, the excitation size is selected to be the same as or slightly larger than the hardware simulation excitation size) as a round, and then after scoring through the similarity, the values of the parameters in the random constraint may be adjusted according to a constraint adjustment rule until the random constraint with the highest score is obtained. The constraint adjustment rule may be: and adjusting (increasing or decreasing) the values of the parameters in the random constraint according to a preset proportion according to the corresponding relation between the values of the parameters in the random constraint and the similarity score. For example, the similarity score of 20% of the tape data incentives in the random constraint is 60 points, and the similarity score of 40% of the tape data incentives in the random constraint is 70 points, where the proportion of the tape data incentives in the random constraint is in a certain range (including the range of 20% to 40% of the tape data incentives) and the similarity score is positively correlated, and where the proportion of the tape data incentives in the random constraint may be increased by a preset proportion based on the constraint adjustment rule until the proportion of the tape data incentives with the highest similarity score is obtained. The above operation is essentially an operation of seeking an optimal solution through traversal, and the introduction of machine learning enables faster convergence. The present embodiment does not limit the kind of the machine learning algorithm employed.
It can be understood that, if the random time is long enough, although some common characteristics may appear in the random verification excitation under the same random constraint, in order to improve efficiency, a plurality of software simulation environments may be constructed by using more software simulation resources, and in this embodiment, different random seeds may be selected when the excitation signal is randomly generated and the operations in step 3 are performed respectively. Of course, the iterative process between step 3 and the generation of the initial random seed in this embodiment may be automatically implemented.
And 4, step 4: and judging the reproduction result.
The method for determining the reproduction result may be to determine whether there is an abnormality or an error that is the same as that in the hardware simulation, and if so, the process in step 3 may be terminated directly. If a plurality of groups of random excitation groups with the highest similarity score are obtained through the step 3 and the method for generating the initial random seeds, but the same abnormity and errors do not occur, the difference of the state information is manually analyzed, or the random constraint is modified, or the range of collecting the state information from the hardware simulation (including the time range and more different state information) is expanded, and then the process of the steps 2 to 4 in the embodiment is repeated.
In the embodiment, under the verification scene of the processor and the chip, and under the condition that the excitation behavior of the input end cannot be completely mastered, the system state information is adopted as the reproduction standard, and under the condition of a small amount of manual intervention analysis, a large amount of software simulation resources and a random simulation mode are used for fitting the hardware simulation scene, so that the method of excitation combination can be reproduced as much as possible. The excitation reproduction method provided by the embodiment can reduce the time and manpower resources for manually analyzing input excitation characteristics and constructing test cases to try reproduction under the verification scene of the processor cooperating with the chip, can better recover colleagues in a hardware simulation field, can perform large-scale repeated verification in similar scenes for hiding deeper abnormal and wrong designs, and can better ensure the verification quality.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a simulation test system of a processor-cooperating chip according to an embodiment of the present disclosure;
the system may include:
a state information obtaining module 100, configured to obtain state information generated by the processor in cooperation with the chip in the hardware simulation operation;
an excitation combination generating module 200, configured to determine a random constraint condition according to the state information if a simulation error occurs in the hardware simulation operation, and generate a plurality of excitation signal combinations under the random constraint condition;
the software simulation module 300 is configured to execute corresponding software simulation operations according to the excitation signal combinations to obtain software simulation results;
and the error positioning module 400 is configured to set the excitation signal combination with the software simulation result that the simulation error occurs as a target excitation signal combination, and execute a simulation error positioning operation by using the target excitation signal combination.
In the embodiment, state information generated by the processor cooperating with the chip in the hardware simulation operation is firstly acquired, and if an error occurs in the hardware simulation process, a corresponding simulation result can be obtained by operating an operation corresponding to each excitation signal combination through software simulation according to the excitation signal combination which is corresponding to the state information and can cause the state information to occur, which is acquired in advance. If the software simulation result also shows a simulation error in hardware simulation, the combination of the excitation signals input into the CPU in the hardware simulation is the target excitation signal combination corresponding to the software simulation result, and the error site can be recovered when the hardware policy is met after the target excitation signal is determined, so that the accurate positioning of the simulation error is realized.
Further, the method also comprises the following steps:
the information storage module is used for performing filtering operation on state information to obtain target state information after the state information generated by the processor and the chip in cooperation in hardware simulation operation is acquired, and storing the target state information into a target storage space;
correspondingly, the root excitation combination generation module 200 is configured to read the target state information from the target storage space, and determine a random constraint condition according to the target state information.
Further, the software simulation module 300 is configured to determine a hardware simulation effect of each excitation signal combination, and perform a clustering operation according to the hardware simulation effect to obtain an excitation signal combination with a hardware simulation effect similarity greater than a preset value; and the simulation system is also used for executing software simulation operation corresponding to the excitation signal combination with the hardware simulation effect similarity larger than a preset value to obtain the software simulation result.
Further, the software simulation module 300 is configured to input the excitation signal combination to a machine learning model, so that the machine learning model is used to perform adaptive adjustment operation on the excitation signal combination to obtain an excitation signal combination to be detected with the highest state similarity; the state similarity is the similarity between the estimated state information generated when the software executes the excitation signal combination and the state information generated in the hardware simulation operation; and the simulation system is also used for executing software simulation operation corresponding to the combination of the excitation signals to be detected to obtain a software simulation result.
Further, the excitation combination generation module 200 is specifically configured to use a time when the hardware simulation operation has a simulation error as a time to be reproduced, and determine the random constraint condition according to state information within a preset time length before the time to be reproduced.
Further, the excitation combination generating module 200 is specifically configured to determine, according to the number of excitation information in the state information and the size of cache data, proportion information of excitation information carrying data in all excitation information; constructing a random constraint comprising the scale information.
Further, the excitation combination generating module 200 is specifically configured to generate a plurality of excitation signal combinations meeting the random constraint condition based on the N initial random seeds.
Since the embodiment of the system part corresponds to the embodiment of the method part, the embodiment of the system part is described with reference to the embodiment of the method part, and is not repeated here.
The present application also provides a storage medium having a computer program stored thereon, which when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The application further provides an electronic device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided by the foregoing embodiments when calling the computer program in the memory. Of course, the electronic device may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A simulation test method of a processor cooperation chip is characterized by comprising the following steps:
acquiring state information generated by a processor cooperating with a chip in hardware simulation operation;
if the hardware simulation operation has simulation errors, determining a random constraint condition according to the state information, and generating a plurality of excitation signal combinations under the random constraint condition;
executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result;
and setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination, and executing simulation error positioning operation by using the target excitation signal combination.
2. The simulation test method of claim 1, after obtaining the state information generated by the processor in cooperation with the chip during the hardware simulation operation, further comprising:
performing filtering operation on the state information to obtain target state information, and storing the target state information to a target storage space;
correspondingly, determining the random constraint condition according to the state information includes:
and reading the target state information from the target storage space, and determining a random constraint condition according to the target state information.
3. The simulation test method of claim 1, wherein performing corresponding software simulation operations according to the combination of excitation signals to obtain a software simulation result comprises:
determining the hardware simulation effect of each excitation signal combination, and executing clustering operation according to the hardware simulation effect to obtain the excitation signal combination with the hardware simulation effect similarity larger than a preset value;
and executing software simulation operation corresponding to the excitation signal combination with the hardware simulation effect similarity larger than the preset value to obtain the software simulation result.
4. The simulation test method of claim 1, wherein determining random constraints based on the state information comprises:
and taking the moment when the hardware simulation operation has the simulation error as the moment to be reproduced, and determining the random constraint condition according to the state information in a preset time length before the moment to be reproduced.
5. The simulation test method of claim 1, wherein performing corresponding software simulation operations according to the combination of excitation signals to obtain a software simulation result comprises:
inputting the excitation signal combination into a machine learning model so as to perform self-adaptive adjustment operation on the excitation signal combination by using the machine learning model to obtain an excitation signal combination to be detected with the highest state similarity; the state similarity is the similarity between the estimated state information generated when the software executes the excitation signal combination and the state information generated in the hardware simulation operation;
and executing software simulation operation corresponding to the excitation signal combination to be detected to obtain the software simulation result.
6. The simulation test method of claim 1, wherein determining random constraints based on the state information comprises:
determining proportion information of excitation information carrying data in all excitation information according to the number of the excitation information in the state information and the size of the cache data;
constructing a random constraint comprising the scale information.
7. The simulation test method of any one of claims 1 to 6, wherein generating a plurality of combinations of excitation signals under the random constraint comprises:
generating a plurality of said excitation signal combinations meeting said random constraints based on the N initial random seeds.
8. A simulation test system of a processor cooperative chip is characterized by comprising:
the state information acquisition module is used for acquiring state information generated by the processor in cooperation with the chip in hardware simulation operation;
the excitation combination generating module is used for determining a random constraint condition according to the state information if the hardware simulation operation has simulation errors, and generating a plurality of excitation signal combinations under the random constraint condition;
the software simulation module is used for executing corresponding software simulation operation according to the excitation signal combination to obtain a software simulation result;
and the error positioning module is used for setting the excitation signal combination with the software simulation result of the simulation error as a target excitation signal combination and executing simulation error positioning operation by utilizing the target excitation signal combination.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the simulation test method of the processor-co-chip according to any one of claims 1 to 7 when calling the computer program in the memory.
10. A storage medium having stored thereon computer-executable instructions, which when loaded and executed by a processor, carry out the steps of the method for simulation testing of a processor-co-chip as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010469700.0A CN111639470B (en) | 2020-05-28 | 2020-05-28 | Simulation test method and system for processor cooperative chip and related components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010469700.0A CN111639470B (en) | 2020-05-28 | 2020-05-28 | Simulation test method and system for processor cooperative chip and related components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111639470A true CN111639470A (en) | 2020-09-08 |
| CN111639470B CN111639470B (en) | 2022-06-17 |
Family
ID=72331178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010469700.0A Active CN111639470B (en) | 2020-05-28 | 2020-05-28 | Simulation test method and system for processor cooperative chip and related components |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111639470B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112464594A (en) * | 2020-12-11 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Circuit function simulation test method, device, equipment and readable storage medium |
| CN114546823A (en) * | 2021-12-27 | 2022-05-27 | 芯华章科技股份有限公司 | Method for reproducing debugging scene of logic system design and related equipment |
| CN115422865A (en) * | 2022-10-28 | 2022-12-02 | 飞腾信息技术有限公司 | Simulation method and device, computing equipment and computer readable storage medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1725188A (en) * | 2004-07-22 | 2006-01-25 | 华为技术有限公司 | Logic verification system and method |
| CN1828617A (en) * | 2006-03-31 | 2006-09-06 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
| CN102542110A (en) * | 2011-12-29 | 2012-07-04 | 北京时代民芯科技有限公司 | Emulation verification method applied to mobile storage SOC (system on chip) chip |
| WO2014110922A1 (en) * | 2013-01-18 | 2014-07-24 | 浪潮电子信息产业股份有限公司 | Extended cache coherence protocol-based multi-level coherence domain simulation verification and test method |
| CN105302950A (en) * | 2015-10-19 | 2016-02-03 | 北京精密机电控制设备研究所 | Software and hardware cooperation based cross-linking simulation test method for programmable logic device |
| WO2016106605A1 (en) * | 2014-12-30 | 2016-07-07 | 京微雅格（北京）科技有限公司 | Simulation verification method for fpga functional module and system thereof |
| CN107038280A (en) * | 2017-03-10 | 2017-08-11 | 烽火通信科技股份有限公司 | A kind of checking system and method for software and hardware cooperating simulation |
| CN110457743A (en) * | 2019-06-27 | 2019-11-15 | 芯翼信息科技(上海)有限公司 | A kind of chip detecting method based on FPGA |
-
2020
- 2020-05-28 CN CN202010469700.0A patent/CN111639470B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1725188A (en) * | 2004-07-22 | 2006-01-25 | 华为技术有限公司 | Logic verification system and method |
| CN1828617A (en) * | 2006-03-31 | 2006-09-06 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
| CN101499937A (en) * | 2009-03-16 | 2009-08-05 | 盛科网络（苏州）有限公司 | Software and hardware collaborative simulation verification system and method based on FPGA |
| CN102542110A (en) * | 2011-12-29 | 2012-07-04 | 北京时代民芯科技有限公司 | Emulation verification method applied to mobile storage SOC (system on chip) chip |
| WO2014110922A1 (en) * | 2013-01-18 | 2014-07-24 | 浪潮电子信息产业股份有限公司 | Extended cache coherence protocol-based multi-level coherence domain simulation verification and test method |
| WO2016106605A1 (en) * | 2014-12-30 | 2016-07-07 | 京微雅格（北京）科技有限公司 | Simulation verification method for fpga functional module and system thereof |
| CN105302950A (en) * | 2015-10-19 | 2016-02-03 | 北京精密机电控制设备研究所 | Software and hardware cooperation based cross-linking simulation test method for programmable logic device |
| CN107038280A (en) * | 2017-03-10 | 2017-08-11 | 烽火通信科技股份有限公司 | A kind of checking system and method for software and hardware cooperating simulation |
| CN110457743A (en) * | 2019-06-27 | 2019-11-15 | 芯翼信息科技(上海)有限公司 | A kind of chip detecting method based on FPGA |
Non-Patent Citations (4)
| Title |
|---|
| F.HUNSINGER等: "Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)", 《IEEE》 * |
| 孙秀睿: "FPGA设计验证中的软硬件协同仿真测试方法", 《南通大学学报(自然科学版)》 * |
| 章林柯等: "基于VMM方法学的系统级软硬件协同仿真验证", 《微型机与应用》 * |
| 许彤等: "基于覆盖率模型的AMBA接口随机验证方法", 《计算机应用研究》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112464594A (en) * | 2020-12-11 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Circuit function simulation test method, device, equipment and readable storage medium |
| CN112464594B (en) * | 2020-12-11 | 2022-10-28 | 苏州浪潮智能科技有限公司 | Circuit function simulation test method, device, equipment and readable storage medium |
| CN114546823A (en) * | 2021-12-27 | 2022-05-27 | 芯华章科技股份有限公司 | Method for reproducing debugging scene of logic system design and related equipment |
| CN114546823B (en) * | 2021-12-27 | 2023-09-12 | 芯华章科技股份有限公司 | Method for reproducing debug scenario of logic system design and related equipment |
| CN115422865A (en) * | 2022-10-28 | 2022-12-02 | 飞腾信息技术有限公司 | Simulation method and device, computing equipment and computer readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111639470B (en) | 2022-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111639470B (en) | Simulation test method and system for processor cooperative chip and related components | |
| US6718521B1 (en) | Method and system for measuring and reporting test coverage of logic designs | |
| CN110647456B (en) | Fault prediction method, system and related device of storage equipment | |
| CN108681505B (en) | Test case ordering method and device based on decision tree | |
| CN106201857B (en) | The choosing method and device of test case | |
| US7366951B2 (en) | Method and apparatus for test program generation based on an instruction set description of a processor | |
| CN115576834A (en) | Software test multiplexing method, system, terminal and medium for supporting fault recovery | |
| CN110334262B (en) | Model training method and device and electronic equipment | |
| EP2546770A1 (en) | System and method for controlling granularity of transaction recording in discrete event simulation | |
| CN108108558B (en) | Method and system for evaluating random verification quality based on coverage frequency statistics | |
| CN109101414B (en) | Massive UI test generation method and device based on buried point data | |
| CN111091863A (en) | Storage equipment fault detection method and related device | |
| CN117150995B (en) | Driving source code tracking method, electronic equipment and medium | |
| CN112416800A (en) | Intelligent contract testing method, device, equipment and storage medium | |
| CN112631920A (en) | Test method, test device, electronic equipment and readable storage medium | |
| CN112731117A (en) | Automatic verification method and system for chip, and storage medium | |
| CN116860583A (en) | Database performance optimization method and device, storage medium and electronic equipment | |
| CN116009889A (en) | Deep learning model deployment method and device, electronic equipment and storage medium | |
| CN113992730A (en) | Knowledge-based user behavior simulation method, simulation system, customization system, computer and storage medium | |
| CN113569953A (en) | Training method and device of classification model and electronic equipment | |
| CN111352825B (en) | Data interface testing method and device and server | |
| CN113628077A (en) | Method for generating non-repeated examination questions, terminal and readable storage medium | |
| CN114077884A (en) | Model conversion optimization device and method of deep learning model and readable storage medium | |
| CN112527631A (en) | bug positioning method, system, electronic equipment and storage medium | |
| US7650579B2 (en) | Model correspondence method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |