CN1828617A - Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method - Google Patents
Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method Download PDFInfo
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Abstract
The system with a PC software part and FPGA hardware comprises: a bottom layer to transfer information on physical channel, a middle layer to pack and unpack data frame, and a top layer for signal input/output. Wherein, it sends ahead the expected result into the hardware for storage. This invention improves simulation speed greatly with well accuracy.
Description
Technical field
A kind of software and hardware cooperating simulation/verification system and arrow pattern emulation/verification method belong to SoC emulation, verification technique field.
Background technology
Technical term and some important abbreviations
Software and hardware cooperating simulation/checking: be meant a large-scale emulation/verification system is divided into soft, hardware two parts realization, the part that need calculate in a large number adopts the FPGA hardware platform to carry out emulation/checking, is referred to as hardware components; Need the emulation/verification portion of carrying out that the usage behavior level is described or that be used to encourage input and response to export to use PC or workstation to finish, be referred to as software section.Like this, just can pass through advantage separately, constitute large artificial/verification system that a function and speed have all improved in conjunction with FPGA simulation hardware and PC software emulation.
Vector software and hardware cooperating simulation/Validation Mode: be that a kind of record of emphasizing the input that encourages and response all is software and hardware cooperating simulation/Validation Mode that the vector format with prior agreement carries out.Wherein Shu Ru excitation designs before emulation, can not change according to the output response change.
MVP:Module Verification Platform (modelling verification platform)
DUT:Design Under Test (design to be measured)
PLI/VPI:Programming Language Interface/Verilog Procedural Interface is the C language of Verilog hardware description language standard definition and routine interface and the interface realization mechanism of Verilog HDL.One cover C language library function is provided the PLI/VPI routine interface so that dynamically access and revise data in the Verilog HDL data structure of exampleization of user.
Sce-Mi:Standard Co-Emulation:Modeling Interface, be by Accellera propose and with the standard of in May, 2003 issue.It is the standard interface that provides general that is connected between existing verification method and SoC model environment.
Continuous development along with very large scale integration technology, the SoC technology has obtained using widely, a complete SoC system has comprised CPU, DSP, storer, bus on chip and abundant hardware modules such as Peripheral Interface, has also comprised softwares such as interface drive program, operating system and application program.Owing to contain so numerous powerful module, and these intermodules also exist complicated reciprocal process, therefore the difficulty of SoC system design is increasing day by day fast, and emulation/checking is as a most important ring in the integrated circuit (IC) design flow process, its complexity is also in growth at full speed, and this makes traditional method can not satisfy the demand of current industry far away.The current subject matter that the SoC system emulation/the checking field faces is: need carry out a large amount of software emulations, and a large amount of experiments show, in design process, use under the situation that surpasses abundant test of 1,000,000 clock period and checking SoC systemic-function at needs, the performance of software simulation emulator will drop to 1～5Hz, and this will cause the sharp increase of test duration and error probability.And if use FPGA hardware emulator carries out emulation, though can realize the high-speed simulation about 10MHz, the also real time execution of support software simultaneously, but, it but has some open defects, for example, lack and friendly human-computer interaction interface and input-output system the input of inconvenient emulation excitation and the collection of response; Can only support the description of RTL level, can not carry out emulation high-level behavior description module; Simultaneously, the leg signal of FPGA inside and the value of register can not Direct observation, exchange trial work and brought very big inconvenience.However, utilize the high speed performance of FPGA hardware emulator, be still the effective measures that improve the SoC verification efficiency, therefore, how to adopt new method to improve the subject matter that its shortcoming has just become current SoC design field to face.Under such background, the notion (Vector-mode Software/Hardware Co-Simulation) soft, hardware collaborative simulation/checking of Vector pattern is suggested just.
Large-scale SoC design is normally begun by the algorithm design of high level, then is divided into software design and hardware design two big modules according to the function of required realization and the difference of complexity thereof, then gradually refinement until last realization.And the main thought of software and hardware cooperating simulation/checking is exactly, with the function complexity, need a large amount of hardware design modules of calculating to download to test in the FPGA simulation hardware platform and verify, the software module that will adopt senior description such as behavioral scaling to design simultaneously is put into goes exploitation in PC or the workstation, thereby has realized that soft, hardware designing two portions carries out simultaneously.Like this, tightly can not utilize the high speed performance of FPGA hardware platform to come the accelerating hardware Module Design, and simultaneously owing to combine work with software simulator on PC or the workstation, also overcome hardware platform and do not had the good man-machine interaction interface, can't observe quickly and easily excitation and response and can only be in shortcomings such as lower levels such as RTL design, improve the design efficiency of SoC system greatly, shortened the cycle of design, proving time and launch products.
As the basic model of software and hardware cooperating simulation/checking, Vector mode simulation/verification method has fully been showed the thought of software and hardware cooperating simulation, and has embodied its advantage on performance.Its realization mainly can be divided into two processes:
The excitation input process: the form of the test vector that at first generates the agreement form at software section (on PC or the workstation)---this vector can have multiple variation according to the difference of test, verification environment, is mainly stipulated by the tester; Then these test vectors are preserved with the form of text, then by certain conversion back by connecting on the information receiving and transmitting module of FPGA emulator that bottom physical channel soft, hardware side is sent to hardware components; After last transceiver module is analyzed the information that receives and recovered, excitation is input on the input port of corresponding DUT according to certain time sequence, for DUT operation use.
The response record process: after the excitation input, DUT begins operate as normal, and its output port output response signal after hardware side's information receiving and transmitting module receives these output signals, carries out certain buffer memory, then form output by appointment.Pass to software side again by the bottom physical channel, last, the information that software side's record is received also changes them the file of text formatting into.
The software and hardware cooperating simulation implementation method of existing Vector pattern mainly is that some large-scale simulation hardware platform device manufacturers propose, and wherein the most representative be exactly that Aptix company is at its series of products Expeditor
TMMiddle using method.
Aptix company product is to carry out according to the thought of Vector pattern software and hardware cooperating simulation about the emulation/checking of Vecotr pattern, and finish in conjunction with the hardware design of himself.Its main realization flow is: the tester is by appointment form input test excitation vectors in software side, the software MVP that this excitation provides by Aptix (Module Verification Platform) Project Manager is converted into binary format, is then sent it among the DUT on the hardware platform by the hardware interface program of Aptix and tests; After test was finished, response results was sent software side back to by the hardware interface program again, and was converted into the output response file of agreement form by MVPProject Manager.End user will respond with expected result and compare and judge whether the DUT function is correct.
Aptix company device also is the popular and method in common of current industry for the implementation method of Vector pattern software and hardware cooperating simulation/checking, it has kept the basic thought of Vector pattern, and by supporting software and hardware, simulation work soft, the hardware both sides have been connected preferably, and, therefore good performance is arranged because software side does not have the participation of software simulator.But simultaneously, because last output response file must be compared itself and expected results in software side by the tester, this will cause the growth of the time of whole software and hardware cooperating simulation process, and, also can cause the reduction of whole simulation performance owing to do not give full play to the high speed processing performance of hardware.
Existing Vector pattern software and hardware cooperating simulation technology under the less situation of data volume, can adopt the method for artificial contrast to reach a conclusion, and under the bigger situation of data volume, adopt the method for software programming to handle usually when processing response is exported.But no matter adopt which kind of above-mentioned method, all caused the reduction of efficient inevitably.
Summary of the invention
At the above-mentioned deficiency of existing Vector pattern software and hardware cooperating simulation technology at the processing response output facet, the present invention proposes a kind of improved Vector pattern software and hardware cooperating simulation/verification method that adopts response output that hardware quickens DUT and expected results to compare, thereby improved the performance of whole simulation.Set up emulation/verification system of realizing whole Vector pattern software and hardware cooperating simulation/checking simultaneously with extensibility.
The basic thought of the improved Vector pattern of the present invention software and hardware cooperating simulation method is: the user is after emulation begins, the test result and the excited data of expection are mail to the FPGA hardware components together, hardware components is by after analyzing Frame, expected results is kept in the storer, and input stimulus is mail to the input end of DUT.Like this, the output terminal from DUT obtain output corresponding after, just can itself and the expected results that is kept in the storer directly be compared at hardware components by simple comparator circuit, then comparing result is returned software section, be convenient to the user and analyze.
In the general Vector pattern software and hardware cooperating simulation architecture, there are two equities, the communication entity-PC software section and the FPGA hardware components that connect by bottom physical communication passage.The present invention is by the research and analysis to Vector pattern workflow and work characteristics, and the OSI seven layer model structure in the reference computers network architecture, each communication entity has been divided into the three-decker of finishing corresponding function, and wherein, lower floor realizes transmission of Information on the physical channel; The encapsulation and the decapsulation of Frame finished in the middle layer; The input and output of respective signal value are then carried out on the upper strata, as shown in Figure 1.Through above-mentioned division, the architecture of Vector pattern software and hardware cooperating simulation just becomes a kind of stratification, modularization and extendible emulation/verification system.
Concrete technical scheme is:
A kind of software and hardware cooperating simulation/verification system, comprise PC software section and FPGA hardware components, connect by the physical communication passage between the two, it is characterized in that, described PC software section and FPGA hardware components structurally are divided into three layers: lower floor, middle layer and upper strata, lower floor realizes transmission of Information on the physical channel, and the encapsulation and the decapsulation of Frame finished in the middle layer, and the input and output of respective signal value are then carried out on the upper strata; Lower floor comprises the communication port driver module of PC software section and the communication port transceiver module of FPGA hardware components, and the two connects by the physical communication passage; The middle layer comprises the frame processing module of PC software section and the adaptor module of FPGA hardware components; The upper strata comprises the DUT of excitation vectors module, response vector module and the FPGA hardware components of PC software section; Call mutually and transmission information by operation system of software or certain agreement between each layer of PC software section, the input and output port by separately between each layer of FPGA hardware components interconnects.
The effect of each functional module is as follows in this system:
Excitation vectors module: the value of listing each input signal by the form of prior agreement;
Response vector module: the value of output response signal is preserved hereof by the form of arranging in advance;
Frame processing module: when hardware side sends excitation, read in excitation vectors, generate transmission frame and give down the transmission of one deck driver; When receiving the response of passing back hardware side, receive the transmission frame of one deck down, analysis frame information is also exported response vector;
Communication port driver module: finish driving, realize the data transmit-receive at passage two ends to the physical channel;
Communication channel transceiver module: partly realize the driving of communication interface at FPGA;
Adaptor module: when the excitation of receiving software side's transmission,, obtain frame information, produce the needed signal value of upper strata DUT input pin by decapsulation; When software side sends response, collect the response signal value of DUT output pin and assemble framing, give transceiver module then and send.
The DUT module: receive the signal value that lower floor is transmitted at its input end, move according to predefined function, obtain the result after, export corresponding response from output terminal.
From above-mentioned narration as can be known, this architecture can realize the software and hardware cooperating simulation of the Vecotor pattern of any kind, and it is a general architecture.In addition, it also has great extensibility.On the basis of above-mentioned architecture,, can realize other two kinds of current software and hardware cooperating simulation/verification system patterns of widely applying that obtained through following expansion:
1) Co-Simulation pattern software and hardware cooperating simulation/analogue system: by replace excitation input and response output with the behavioral scaling describing module, and the mode of adding the VPI/PLI interface, can realize the software and hardware cooperating simulation of Co-Simulation pattern, as shown in Figure 2.
2) Transaction-Mode transaction mode software and hardware cooperating simulation/verification system: by replace excitation input and response output with the behavioral scaling describing module, and the method for on the passage transceiver module of the channels drive module of software side and hardware side, adding the SCE-MI standard interface, can realize Transaction-Mode transaction mode software and hardware cooperating simulation, as shown in Figure 3.
A kind of arrow pattern software and hardware cooperating simulation/verification method of the present invention is characterized in that it may further comprise the steps:
Step 1: software section is to the processing of input stimulus.Its treatment scheme is as shown in Figure 4:
Text formatting according to prior agreement, the input stimulus vector file, simultaneously, with expected result also with the agreement text formatting write file after, transfer the file in the frame handling procedure of lower floor, send it to the FPGA hardware components after handling by the frame handling procedure.Its specifically can be divided into following three step by step:
Step 1.1: the user finishes on the upper strata of software side the writing of input file (comprise excitation and expected result), and it down is sent in the frame handler module;
Step 1.2: the frame handling procedure in middle layer, software side encapsulates this document after reading the file of user's input, makes it to become the input signal data frame and continue to transmit toward the channels drive program of lower floor, and the idiographic flow of frame handling procedure as shown in Figure 5;
Step 1.3: after the channels drive program receives the Frame that transmits on the upper strata,, Frame is mail to the hardware FPGA emulator by the bottom physical channel by calling the API relevant with the operating system of current operation.
Step 2: hardware components receives excitation and output response.Its treatment scheme is illustrated in fig. 6 shown below:
After the FPGA hardware components receives the data that transmit software side, data are analyzed, it is kept in the storer of FPGA with expected results, and input signal is sent to DUT, then will export response after the output response of collecting DUT and compare with the result who preserves.Deliver in the bottom communication passage transceiver module after at last output response signal and/or comparing result being encapsulated and send to software side.Its concrete steps can be divided into following five step by step:
After the communication port transceiver module of step 2.1:FPGA hardware components receives the Frame of input signal from the bottom physical channel, transfer them in the adaptor module on upper strata;
Step 2.2: adaptor module is by after carrying out decapsulation to the Frame that receives, data are analyzed, the result partly is kept in the storer of FPGA with the output of the expection in the data, produces the pumping signal of excitation files specify in addition, and the input end of input upper strata DUT;
Step 2.3:DUT calculates according to input signal values, produces output response signal and output;
Step 2.4: adaptor module is collected the output response signal that is produced by DUT from the output terminal of DUT, and itself and the expected results that is kept in the storer directly compared at hardware components, after then output response signal and/or comparing result being packaged into Frame, be transferred in lower floor's communication port transceiver module;
Step 2.5: the Frame that the communication channel transceiver module transmits the upper strata mails to software side by the bottom physical channel.
Step 3: software section is to the reception of response signal.Its treatment scheme is as shown in Figure 7:
After software side receives the output response signal Frame that hardware sends over, upwards be submitted to the frame handling procedure on upper strata, save as the output response file at last after treatment or directly present DUT operation result after utilizing hardware-accelerated contrast to the user.
Step 4: repeating step 1 is to step 3, until emulation/checking of finishing whole DUT.
Need to prove that in above-mentioned step 1.2, the user must encapsulate excitation vectors and expected results according to the text formatting of prior agreement, like this, hardware side could distinguish excitation vectors and expected results after receiving Frame.
And in encapsulation process, can also select whether to need hardware components to return concrete comparing result by the mode that zone bit is set: if only need to be judged the function correctness of DUT, then whether hardware side only need return 0/1 and represent function correct; Concrete if desired contrast conclusion, then hardware side still can return detailed error message.This provides multiple choices for the user that different demands are arranged, and has accelerated the whole simulation performance of system greatly.
In step 2.2, hardware side receives after the Frame, according to the form of prior regulation, distinguishes excitation vectors and expected results, handles respectively, simultaneously, also will obtain the information of zone bit, with the data of determining to return after carrying out hardware contrasts.
In step 2.4, obtain comparing result after, according to user's demand (to the judgement of zone bit), the data (simple result or details) that the user is needed encapsulate, and send to lower floor then.
The software and hardware cooperating simulation scheme of the existing Vecotr pattern of contrast, novelty of the present invention are, have proposed to adopt the simulation hardware platform to quicken the improved Vector pattern collaborative simulation/checking implementation method of result's contrast, for the user provides more choices.Simultaneously, at existing Vector pattern software and hardware cooperating simulation/verification method, a general stratification, modular, extendible emulation/verification system have been set up, and make it to be applicable to Vector pattern, Co-Simulation pattern, Transaction-Mode existing three kinds of the most frequently used software and hardware cooperating simulations, Validation Modes such as (transaction mode) through after certain simple function expansion.
On Vector pattern software and hardware cooperating simulation method, essence of the present invention is to have utilized hardware platform emulator travelling speed far away faster than the simple principle of software platform travelling speed, the expected results that will need to be used for comparing in test process sends to hardware components in advance and is kept in the storer of hardware emulator, and just can finish the contrast of mass data by easy comparator circuit.
Compare with existing technology, the present invention has following superiority:
(1) emulation/verification system that is proposed has the characteristic of modularization, stratification, and the modularization work when this characteristic designs the user provides greatly and helped.
(2) emulation/verification system that is proposed also has the characteristics of versatility and extensibility.Through experiment showed, that this system not only can realize the software and hardware cooperating simulation/checking of Vector pattern, after certain expansion, can also be applicable to the software and hardware cooperating simulation of Co-Simulation pattern and Transaction pattern.
(3) the arrow pattern software and hardware cooperating simulation/verification method that is proposed has greatly improved whole simulation velocity by the method that adopts hardware to quicken result's contrast, has reduced the workload of user (tester).
(4) the arrow pattern software and hardware cooperating simulation/verification method that is proposed owing to adopt the hardware contrast to replace the user to DUT operation result subjective observation or software contrast, therefore can improve the accuracy and the correctness of simulation result.
Description of drawings
Fig. 1: arrow pattern software and hardware cooperating simulation of the present invention/verification system structural representation.
Fig. 2: Co-Simulation pattern software and hardware cooperating simulation of the present invention/verification system structural representation.
Fig. 3: transaction mode software and hardware cooperating simulation of the present invention/verification system structural representation.
Fig. 4: step 1-software section is to the treatment scheme synoptic diagram of input stimulus in arrow pattern software and hardware cooperating simulation/verification method of the present invention.
Fig. 5: step 1.2-frame routine processes schematic flow sheet in arrow pattern software and hardware cooperating simulation/verification method of the present invention.
Fig. 6: step 2-hardware components receives the treatment scheme synoptic diagram of excitation and output response in arrow pattern software and hardware cooperating simulation/verification method of the present invention.
Fig. 7: step 3-software section is to the schematic flow sheet of the reception of response signal in arrow pattern software and hardware cooperating simulation/verification method of the present invention.
Embodiment
Modularization analysis according to above-mentioned architecture, the realization of improved Vector pattern software and hardware cooperating simulation can be by realizing earlier the function of each module respectively, and interface according to the rules links to each other then, make up as a whole method and finish, specific implementation can be divided into following a few part:
One, software section:
(1) adopt text formatting, and file of format description excitation vectors according to the rules and response vector file;
(2) adopt C/C++ to realize the frame processing module of software section;
(3) by calling the method for the api function relevant, realize the communication port driver module with operating system.
Two, hardware components:
(1) at the communication channel transceiver module of FPGA hardware platform part, can realize by the interface chip of special use and the internal logic function of FPGA, and finish the connection of communication port;
(2) download to method in the hardware platform by finishing, can realize adaptor module with frame handling procedure corresponding hardware side, software side at the parsing of FPGA part achieve frame and assembling Verilog code;
(3) last, the DUT module is the realization of module to be tested in FPGA, also can be by before emulation begin, design is finished configuration to FPGA by bottom physical channel the method among the FPGA of downloading to.
Claims (7)
1, a kind of software and hardware cooperating simulation/verification system, comprise PC software section and FPGA hardware components, connect by the physical communication passage between the two, it is characterized in that, described PC software section and FPGA hardware components structurally are divided into three layers: lower floor, middle layer and upper strata, lower floor realizes transmission of Information on the physical channel, and the encapsulation and the decapsulation of Frame finished in the middle layer, and the input and output of respective signal value are then carried out on the upper strata; Lower floor comprises the communication port driver module of PC software section and the communication port transceiver module of FPGA hardware components, and the two connects by the physical communication passage; The middle layer comprises the frame processing module of PC software section and the adaptor module of FPGA hardware components; The upper strata comprises the DUT of excitation vectors module, response vector module and the FPGA hardware components of PC software section; Call mutually and transmission information by operation system of software or certain agreement between each layer of PC software section, the input and output port by separately between each layer of FPGA hardware components interconnects.
2, a kind of software and hardware cooperating simulation/verification system according to claim 1 is characterized in that, replaces excitation vectors module, the response vector module of described PC software section with the behavioral scaling describing module, replaces a DUT with net table level functional module; And between the upper strata of PC software section and middle layer, increase the VPI/PLI interface.
3, a kind of software and hardware cooperating simulation/verification system according to claim 1 is characterized in that, replaces excitation vectors module, the response vector module of described PC software section with the behavioral scaling describing module, replaces a DUT with net table level functional module; And close at the PC software section and to increase the SCE-MI standard interface between the middle layer of FPGA hardware components and the lower floor.
4, a kind of software and hardware cooperating simulation/verification system according to claim 1 is characterized in that, the frame processing module of described PC software section can adopt the C/C++ high-level language programs to realize; The communication port driver module of described PC software section can be realized by the method for calling the api function relevant with operating system.
5, a kind of software and hardware cooperating simulation/verification system according to claim 1, it is characterized in that, the communication port transceiver module of described FPGA hardware components can be realized by the interface chip of special use and the internal logic function of FPGA, and finish the connection of communication port; The adaptor module of described FPGA hardware components can be realized the adaptor module with frame handling procedure corresponding hardware side, software side by finishing the method that downloads in the hardware platform at the parsing of FPGA part achieve frame and assembling Verilog code; Described DUT module can be the realization of module to be tested in FPGA, also can be by before emulation begin, design is finished configuration to FPGA by bottom physical channel the method among the FPGA of downloading to.
6, a kind of arrow pattern software and hardware cooperating simulation/verification method is characterized in that it may further comprise the steps:
Step 1: software section is to the processing of input stimulus
Text formatting according to prior agreement, the input stimulus vector file, simultaneously, with expected result also with the agreement text formatting write file after, transfer the file in the frame handling procedure of lower floor, send it to the FPGA hardware components after handling by the frame handling procedure; Its concrete steps can be divided into following three step by step:
Step 1.1: the user finishes on the upper strata of software side the writing of input file, and it down is sent in the frame handler module;
Step 1.2: the frame handling procedure in middle layer, software side encapsulates this document after reading the file of user's input, makes it to become the input signal data frame and continue to transmit toward the channels drive program of lower floor;
Step 1.3: after the channels drive program receives the Frame that transmits on the upper strata,, Frame is mail to the hardware FPGA emulator by the bottom physical channel by calling the API relevant with the operating system of current operation;
Step 2: hardware components receives excitation and output response
After the FPGA hardware components receives the data that transmit software side, data are analyzed, it is kept in the storer of FPGA with expected results, and input signal is sent to DUT, the result that then will export response and preservation after the output response of collecting DUT compares, and delivers in the bottom communication passage transceiver module after at last output response signal and/or comparing result being encapsulated and sends to software side; Its concrete steps can be divided into following five step by step:
After the communication port transceiver module of step 2.1:FPGA hardware components receives the Frame of input signal from the bottom physical channel, transfer them in the adaptor module on upper strata;
Step 2.2: adaptor module is by after carrying out decapsulation to the Frame that receives, data are analyzed, the result partly is kept in the storer of FPGA with the output of the expection in the data, produces the pumping signal of excitation files specify in addition, and the input end of input upper strata DUT;
Step 2.3:DUT calculates according to input signal values, produces output response signal and output;
Step 2.4: adaptor module is collected the output response signal that is produced by DUT from the output terminal of DUT, and itself and the expected results that is kept in the storer directly compared at hardware components, after then output response signal and/or comparing result being packaged into Frame, be transferred in lower floor's communication port transceiver module;
Step 2.5: the Frame that the communication channel transceiver module transmits the upper strata mails to software side by the bottom physical channel;
Step 3: software section is to the reception of response signal
After software side receives the output response signal Frame that hardware sends over, upwards be submitted to the frame handling procedure on upper strata, save as the output response file at last after treatment or directly present DUT operation result after utilizing hardware-accelerated contrast to the user;
Step 4: repeating step 1 is to step 3, until emulation/checking of finishing whole DUT.
7, a kind of arrow pattern software and hardware cooperating simulation/verification method according to claim 6, during its feature, in 1.2 the encapsulation process step by step of described step 1, whether can select to need hardware components to return concrete comparing result by the mode that zone bit is set: if only need to be judged the function correctness of DUT, then whether hardware side only need return 0/1 and represent function correct; Concrete if desired contrast conclusion, then hardware side still can return detailed error message.
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