CN116451617A - Information processing method, device and application based on simulation waveform in chip simulation - Google Patents
Information processing method, device and application based on simulation waveform in chip simulation Download PDFInfo
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Abstract
The invention discloses an information processing method, device and application based on simulation waveforms in chip simulation, and relates to the technical field of chip development. The method comprises the following steps: acquiring an IP-level simulation waveform file of the tested IP module; analyzing the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the change information of the bus transmission state along with time, and judging whether to trigger code conversion operation according to the change of the bus transmission state; when code conversion operation is triggered, corresponding bus configuration information is obtained according to the current bus transmission state, and corresponding SoC-level test case codes are formed, wherein the SoC-level test case codes are used for SoC interface bus configuration of the tested IP module. The invention realizes the automatic conversion of interface bus configuration of test cases in different verification environments, and can improve the efficiency of transplanting the test cases in the IP level verification environment, thereby shortening the chip research and development period.
Description
Technical Field
The present invention relates to the field of chip development technologies, and in particular, to an information processing method, apparatus and application based on simulation waveforms in chip simulation.
Background
One large-scale system chip SoC (System on Chip) generally includes a circuit portion that a chip designer designs autonomously and an outsourced IP module, also called an IP Core, which is a mature design of circuit modules in the chip with independent functions, such as DSP (digital signal processor) modules, DRAM (dynamic random access memory) modules, USB modules, etc., with interconnections between the IP modules being made through on-chip buses. The use of the IP module can shorten the design period and improve the success rate of chip design. Correspondingly, the functional verification design of SoC chips is also generally divided into two parts: IP (Intellectual Property) level verification (also called module level verification) and SoC level verification (also called chip level verification or chip level verification), and the simulation verification needs to build an IP level verification environment and an SoC level verification environment respectively. The IP level verification environment is mainly used for simulating and verifying the functions of the independent IP modules, and the SoC level verification environment is mainly used for verifying whether the IP modules can normally work in the whole chip system and accords with expected results. In the actual chip simulation verification process, some outsourced IP modules also typically need to perform the two levels of verification.
Common IP level verification is typically a register interface using UVM (Universal Verification Methodology ) bus stimulus control IP, a test machine may include a bus stimulus sequence of an IP under test, a VIP (verification IP) tool, and a bus function model that operates at a clock frequency generated by the test machine to drive the IP under test (DUT) and VIP interactions, through which the function of the IP under test is checked for correctness. Currently, IP core vendors typically provide an IP level verification environment for IP cores to verify personnel to perform IP level verification on the IP core design.
However, since the code of the verification environment provided by some manufacturers is generally encrypted, the verification personnel can only run the verification simulation environment, but cannot change the code information, and cannot directly perform test case migration (Porting). If a verifier needs to migrate a simulation test case (case test, a series of codes written to verify the function or performance of a test item) in an IP level verification environment to an SoC level verification environment, the current common practice in the industry is: according to the test case information visible in the IP level verification simulation environment, verification personnel disassemble the detail information of the test cases provided in the IP level verification simulation environment, then describe the detail information again by using the System Verilog language to form test cases capable of running in the SoC level verification environment, and the rewritten test cases are added into a test case set of a test System. In the information analysis and recompilation work of simulation test cases, it is one of important works to analyze and rewrite bus information (to convert the bus information of IP level test cases into the bus information of SoC level test cases), and the time consumption of manual analysis and rewriting is large, resulting in low efficiency of test case migration and affecting the whole development cycle of the chip.
Disclosure of Invention
The invention aims at: the method, the device and the application for processing the information based on the simulation waveform in the chip simulation are provided for overcoming the defects of the prior art. According to the invention, through analyzing the simulation waveform file obtained by the IP level verification, the corresponding bus configuration information is automatically identified according to the simulation waveform file and converted to form the test case code for the SoC level verification environment, the automatic conversion of the interface bus configuration of the test cases in different verification environments is realized, and the processing efficiency of transplanting the test cases in the IP level verification environment into the SoC level verification environment can be improved, so that the chip research and development period can be shortened.
In order to achieve the above object, the present invention provides the following technical solutions:
an information processing method based on simulation waveforms in chip simulation comprises the following steps:
acquiring an IP level simulation waveform file obtained after an IP level test case of a tested IP module is executed in an IP level UVM verification environment, wherein the IP level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the IP level test case;
analyzing the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the change information of the bus transmission state along with time, and judging whether to trigger code conversion operation according to the change of the bus transmission state;
when code conversion operation is triggered, corresponding bus configuration information is obtained according to the current bus transmission state, and the bus configuration information is described by using a System Verilog language to form corresponding SoC level test case codes, wherein the SoC level test case codes are used for SoC interface bus configuration of the tested IP module.
Further, the tested IP module is a processor IP module, a memory IP module, an input/output I/O interface IP module or other special function IP modules.
Further, the name and bus type of the tested IP module are recorded in the simulation waveform file.
Further, the connection bus of the tested IP module is an advanced peripheral bus APB bus, and at this time, the step of determining whether to trigger the transcoding operation is as follows:
analyzing a bus clock signal PCLK, a bus strobe signal PSEL and an enable control signal PENABLE in the APB bus transmission signal to obtain the change information of the bus transmission state along with time;
when the bus transmission state is the read-write transmission state, the code conversion operation is triggered.
Further, when the bus transmission state is a write transmission state, after the bus address and the write data corresponding to the write operation are obtained according to the bus address signal PADDR and the bus write data signal PWDATA, the corresponding bus configuration information is described by using the System Verilog language to form a corresponding SoC level test case code, and the code is added into the corresponding SoC level test case of the tested IP module;
when the bus transmission state is the read transmission state, acquiring read data information corresponding to the read operation according to the bus address signal PADR and the bus read data signal PRDATA, describing corresponding bus configuration information by using a System Verilog language to form a corresponding SoC level test case code, and adding the code into a corresponding SoC level test case of the tested IP module.
Further, the method also comprises a verification step of interface bus configuration conversion, which comprises the following steps:
recording occurrence time points and times of bus transmission states triggering code conversion operation aiming at the IP level simulation waveform file, and generating a first table file based on the occurrence time points and times; the method comprises the steps of,
according to the SoC level simulation waveform file obtained after the SoC level test case is executed in the SoC level UVM verification environment, the SoC level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the SoC level test case, analysis is carried out on the SoC level simulation waveform file to obtain change information of a bus transmission state along with time, whether code conversion operation is triggered or not is judged according to the change of the bus transmission state, occurrence time points and times of the bus transmission state triggering the code conversion operation are recorded, and a second table file is generated;
comparing the first table file with the second table file, and judging whether the recorded contents of the first table file and the second table file are consistent;
when it is determined that the content is inconsistent, the inconsistent content is identified in the first table file and the second table file and/or an error prompt is output.
The invention also provides an information processing device based on simulation waveforms in chip simulation, which comprises the following structures:
the information acquisition module is used for acquiring an IP-level simulation waveform file obtained after the IP-level test case of the tested IP module is executed in an IP-level UVM verification environment, wherein the IP-level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the IP-level test case;
the waveform file analysis module analyzes the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the time-dependent change information of the bus transmission state, and judges whether to trigger code conversion operation according to the change of the bus transmission state;
and the code conversion module is used for obtaining corresponding bus configuration information according to the current bus transmission state when code conversion operation is triggered, describing the bus configuration information by using a System Verilog language to form corresponding SoC-level test case codes, wherein the SoC-level test case codes are used for SoC interface bus configuration of the tested IP module.
The invention also provides a method for carrying out case transplanting in the chip simulation, which comprises the step of converting the IP interface bus configuration of the IP module into the SoC interface bus configuration, wherein the automatic conversion of the interface bus configuration is carried out according to the method.
The invention also provides a chip test system, which comprises a case transplanting device for converting the test cases in the IP level UVM verification environment of the IP module into the test cases in the SOC level UVM verification environment, wherein the case transplanting device is configured to automatically convert the interface bus configuration by the method.
Further, the IP level UVM verification environment interacts with the IP module to be tested through an IP interface module, and module level function verification is carried out on the IP module through an IP level test case; and the SOC-level UVM verification environment interacts with the IP module to be tested in the chip to be tested through the SOC interface module, and verifies the functions of the IP module to be tested in the chip to be tested through the SOC-level test case obtained through conversion.
Compared with the prior art, the invention has the following advantages and positive effects by taking the technical scheme as an example: according to the invention, through analyzing the simulation waveform file obtained by the IP level verification, the corresponding bus configuration information is automatically identified according to the simulation waveform file and converted to form the test case code for the SoC level verification environment, the automatic conversion of the interface bus configuration of the test cases in different verification environments is realized, and the processing efficiency of transplanting the test cases in the IP level verification environment into the SoC level verification environment can be improved, so that the chip research and development period can be shortened.
Drawings
Fig. 1 is a schematic diagram of bus transmission signals recorded in a simulation waveform file according to an embodiment of the present invention.
Fig. 2 is a logic diagram of triggering code conversion according to a bus transmission state according to an embodiment of the present invention.
Fig. 3 is a verification flow chart of interface bus configuration conversion according to an embodiment of the present invention.
Fig. 4 is an information output schematic diagram of a first table file according to an embodiment of the present invention.
Fig. 5 is an information output schematic diagram of a second table file according to an embodiment of the present invention.
Description of the embodiments
The method, the device and the application for processing the information based on the simulation waveform in the chip simulation disclosed by the invention are further described in detail below with reference to the accompanying drawings and the specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be regarded as being isolated, and they may be combined with each other to achieve a better technical effect. In the drawings of the embodiments described below, like reference numerals appearing in the various drawings represent like features or components and are applicable to the various embodiments. Thus, once an item is defined in one drawing, no further discussion thereof is required in subsequent drawings.
It should be noted that the structures, proportions, sizes, etc. shown in the drawings are merely used in conjunction with the disclosure of the present specification, and are not intended to limit the applicable scope of the present invention, but rather to limit the scope of the present invention. The scope of the preferred embodiments of the present invention includes additional implementations in which functions may be performed out of the order described or discussed, including in a substantially simultaneous manner or in an order that is reverse, depending on the function involved, as would be understood by those of skill in the art to which embodiments of the present invention pertain.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.
Examples
In the design of a system-on-chip SoC, the interconnection between the integrated IP modules is realized by an on-chip bus. Buses are communication links that convey information between various functional components of a computer (operators, controllers, memories, inputs, outputs, etc.). Conventional on-chip buses, such as AMBA (Advanced Microcontroller Bus Architecture) buses, AMBA facilitate modular design, reusability, compatibility, and scalability of IP modules. In the AMBA bus specification, different types of buses are defined that can be used in combination, including: advanced high performance bus AHB, advanced system bus ASB, advanced peripheral bus APB, advanced extensible interface AXI bus, etc.
In the design and development process of an AMBA bus architecture type SoC chip (i.e., the SoC chip adopts an AMBA bus as a bus architecture for on-chip communication), performance verification (i.e., soC-level verification of an IP module) is generally performed on an IP module in a tested chip through a UVM verification environment. The IP module is hung on an on-chip bus (such as an APB bus), and when the simulation verification is performed, the read-write operation parameter information of the bus (or called interface bus) data of the IP module is configured to perform the function verification of the IP module, and the bus configuration information forms a corresponding test case code. When EDA simulation is performed with test case codes, the simulation results are typically saved in the form of a simulation waveform, such as a FSDB (Fast Signal Data Base) waveform.
Accordingly, the invention provides an information processing method based on simulation waveforms in chip simulation, which comprises the following steps:
s100, obtaining a simulation waveform file obtained after an IP level test case of the tested IP module is executed in an IP level UVM verification environment, wherein the simulation waveform file is called an IP level simulation waveform file, and the simulation time sequence information and bus transmission signals of the IP level test case are recorded in the IP level simulation waveform file.
S200, analyzing the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the time-dependent change information of the bus transmission state, and judging whether to trigger code conversion operation according to the change of the bus transmission state.
And S300, when code conversion operation is triggered, obtaining corresponding bus configuration information according to the current bus transmission state, and describing the bus configuration information by using a System Verilog language to form corresponding SoC-level test case codes, wherein the SoC-level test case codes are used for SoC interface bus configuration of the tested IP module.
In this embodiment, the tested IP module may be a processor IP module, a memory IP module, an I/O interface IP module, or other special function IP modules. By way of example and not limitation, the processor IP block, such as may be a DSP block; the memory IP module may be, for example, a DRAM module; the input/output I/O interface IP module can be a USB module, a UART module and the like; the other special function IP module may be, for example, an ADC module, a DAC module, a PLL module, etc.
And the name of the tested IP module and the bus type of the tested IP module are also recorded in the simulation waveform file. The bus type of the tested IP module may be, for example, an advanced high performance bus AHB, an advanced system bus ASB, an advanced peripheral bus APB, or an advanced extensible interface AXI bus.
As a typical mode, for example, the IP module to be tested is a USB module, an interface bus of the USB module is an APB bus (the APB bus is mainly used for connection of low-bandwidth peripheral peripherals), and a certain test case a in the IP level UVM verification environment is used for performing verification test on the USB module to obtain a simulation result file, the simulation result is stored in a waveform mode, and recorded APB bus transmission signals are shown in fig. 1. In fig. 1, PCLK represents a bus clock signal, PSEL represents a bus strobe signal, PADDR represents a bus address signal, penble represents an enable signal, and PWDATA represents bus write data.
The read data bus and the write data bus on the APB bus are separated and initialized to IDLE state, where no transfer operation is performed and no module is selected. When there is a transmission to be made, psel=1, penable=0, enter the SETUP state, and stay in the SETUP state for only one period. When the next rising edge of PCLK arrives, the ENABLE state is entered. Upon entering the ENABLE state, PADDR, PSEL, PWRITE, which was previously in the SETUP state, is maintained unchanged and PENABLE is set to 1. The transfer will only remain in the ENABLE state for one cycle, and will be completed after the SETUP and ENABLE states have passed. Then if no transmission is to be carried out, entering an IDLE state for waiting; if there is a continuous transmission, the SETUP state is entered.
The data transfer of the APB bus includes write transfer and read transfer, corresponding to a write transfer state and a read transfer state, respectively. The write transfer begins with all changes in address, write data, write signals, and select signals after the rising edge of the clock. The timing of the signals during a read transfer is the same as during a write, in which the slave must provide data during the ENABLE cycle, the data being sampled at the clock rising edge at the end of the ENABLE. By analyzing the bus transmission signal of the APB bus, the change information of the bus transmission state along with time can be obtained. Such as the APB bus transfer signal illustrated in fig. 1, which has 2 write transfer states, corresponding to 2 write transfer operations, in the T1-T3 and T4-T6 periods, respectively. The 1 st write transfer operation is that the CPU writes data date1 to address addr1, and the 2 nd write transfer operation is that the CPU writes data date2 to address addr 2.
In this embodiment, whether to trigger the transcoding operation may be determined according to the foregoing change of the bus transmission status. Taking the APB bus as an example of a typical manner, the specific steps for determining whether to trigger the transcoding operation may be as follows: analyzing a bus clock signal PCLK, a bus strobe signal PSEL and an enable control signal PENABLE in the APB bus transmission signal to obtain the change information of the bus transmission state along with time; when the bus transmission state is the read-write transmission state, the code conversion operation is triggered. When the code conversion operation is triggered, corresponding bus configuration information can be obtained according to the current bus transmission state (either a write transmission state or a read transmission state), and the bus configuration information is described by using a System Verilog language to form corresponding SoC level test case codes, wherein the SoC level test case codes are used for SoC interface bus configuration of the tested IP module.
Specifically, when the bus transmission state is the write transmission state, the bus address and the write data corresponding to the write operation can be obtained according to the bus address signal PADDR and the bus write data signal PWDATA, and then the corresponding bus configuration information is described by using the System Verilog language to form a corresponding SoC level test case code, and the code is added into the corresponding SoC level test case of the tested IP module.
When the bus transmission state is the read transmission state, the read data information corresponding to the read operation can be obtained according to the bus address signal PADR and the bus read data signal PRDATA, then the corresponding bus configuration information is described by using the System Verilog language to form a corresponding SoC level test case code, and the code is added into the corresponding SoC level test case of the tested IP module.
By way of example and not limitation, taking the APB bus transfer signal illustrated in fig. 1 as an example, the identified bus transfer states include 3 states: state 1, no PSEL (psel=0) is detected at the time of the PCLK clock rising edge, being an IDLE state; state 2, PSEL is detected at the rising edge of the PCLK clock, where PSEL=1 and PENABLE=0, and is in SETUP state; state 3: when PSEL is high, PENABLE is detected at the next rising edge of PCLK clock, where psel=1 and penable=1 are in the write transfer state. The transcoding operation is triggered at state 3.
The transition from state 1 to state 2 to state 3 to state 1 may be a cyclic state jump process, with the transcoding operation being triggered only when state 3. When the transcoding operation is triggered, corresponding bus configuration information can be obtained according to the current writing transmission state, and the bus configuration information is described by using a System Verilog language to form corresponding SoC level test case codes, for example, the SoC level test case codes obtained by recognition and conversion according to the simulation waveforms shown in fig. 1 are as follows:
CPU_write(addr1，date1)；
CPU_write(addr2，date2)；
the corresponding bus configuration information is:
the CPU writes data date1 to the address addr 1;
the CPU writes data date2 to address addr 2.
Referring to fig. 3, in another implementation manner of this embodiment, a verification step of interface bus configuration conversion may further be included, which may specifically be as follows:
recording the occurrence time point and the number of times of the bus transmission state triggering the code conversion operation aiming at the IP level simulation waveform file, namely the IP level verification simulation waveform file, and generating a first table file based on the occurrence time point and the number of times; according to the SoC level simulation waveform file obtained after the SoC level test case is executed in the SoC level UVM verification environment, the SoC level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the SoC level test case, analysis is conducted on the SoC level simulation waveform file to obtain change information of a bus transmission state along with time, whether code conversion operation is triggered or not is judged according to the change of the bus transmission state, occurrence time points and times of the bus transmission state triggering the code conversion operation are recorded, and a second table file is generated; comparing the first table file with the second table file, and judging whether the recorded contents of the first table file and the second table file are consistent; when it is determined that the content is inconsistent, the inconsistent content is identified in the first table file and the second table file and/or an error prompt is output.
By way of example and not limitation, such as the first table file being generated as shown in fig. 4, the second table file being generated as shown in fig. 5, the occurrence time points and the number of times of state 3 (bus transfer state that triggered the transcoding operation) recorded in fig. 4 and 5 are inconsistent-the corresponding state 3 time points are different at the time of number 2, and then the inconsistent contents are marked with boxes at the first table file and the second table file to prompt the user for verification of the conversion information.
The invention also provides an information processing device based on the simulation waveform in the chip simulation.
The information processing device comprises an information acquisition module, a waveform file analysis module and a code conversion module.
The information acquisition module is used for acquiring an IP-level simulation waveform file obtained after the IP-level test case of the tested IP module is executed in an IP-level UVM verification environment, wherein the IP-level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the IP-level test case.
The waveform file analysis module analyzes the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the time-dependent change information of the bus transmission state, and judges whether to trigger code conversion operation according to the change of the bus transmission state.
And the code conversion module is used for obtaining corresponding bus configuration information according to the current bus transmission state when code conversion operation is triggered, describing the bus configuration information by using a System Verilog language to form corresponding SoC-level test case codes, wherein the SoC-level test case codes are used for SoC interface bus configuration of the tested IP module.
The tested IP module can be a processor IP module, a memory IP module, an input/output I/O interface IP module or other special function IP modules.
The name and bus type of the tested IP module can be recorded in the simulation waveform file.
Preferably, when the connection bus of the tested IP module is an advanced peripheral bus APB bus, the step of determining whether to trigger the transcoding operation is as follows: analyzing a bus clock signal PCLK, a bus strobe signal PSEL and an enable control signal PENABLE in the APB bus transmission signal to obtain the change information of the bus transmission state along with time; when the bus transmission state is the read-write transmission state, the code conversion operation is triggered.
Preferably, the information processing apparatus may further include a verification module.
The verification module is configured to: recording occurrence time points and times of bus transmission states triggering code conversion operation aiming at the IP level simulation waveform file, and generating a first table file based on the occurrence time points and times; according to the SoC level simulation waveform file obtained after the SoC level test case is executed in the SoC level UVM verification environment, the SoC level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the SoC level test case, analysis is conducted on the SoC level simulation waveform file to obtain change information of a bus transmission state along with time, whether code conversion operation is triggered or not is judged according to the change of the bus transmission state, occurrence time points and times of the bus transmission state triggering the code conversion operation are recorded, and a second table file is generated; comparing the first table file with the second table file, and judging whether the recorded contents of the first table file and the second table file are consistent; when it is determined that the content is inconsistent, the inconsistent content is identified in the first table file and the second table file and/or an error prompt is output.
Other technical features are referred to the previous embodiments and will not be described here again.
In another embodiment of the present invention, a method for performing case migration in chip emulation is provided, which includes a step of converting an IP interface bus configuration of an IP module into an SoC interface bus configuration, where automatic conversion of the interface bus configuration is performed according to the foregoing method.
Other technical features are referred to the previous embodiments and will not be described here again.
In another embodiment of the present invention, there is provided a chip test system including a case migration apparatus for converting a test case in an IP level UVM verification environment of an IP module into a test case in an SOC level UVM verification environment, the case migration apparatus being configured to perform automatic conversion of an interface bus configuration by the foregoing method.
The IP level UVM verification environment interacts with the IP module to be tested through the IP interface module, and the IP module is subjected to module level function verification through the IP level test case.
And the SOC-level UVM verification environment interacts with the IP module to be tested in the chip to be tested through the SOC interface module, and verifies the functions of the IP module to be tested in the chip to be tested through the SOC-level test case obtained through conversion.
Specifically, the IP level UVM verification environment and the SOC level UVM verification environment are built by using the UVM and System Verilog languages of a general verification methodology.
The IP level UVM verification environment may include test cases and the following components: referring to the model Reference model, an input agent in_agent, an output agent out_agent, and a scoreboard. The input agent In_agent is used for encapsulation and instantiation of sequencer sequencers, driver drivers, and monitor monitors. The sequencer is used to manage the sequencer and generate the valid sequence. Wherein the sequencer sequence is used to generate a transaction, which is used to define a basic item data packet. The driver is used for applying test excitation and data conversion to the IP module. The monitor is used for collecting output data of the IP module and converting the data. The output agent Out agent also comprises a monitor for collecting the output data of the IP module after the stimulus is applied. The score board is connected with the Reference model and is used for comparing the output data collected by the monitor of the output agent with the expected value of the Reference model and outputting the comparison result.
The IP level UVM verification environment can also comprise a testbench top file, which is used for realizing the initialization and connection operation of the whole UVM verification environment, and executing test cases is started through a run_test function during test.
The SOC level UVM verification environment is isomorphic (adopting the same structure) with the IP level UVM verification environment, and also comprises a test case test and the components: reference model, input agent In agent, output agent Out agent, and scoreboard. The SOC-level UVM verification environment can also comprise a testbench top file, and the testbench top file is used for realizing the initialization and connection operation of the whole UVM verification environment, and a test case is started and executed through a run_test function during test. The construction of the UVM verification environment, the configuration of the verification components, and the data processing may refer to the prior art, and will not be described herein.
The technical features of the automatic conversion of the interface bus configuration are referred to the previous embodiments and will not be described in detail here.
In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the components may be selectively and operatively combined in any number within the scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be construed by default as inclusive or open-ended, rather than exclusive or closed-ended, unless expressly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Common terms found in dictionaries should not be too idealized or too unrealistically interpreted in the context of the relevant technical document unless the present disclosure explicitly defines them as such. Any alterations and modifications of the present invention, which are made by those of ordinary skill in the art based on the above disclosure, are intended to be within the scope of the appended claims.
Claims (10)
1. An information processing method based on simulation waveforms in chip simulation is characterized by comprising the following steps:
acquiring an IP level simulation waveform file obtained after an IP level test case of a tested IP module is executed in an IP level UVM verification environment, wherein the IP level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the IP level test case;
analyzing the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the change information of the bus transmission state along with time, and judging whether to trigger code conversion operation according to the change of the bus transmission state;
when code conversion operation is triggered, corresponding bus configuration information is obtained according to the current bus transmission state, and the bus configuration information is described by using a System Verilog language to form corresponding SoC level test case codes, wherein the SoC level test case codes are used for SoC interface bus configuration of the tested IP module.
2. The method according to claim 1, characterized in that: the tested IP module is a processor IP module, a memory IP module, an input/output I/O interface IP module or other special function IP modules.
3. The method according to claim 1, characterized in that: and the name and the bus type of the tested IP module are also recorded in the simulation waveform file.
4. The method according to claim 1, characterized in that: the connection bus of the tested IP module is an advanced peripheral bus APB bus, and at the moment, the step of judging whether to trigger code conversion operation is as follows:
analyzing a bus clock signal PCLK, a bus strobe signal PSEL and an enable control signal PENABLE in the APB bus transmission signal to obtain the change information of the bus transmission state along with time;
when the bus transmission state is the read-write transmission state, the code conversion operation is triggered.
5. The method according to claim 4, wherein: when the bus transmission state is a writing transmission state, after the bus address and the writing data corresponding to the writing operation are obtained according to the bus address signal PADDR and the bus writing data signal PWDATA, the corresponding bus configuration information is described by using the System Verilog language to form a corresponding SoC level test case code, and the code is added into the corresponding SoC level test case of the tested IP module;
when the bus transmission state is the read transmission state, acquiring read data information corresponding to the read operation according to the bus address signal PADR and the bus read data signal PRDATA, describing corresponding bus configuration information by using a System Verilog language to form a corresponding SoC level test case code, and adding the code into a corresponding SoC level test case of the tested IP module.
6. The method of claim 1, further comprising the step of verifying interface bus configuration transitions as follows:
recording occurrence time points and times of bus transmission states triggering code conversion operation aiming at the IP level simulation waveform file, and generating a first table file based on the occurrence time points and times; the method comprises the steps of,
according to the SoC level simulation waveform file obtained after the SoC level test case is executed in the SoC level UVM verification environment, the SoC level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the SoC level test case, analysis is carried out on the SoC level simulation waveform file to obtain change information of a bus transmission state along with time, whether code conversion operation is triggered or not is judged according to the change of the bus transmission state, occurrence time points and times of the bus transmission state triggering the code conversion operation are recorded, and a second table file is generated;
comparing the first table file with the second table file, and judging whether the recorded contents of the first table file and the second table file are consistent;
when it is determined that the content is inconsistent, the inconsistent content is identified in the first table file and the second table file and/or an error prompt is output.
7. An information processing device based on simulation waveforms in chip simulation is characterized by comprising the following structures:
the information acquisition module is used for acquiring an IP-level simulation waveform file obtained after the IP-level test case of the tested IP module is executed in an IP-level UVM verification environment, wherein the IP-level simulation waveform file is recorded with simulation time sequence information and bus transmission signals of the IP-level test case;
the waveform file analysis module analyzes the bus transmission signals according to the simulation time sequence of the IP level test case to obtain the time-dependent change information of the bus transmission state, and judges whether to trigger code conversion operation according to the change of the bus transmission state;
and the code conversion module is used for obtaining corresponding bus configuration information according to the current bus transmission state when code conversion operation is triggered, describing the bus configuration information by using a System Verilog language to form corresponding SoC-level test case codes, wherein the SoC-level test case codes are used for SoC interface bus configuration of the tested IP module.
8. The method for carrying out case transplanting in the chip simulation comprises the step of converting the IP interface bus configuration of the IP module into the SoC interface bus configuration, and is characterized in that: the method according to any of claims 1-6, wherein the automatic switching of the interface bus configuration is performed.
9. A chip testing system, characterized by: comprising case migration means for converting test cases in an IP level UVM verification environment of an IP module into test cases in an SOC level UVM verification environment, the case migration means being configured for automatic conversion of interface bus configuration by the method of any of claims 1-6.
10. A chip testing system according to claim 9, wherein: the IP level UVM verification environment interacts with the IP module to be tested through an IP interface module, and performs module level function verification on the IP module through an IP level test case; and the SOC-level UVM verification environment interacts with the IP module to be tested in the chip to be tested through the SOC interface module, and verifies the functions of the IP module to be tested in the chip to be tested through the SOC-level test case obtained through conversion.
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