CN113297017B - SOC verification system and method based on UVM - Google Patents

SOC verification system and method based on UVM Download PDF

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CN113297017B
CN113297017B CN202110495249.4A CN202110495249A CN113297017B CN 113297017 B CN113297017 B CN 113297017B CN 202110495249 A CN202110495249 A CN 202110495249A CN 113297017 B CN113297017 B CN 113297017B
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soc
chip
verification
data
driver
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CN113297017A (en
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赵燕
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Hangzhou Dewang Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Evolutionary Computation (AREA)
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  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to the technical field of chip verification, in particular to a system and a method for verifying an SOC based on UVM, comprising test excitation which is randomly generated by covering design specifications, a verification environment layer which is built by a plurality of IP_ENVs and a system-on-chip SOC based on risc-v kernels, wherein the IP_ENVs comprise a scoring board, a kernel register, a reference model, an excitation generator, a driver and a monitoring module; when the data sent to the bus by the system on chip SOC is verified, the excitation generator and the driver are closed, the driver is loaded to the risc-v kernel, the on-chip bus drives the IP module to send the data, the monitoring module collects the sent data, and the scoreboard makes a judgment of a final result. The invention has the following beneficial effects: the verification time is greatly shortened while the test flexibility is ensured.

Description

SOC verification system and method based on UVM
Technical Field
The invention relates to the technical field of chip verification, in particular to a system and a method for verifying a System On Chip (SOC) based on UVM.
Background
With the development of large-scale integrated circuits, the SOC system-on-chip integrates more and more IP modules, the complexity and integration of the chip are continuously improved, and the requirements on verification are higher and higher. The verification occupies eighty percent of time in the whole chip design work, a verification platform is quickly and accurately built, effective verification excitation is developed, and design problems are found as soon as possible, so that great challenges are brought to the verification work.
Disclosure of Invention
In order to solve the above problems, the present invention provides a system and a method for verifying SOC based on UVM.
A system for verifying SOC based on UVM comprises a test stimulus randomly generated by covering design specifications, a verification environment layer built by a plurality of IP_ENV combinations and a system-on-chip SOC based on risc-v kernel, wherein the IP_ENV comprises a score board, a kernel register, a reference model, a stimulus generator, a driver and a monitoring module,
when verifying data sent by peripheral equipment to a System On Chip (SOC), directly multiplexing a verification environment to generate and send an excitation signal, accessing a kernel register by a score board through a back door, and automatically comparing the kernel register with an expected value of a reference model to obtain a verification result;
when the data sent to the bus by the system on chip SOC is verified, the excitation generator and the driver are closed, the driver is loaded to the risc-v kernel, the on-chip bus drives the IP module to send the data, the monitoring module collects the sent data, and the scoreboard makes a judgment of a final result.
Preferably, an interface module for interfacing the system-on-chip SOC with the components is also included.
Preferably, the components communicate with each other through a TLM mechanism, and the components exchange data through data packets.
Preferably, the monitoring module comprises a first detector and a second detector;
the first detector samples data of the SOC input port of the system on a chip and packages the data into a data packet according to a protocol time sequence;
the second detector samples data of the system on chip SOC output port.
Preferably, the test stimulus comprises a C language driver and a test stimulus based on SystemVerilog, wherein the C language driver compiles an alf file, and further compiles the alf file into an executable binary program, and the executable file is written into a memory in a test case for a CPU to fetch instructions and execute, and the test stimulus based on SystemVerilog configures a verification environment layer and controls the execution of simulation.
A UVM-based SOC verification method, comprising:
when verifying data sent by peripheral equipment to a System On Chip (SOC), directly multiplexing a verification environment to generate and send an excitation signal, accessing a kernel register by a score board through a back door, and automatically comparing the kernel register with an expected value of a reference model to obtain a verification result;
when the data sent to the bus by the system on chip SOC is verified, the excitation generator and the driver are closed, the driver is loaded to the risc-v kernel, the on-chip bus drives the IP module to send the data, the monitoring module collects the sent data, and the scoreboard makes a judgment of a final result.
The invention has the following beneficial effects:
1. when verifying data sent by peripheral equipment to a System On Chip (SOC), directly multiplexing a verification environment to generate and send an excitation signal, accessing a kernel register by a score board through a back door, and automatically comparing the kernel register with an expected value of a reference model to obtain a verification result; when the data sent to the bus by the system on chip SOC is verified, the excitation generator and the driver are closed, the driver is loaded to the risc-v kernel, the on-chip bus drives the IP module to send the data, the monitoring module collects the sent data, and the scoreboard makes a judgment of a final result. The verification environment based on the UVM platform is built, so that the verification time is greatly shortened while the testing flexibility is ensured;
2. the verification environment built in the verification process is reasonably multiplexed into the verification environment of the system-on-a-chip SOC, so that the correctness of codes is ensured, and the repeated development process of verification components is avoided.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
Fig. 1 is a schematic structural diagram of an ip_env in a UVM-based SOC verification system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a UVM-based SOC verification system according to an embodiment of the present invention;
fig. 3 is a flow chart of a UVM-based SOC verification method according to an embodiment of the present invention.
Detailed Description
The technical scheme of the present invention will be further described with reference to the accompanying drawings, but the present invention is not limited to these examples.
Example 1
The verification object in this embodiment is a high-performance low-power consumption general-purpose system on chip SOC using risc-v as a core. Within the system-on-chip SOC are buses AXI (Advanced Extensible Interface), AHB (Advanced High performance Bus), APB (Advanced Peripheral Bus). Bus AXI is an on-chip bus that is high-performance, high-bandwidth, low-latency oriented. Bus AHB is mainly used for connection between high performance modules such as CPU, DMA, DSP, etc. The bus APB is mainly used for connection between peripheral peripherals of low bandwidth, such as UART, 1284, etc.
Specifically, different IPs are connected to corresponding buses according to bus characteristics and IP performance requirements. DDR and DMA module are hung on AXI bus, USB and Ethernet IP are hung on AHB bus, IIC/UART/SPI etc. IP are hung on APB bus.
The embodiment provides an SOC verification system based on UVM, which comprises test stimulus randomly generated by a coverage design specification, a verification environment layer built by a plurality of IP layer IP_ENV combinations and an SOC of a system on a chip based on risc-v kernels. As shown in fig. 2, the ip_env includes: IP0_env, IP1_env, and IP2_env.
As shown in fig. 1, the ip_env includes an input agent in_agent, an output agent out_agent, a reference model, and a scoreboard. The input agent in_agent connects the input end of the system on chip SOC and the output agent out_agent connects the output end of the system on chip SOC. The reference model simulates the output of the system on chip SOC as the desired output of the scoreboard. The output agent out agent monitors the true output of the system on chip SOC and sends it to the scoreboard via TLM mechanism. The scoreboard compares the real output data of the system on chip SOC with the expected output of the reference model, and prints out the comparison result.
The system on chip SOC is connected to a verification environment env and the randomly generated test sequence is sent to the driver by the stimulus generator sequencer at the beginning of verification. The driver analyzes the transaction packet sent by the excitation generator sequencer and drives the input port of the DUT according to the protocol time sequence. The input port of the DUT is connected to the driver of the input agent in_agent through the interface module interface.
The input port of the system on chip SOC is connected to the first detector monitor of the input agent in_agent through the interface module interface. The first detector of the input agent in_agent samples the input port of the system on chip SOC and composes a transaction packet according to the protocol timing.
The reference model gives out an expected output behavior transaction package of the system on chip SOC according to the input transaction package of the system on chip SOC sampled by the first detector in the input agent in_agent, and the expected output behavior transaction package is used as a golden transaction of the scoreboard.
The second detector monitor in the output agent out_agent samples the output of the system on chip SOC and composes a transaction packet according to the protocol timing. This is the true output transaction of the system on chip SOC.
The scoreboard component compares the true output of the system-on-chip SOC with the golden output of the reference model, determines if the system-on-chip SOC is behaving correctly and gives a corresponding report.
In the verification platform, except for the driver, the first detector monitor and the second detector monitor which are connected through TLM (Transaction Level Modeling) by using interface buses, data exchange is performed through object-level (Transaction Level) data packets, so that the abstraction level of data is improved, and the reusability of the components is realized.
In this embodiment, the test case layer test is used to create different verification environments and generate different test incentives. And the verification environment layer ENV is used for carrying out corresponding configuration on the IP_ENV according to the configuration parameters input by the test layer.
In the UVM verification environment of the system on chip SOC, different verification requirements can be achieved by making appropriate configurations for the ip_env. When the peripheral equipment is verified to send to the function of the system on chip SOC, the verification environment layer of the IP_ENV is directly multiplexed to generate and send excitation, the scoreboard accesses a state register in the kernel through a back door, the result is automatically compared with the expected value of the reference model, and meanwhile, the hex file judges the verification result by reading the kernel register and interrupt information. When data sent to a bus by the system on chip SOC is verified, a stimulus generator sequence and a driver are closed, a driver program is loaded to an risc-v kernel, the data is sent by an on-chip bus driver IP module, an AXI_ENV is added in a verification environment layer of the system on chip SOC to monitor bus signals in the chip, the bus is packaged into an Interface module Interface, the monitoring module collects the sent data, and a scoreboard is used for judging a final result.
The test stimulus comprises a C language driver and a test stimulus based on SystemVerilog, wherein the C language driver compiles an alf file, and further compiles the alf file into an executable binary program, and the executable file is written into a memory in a test case for a CPU to take out instructions and execute, and the test stimulus based on SystemVerilog configures a verification environment layer and controls the execution of simulation.
Example two
Based on the first embodiment, a SOC verification system based on UVM is provided, and correspondingly, in terms of a method, the second embodiment provides a SOC verification method based on UVM, as shown in fig. 3, which specifically includes the following steps:
s1: when verifying data sent by peripheral equipment to a System On Chip (SOC), directly multiplexing a verification environment to generate and send an excitation signal, accessing a kernel register by a score board through a back door, and automatically comparing the kernel register with an expected value of a reference model to obtain a verification result;
s2: when the data sent to the bus by the system on chip SOC is verified, the excitation generator and the driver are closed, the driver is loaded to the risc-v kernel, the on-chip bus drives the IP module to send the data, the monitoring module collects the sent data, and the scoreboard makes a judgment of a final result.
The technical scheme and the technical effect based on the embodiment are the same as those of the hardware embodiment, so that the description is omitted.
Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.

Claims (5)

1. The system is characterized by comprising a test stimulus randomly generated by an overlay design specification, a verification environment layer built by a plurality of IP_ENVs and a system-on-a-chip SOC based on risc-v kernels, wherein the IP_ENVs comprise a score board, kernel registers, a reference model, a stimulus generator, a driver and a monitoring module;
the monitoring module comprises a first detector and a second detector; the first detector samples data of the SOC input port of the system on a chip, and packages the data into data packets according to protocol time sequence; the second detector samples data of an SOC output port of the system on a chip;
connecting the system-on-chip SOC with a verification environment layer, and transmitting a randomly generated test sequence to a driver through an excitation generator at the beginning of verification; the driver analyzes the transaction packet sent by the excitation generator and drives an input port of the DUT according to the protocol time sequence; the input port of the DUT is connected to the driver of the input agent through the interface module;
the input port of the system on chip SOC is connected to the first detector of the input agent through the interface module, and the first detector of the input agent samples the input port of the system on chip SOC and forms a transaction packet according to the protocol time sequence;
the reference model gives out an output behavior transaction package expected by the system-on-chip SOC according to the system-on-chip SOC input transaction package sampled by the first detector in the input agent, and the output behavior transaction package is used as a golden transaction of the score board;
a second detector in the output agent samples the output end of the system on chip SOC and forms a transaction packet according to a protocol time sequence;
the score board component compares the real output of the system on chip SOC with the golden output of the reference model, judges whether the system on chip SOC acts correctly and gives a corresponding report;
when verifying data sent by peripheral equipment to a System On Chip (SOC), directly multiplexing a verification environment layer to generate and send an excitation signal, accessing a kernel register by a score board through a back door, automatically comparing the kernel register with an expected value of a reference model, and judging a verification result by a hex file through reading the kernel register and interrupt information;
when data sent to a bus by the system on chip SOC is verified, the excitation generator and the driver are closed, a driver program is loaded to an risc-v kernel, an on-chip bus drives an IP module to send data, an AXI_ENV is added into a verification environment layer of the system on chip SOC to monitor bus signals in the chip, the bus is packaged into an interface module, the monitoring module collects the sent data, and a scoreboard makes a judgment of a final result.
2. The UVM based SOC verification system of claim 1, further comprising an interface module for interfacing the system-on-chip SOC with the components.
3. The UVM based SOC verification system of claim 1, wherein the components communicate with each other via a TLM mechanism, and the components exchange data via data packets.
4. The UVM-based SOC verification system of claim 1, wherein the test stimulus comprises a C language driver and a SystemVerilog-based test stimulus, the C language program is compiled into an elf file, the elf file is further compiled into an executable binary program, and the executable file is written into a memory in a test case for a CPU to fetch and execute instructions, and the SystemVerilog-based test stimulus configures a verification environment layer and controls execution of a simulation.
5. A UVM-based SOC verification method applied to the UVM-based SOC verification system of any of claims 1-4, the method comprising:
when verifying data sent by peripheral equipment to a System On Chip (SOC), directly multiplexing a verification environment to generate and send an excitation signal, accessing a kernel register by a score board through a back door, and automatically comparing the kernel register with an expected value of a reference model to obtain a verification result;
when the data sent to the bus by the system on chip SOC is verified, the excitation generator and the driver are closed, the driver is loaded to the risc-v kernel, the on-chip bus drives the IP module to send the data, the monitoring module collects the sent data, and the scoreboard makes a judgment of a final result.
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