CN115345123B - Chip verification device for hardware accelerated non-standard protocol - Google Patents
Chip verification device for hardware accelerated non-standard protocol Download PDFInfo
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Abstract
The invention relates to a chip verification device of a nonstandard protocol for hardware acceleration, which is applied to the hardware acceleration process of chip verification and comprises a first verification IP and a second verification IP, wherein the first verification IP comprises a sequence generator, a sequence driving module, a first control vector component and a first data vector component; the second verification IP comprises a second control vector component, a second data vector component and an interface module; the first verification IP is not synthesizable; the second verification IP is synthesizable; the first verification IP and the second verification IP are connected through a conversion interface; the device is connected with a design to be tested through the interface module, and the interface module comprises a control vector interface unit, an input data vector interface unit and an output data vector interface unit. The device of the invention is adaptive to all non-standard bus protocols, and can accelerate the simulation hardware in the verification process, thereby improving the efficiency and the accuracy of chip verification.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to a chip verification device of a nonstandard protocol for hardware acceleration.
Background
In the chip Verification process, a Verification IP (VIP) is usually required to be set to replace a module connected to a Design Under Test (DUT), and the DUT is verified by interacting the Verification IP with the DUT. The design to be tested can be interconnected with the module through a plurality of different protocols, and each protocol corresponds to one type of verification IP. The design to be tested and the module interconnection can be interconnected through a standard Bus protocol, and the standard Bus protocol comprises Bus protocols such as AMBA (Arm Microcontroller Bus architecture), PCI-Express (peripheral component interconnect Express) and the like. And may be interconnected via a variety of custom, non-standard bus protocols. In the prior art, verification IPs corresponding to standard bus protocols exist, but the verification IPs corresponding to non-standard bus protocols need to be designed one by one for each non-standard bus protocol, along with the fact that the design scale of chips is larger and larger, more and more non-standard bus protocol buses are involved, if one verification IP is set for each non-standard bus protocol one by one, the verification workload is huge, the verification efficiency is low, once design change occurs, the corresponding verification IPs also need to be changed one by one, the workload is large, errors are prone to occurring, the verification efficiency is low, and the accuracy cannot be guaranteed.
Disclosure of Invention
The invention aims to provide a chip verification device of a non-standard protocol for hardware acceleration, which can be suitable for all non-standard bus protocols and improves the efficiency and the accuracy of chip verification.
The invention provides a chip verification device of a nonstandard protocol for hardware acceleration, which is applied to the hardware acceleration process of chip verification and comprises a first verification IP and a second verification IP, wherein the first verification IP comprises a sequence generator, a sequence driving module, a first control vector component and a first data vector component; the second verification IP comprises a second control vector component, a second data vector component and an interface module; the first verification IP is not comprehensive; the second verification IP can be integrated; the first verification IP and the second verification IP are connected through a conversion interface; the device is connected with the design to be tested through the interface module, and the interface module comprises a control vector interface unit, an input data vector interface unit and an output data vector interface unit.
The sequence generator is used for acquiring the excitation sequence items and sending the excitation sequence items to the sequence driving module.
The sequence driving module is used for caching the excitation sequence items and distributing the excitation sequence items to a first control vector component or a first data vector component according to bus interface signals corresponding to the excitation sequence items.
And the first control vector component is used for splicing the received excitation sequence items into control vectors, converting the control structure body through a corresponding conversion interface and sending the control vectors to the second control vector component.
And the second control vector component is used for sending the control structure body to the design to be tested through the control vector interface unit.
And the first data vector component is used for splicing the received excitation sequence items into input data vectors, converting the input data vectors into an input structural body through a corresponding conversion interface, and sending the input structural body to the second data vector component.
The second data vector component is used for sending the input data vector interface unit to the design to be tested; the output data vector interface unit is used for receiving response data sent by the design to be tested, splicing the response data to generate an output data vector structural body, converting the output data vector into an output data vector through the corresponding conversion interface, and sending the output data vector to the first data vector component.
The control vector, the input data vector and the output data vector are all variable length vectors, and the vector length is related to the bus protocol.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the chip verification device for the hardware accelerated nonstandard protocol can achieve considerable technical progress and practicability, has wide industrial utilization value and at least has the following advantages:
the invention sets the universal chip verification device of the nonstandard protocol for hardware acceleration to adapt to all nonstandard bus protocols, instantiates verification IP directly based on the chip verification device of the nonstandard protocol for hardware acceleration in the chip verification process, can simulate hardware acceleration in the verification process, can improve the traditional simulation to dozens of times or even hundreds of times, and improves the efficiency and the accuracy of chip verification.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a chip verification apparatus for hardware acceleration according to a non-standard protocol according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to an embodiment of a non-standard protocol chip verification apparatus for hardware acceleration and its effects according to the present invention with reference to the accompanying drawings and preferred embodiments.
The embodiment of the invention provides a chip Verification device of a nonstandard protocol for Hardware acceleration, which is applied to a Hardware acceleration (Hardware acceleration) process, and as shown in fig. 1, the device comprises a first Verification IP (Verification IP) and a second Verification IP, wherein the first Verification IP comprises a sequence generator, a sequence driving module, a first control vector component and a first data vector component; the second authentication IP includes a second control vector component, a second data vector component, and an interface module. The first verification IP is not synthesizable; the second verification IP may be Synthesis (Synthesis). The first verification IP and the second verification IP are connected through a conversion interface, it should be noted that data in the first verification IP is Transaction data (Transaction) which cannot be integrated, and the Transaction data in the first verification IP can be converted into a structure (Struct) through the conversion interface and then transmitted to the second verification IP, and the structure can be integrated. The conversion interface can also convert the structural data of the second verification IP into transaction data, and then transmit the transaction data to the first verification IP, so that efficient communication between the first verification IP and the second verification IP is realized, and the acceleration of simulation hardware of the first verification IP is realized. The device is connected with a design to be tested through the interface module, and the interface module comprises a control vector interface unit, an input data vector interface unit and an output data vector interface unit.
The Sequence generator is used for acquiring an excitation Sequence Item (Sequence Item) and sending the excitation Sequence Item to the Sequence driving module; it should be noted that, based on the bus protocol and the interconnection relationship between the second verification IP and the design to be tested, a corresponding excitation Sequence (Sequence) is generated, the sequencer obtains the corresponding excitation Sequence from the corresponding excitation Sequence, the excitation Sequence items are Transaction data (Transaction), and each excitation Sequence item corresponds to a group of Transaction data fields (Transaction fields) and corresponds to a group of bus interface signals.
The sequence driving module is used for caching the excitation sequence items and distributing the excitation sequence items to a first control vector component or a first data vector component according to bus interface signals corresponding to the excitation sequence items; specifically, a First-in First-out (FIFO) queue may be set in the sequence driving module, so that a continuous timing sequence can be processed. And based on the bus interface signal corresponding to the excitation sequence item and the control signal or the data which can be determined as the excitation sequence item, distributing the excitation sequence item to a corresponding first control vector component or a corresponding first data vector component, forwarding a second control vector component or a second data vector component, and sending the second control vector component or the second data vector component to the design to be tested through a control vector interface unit, an input data vector interface unit or an output data vector interface unit based on a corresponding bus interface signal line.
The control signal specifically includes a valid signal or a handshake signal (e.g., a vaild, ack, ready, etc. signal) and/or a clock enable signal (e.g., a ck _ gate signal), and implements control in cooperation with data. However, the widths of control signals and data of different bus protocols are usually different, and in order to make the verification IP of the device suitable for all bus protocols, the first control vector component is used for splicing the received excitation sequence items into control vectors, converting the control structure through the corresponding conversion interface, and sending the control vectors to the second control vector component; and the second control vector component is used for sending the control structure body to the design to be tested through the control vector interface unit. The first data vector component is used for splicing the received excitation sequence items into input data vectors, converting the input data vectors into an input structural body through a corresponding conversion interface, and sending the input structural body to the second data vector component; the second data vector component is used for sending the input data vector interface unit to the design to be tested; the output data vector interface unit is used for receiving response data sent by the design to be tested, splicing the response data to generate an output data vector structure, converting the output data vector structure into an output data vector through a corresponding conversion interface, and sending the output data vector structure to the first data vector component; the control vector, the input data vector and the output data vector are variable length vectors, the variable length vectors are indefinite length vectors, and the vector length is related to a bus protocol. The embodiment of the invention can control the vector interface unit, the input data vector interface unit and the output data vector interface unit to uniformly transmit in a structure body form corresponding to the vector through the vector splicing, thereby being applicable to different non-standard bus protocols. The control vector interface unit can also be provided with a built-in protocol time sequence checking module for checking the protocol time sequence.
It should be noted that the verification IP can be used as a clock generator and a reset generator in addition to chip verification.
It should be noted that the verification IP and the simulation verification IP applied to hardware acceleration may be based on the same top layer, and different file lists are selected to generate different internal structures, so that the top layer consistently ensures the non-inductive transplantation of the verification platform, and can implement one-key switching of the verification platform from the simulation mode to the hardware acceleration mode.
As an embodiment, as shown in fig. 1, the second verification IP further includes a clock component and a reset component, and the interface module includes a clock interface unit and a reset interface unit, where:
the clock component is used for generating a clock signal and sending the clock signal to the design to be tested through the clock interface unit; the clock interface unit may be configured as an uninterrupted clock signal or as a clock gated. By configuring the clock components, various clock-related characteristics may be generated, such as frequency, duty cycle, jitter, and the like.
The reset assembly is used for generating synchronous or asynchronous reset signals and sending the synchronous or asynchronous reset signals to the design to be tested through the reset interface unit. An interface module can be influenced by a clock signal corresponding to a clock interface unit and a reset signal corresponding to the reset interface unit, a reset signal line specifically connected with the reset interface unit can be determined according to the interface module and a specific connection mode of a design to be tested, the reset signal line can be one or multiple, and the reset signal corresponding to the reset interface unit is determined based on one or multiple connected reset signal lines. It should be noted that, when the second verification IP interacts with the design to be tested, the reset signal must be synchronized with the clock signal to drive and access the design to be tested, so that for any bus protocol, a clock interface unit and a reset interface unit must be set in the verification IP. It should be noted that the Reset signal supports plug-and-play power-on Reset (POR Reset) and mid-way Reset (infight Reset)
It should be noted that, the clock component, the reset component, the first control vector component, and the first data vector component; the second control vector component and the second data vector component respectively comprise corresponding component drivers and component monitors, the component drivers of the first control vector component and the first data vector component are used for converting excitation sequence items received in the components into corresponding vectors, and the component drivers of the second control vector component and the second data vector component are used for converting the corresponding vectors into corresponding structural bodies to obtain corresponding bus interface signals, and the corresponding bus interface signals are sent to the design to be tested through corresponding interface units. The signal sent by the component driver may be successful or may fail, and the component monitor is configured to obtain a corresponding record from the corresponding interface unit, and record the corresponding interface unit and the signal actually sent by the switching interface between the first authentication IP and the second authentication IP. The clock component, the reset component, the first control vector component and the first data vector component are connected in series; the second control vector Component and the second data vector Component may be specifically configured as UVC (universal Verification Component) components of UVM.
As an embodiment, the component monitor of the clock component is used for monitoring the clock interface unit and generating a clock signal recording structure body actually sent by the clock interface unit; the component monitor of the reset component is used for monitoring the reset interface unit and generating a reset signal recording structural body actually sent by the reset interface unit; the component monitor of the second control vector component is used for monitoring the control vector interface unit, generating a control vector record structural body actually sent by the control vector interface, sending the control vector record structural body to the corresponding conversion interface and converting the control vector record structural body into a control vector record; the component monitor of the first control vector component is used for monitoring a conversion interface corresponding to the second control vector component and acquiring a control vector record; the component monitor of the second data vector component is used for monitoring the input data vector interface unit and the output data vector interface unit, generating an input data vector recording structural body and an output data vector recording structural body which are actually transmitted by the input data vector interface unit and the output data vector interface unit, sending the input data vector recording structural body and the output data vector recording structural body to corresponding conversion interfaces, and converting the conversion interfaces into input data vector records and output data vector records; the component monitor of the first data vector component is used for monitoring the conversion interface corresponding to the second data vector component, and acquiring an input data vector record and an output data vector record.
As an embodiment, the first authentication IP further comprises an authentication component; the verification component may be a score plate (Scoreboard), a Reference Model (Reference Model) or a comparator (Checker), and when the existing score plate, reference Model or comparator is applied to the verification component, the existing score plate, reference Model or comparator all fall into the protection scope of the present invention, and the specific structure of the score plate, reference Model or comparator is not described herein again. The conversion interface corresponding to the clock component is used for converting the clock signal recording structural body into a clock signal record and sending the clock signal record to the verification component; the conversion interface corresponding to the reset assembly is used for converting the reset signal recording structural body into a reset signal record and sending the reset signal record to the verification assembly; the conversion interface corresponding to the second control vector is used for converting the control vector record structure into a control vector record; the component monitor of the first control vector component is used for monitoring a conversion interface corresponding to the second control vector component, acquiring a control vector record and sending the control vector record to the verification component; the conversion interface corresponding to the second data vector is used for converting the input data vector record structure body and the output data vector record structure body into an input data vector record and an output data vector record and sending the input data vector record and the output data vector record to the verification component; the component monitor of the first data vector component is used for monitoring a conversion interface corresponding to the second data vector component, acquiring an input data vector record and an output data vector record, and sending the input data vector record and the output data vector record to the verification component; the verification component is used for verifying the design to be tested based on the clock signal record, the reset signal record, the control vector record, the input data vector record and the output data vector record, and the clock signal record, the reset signal record, the control vector record, the input data vector record and the output data vector record are transaction data.
As an embodiment, the first authentication IP further comprises a system monitor for obtaining at least one of a clock signal record, a reset signal record, a control vector record, an input data vector record, and an output data vector record for presentation. The device is divided into an application layer and a physical layer, and the sequence generator, the sequence driving module and the system monitor are arranged on the application layer; the user interacts with the device directly through the application layer. The first control vector component, the first data vector component and the second verification IP comprise a second control vector component, a second data vector component and an interface module which are arranged on the physical layer. The user need not directly to obtain data from the physical layer, directly sets up the corresponding excitation sequence through the application layer and supplies sequencer to use, directly obtains the record that each interface unit actually just sent the signal through the system monitor of application layer, has improved interactive efficiency, has promoted user experience.
The first verification IP and the second verification IP may be Slave device (Slave or Target or Completer) verification IPs or Master device (Master or Initiator or originor) verification IPs, depending on the corresponding design to be tested, if the design to be tested is a Slave device, the IP is verified as a Master device, if the design to be tested is a Master device, the IP is verified as a Slave device, and when the IP is verified as a Slave device, the first verification IP further includes a memory, the apparatus further includes a memory model, the memory is disposed at the application layer, the memory interacts with a Direct Programming Interface (DPI) of the memory model, where the memory may be a systemwverilog memory and the memory model may be a C + + model.
When the verification component is a score board, records corresponding to component monitors in the first verification IP and the second verification IP need to be sent to the score board, the output of the design to be tested also needs to be sent to the score board for comparison, the score board is usually arranged on a verification platform (Testbench), so that when the verification platform is established, a score board example needs to be arranged, an output example of the first verification IP and the second verification IP, an output example of the design to be tested, and interconnection among the score board example, the output examples of the first verification IP and the second verification IP, and the output example of the design to be tested is established, which is very complicated. Based on this, the embodiment Of the present invention improves this, where the verification component is an embedded scoreboard located In a first verification IP, the embedded scoreboard may be arranged In Order (In Order) or Out Of Order (Out Of Order) for supporting dynamic comparison Of built-In data, the embedded scoreboard includes a first interface and a second interface, the clock component, the reset component, the control vector component and/or the data vector component transmit corresponding records to the embedded scoreboard through the first interface, and the second interface is used for connecting with reference models outside the first verification IP and the second verification IP to obtain data output by the reference models and compare the data with the records obtained by the first interface. Through the design, a scoring board does not need to be arranged in the verification platform, the interconnection relation is reduced, the scoring board is directly embedded in the first verification IP, the building process of the verification platform is simplified, and the verification efficiency is improved.
The sequence driving module is also used for carrying out time sequence control on the excitation sequence items based on the bus protocol. Preferably, the bus protocol corresponding to the device of the present invention is a non-standard custom bus protocol. It is understood that the standard bus protocol may be applied, but the corresponding authentication IP of the existing standard bus protocol may also be directly used.
As an embodiment, the apparatus further comprises a configuration module for supporting flexible configuration of all functions of the apparatus.
As an embodiment, the apparatus further includes a Register abstraction model, where the Register abstraction model (RAL) is an abstraction of a Register connected to a design to be tested, the Verification IP is a Verification IP generated based on a Universal Verification Methodology (UVM), the first Verification IP further includes an Adapter (Adapter) and a Predictor (Predictor), and the Adapter is an Adapter corresponding to the bus protocol, that is, a corresponding Adapter is configured based on the corresponding bus protocol. The adapter is used for acquiring register excitation sequence items from the register abstract model, converting the register excitation sequence items into bus excitation sequence items and distributing the bus excitation sequence items to corresponding components through the sequence driving module; the predictor is used to update the register abstraction model. According to the embodiment of the invention, the adapter and the predictor are arranged in the first verification IP, so that the complexity of accessing the abstract model of the register in the verification process is reduced, and the verification efficiency is improved.
As an embodiment, a design to be tested is interconnected with a brother component module of the design to be tested through at least one bus interface, each bus interface is correspondingly provided with a group of first verification IPs and second verification IPs, each bus interface is corresponding to one bus type, each bus type is corresponding to one bus protocol and a bus interface reorganization structure, each bus interface reorganization structure comprises a plurality of bus interface signals, each bus interface signal comprises a signal direction, a signal width, a signal reset value and a signal default value, a corresponding excitation sequence is generated based on the bus interface reorganization structure, each bus interface signal corresponds to one excitation sequence item, and the sequence generator obtains the corresponding excitation sequence from the corresponding excitation sequence.
Specifically, the chip according to the embodiment of the present invention is implemented as K1 component modules (Mod) arranged in a hierarchical manner 1 ,Mod 2 ,...,Mod K1 ) And K2 Atomic Units (AU) 1 ,AT 2 ,...,AT K2 )，K1>＝1，K2>=1, atomic unit exists pre-written RTL code.
The top-level component module (chip) has no parent component module, and the atomic unit has no child component module or child atomic unit; any module Mod except the top module i1 And arbitrary atomic units AU i2 All have only one parent component module, i1 takes values from 1 to K1, and i2 takes values from 1 to K2. The parent component module comprises Mod i1 And AU i2 And is compared with Mod i1 And AU i2 One level higher.
Mod i1 Including unique identification MID of component modules i1 And Mod i1 Z1 (i 1) of the child component module and child atomic unit interconnection constitutes a module internal bus Interface (Interface) list (InI) 1 ,InI 2 ,...,InI Z1(i1) ) And Mod i1 The brother component module and the brother atom listZ2 (i 1) component module External bus Interface (External Interface) list (MExI) of meta-interconnect 1 ,MExI 2 ,...,MExI Z2(i1) )。
The chip also comprises K4 Design interconnection assemblY DIY (Design interconnection assemblY) = (X) 1 _Y 1 _CMD 1 ,X 2 _Y 2 _CMD 2 ,......，X K4 _Y K4 _CMD K4 ). Wherein, X i5 And Y i5 Belong to { Mod 1 ,Mod 2 ,...,Mod K1 ,AU 1 ,AU 2 ,...,AU K2 The value range of i5 is 1 to K4; x i5 And Y i5 Component modules or sibling atomic units of each other, or X i5 Is Y i5 Or Y as a parent building block i5 Is X i5 The parent of (a) constitutes a module. X i5 And X i6 May be the same or different; y is i5 And Y i6 May be the same or different; i6 ranges from 1 to K4.CMD i5 Belong to { IDF-ID 1 ，IDF-ID 2 ，...，IDF-IDK 3 }。
The bus Interface Description reconstruction library comprises K3 predefined bus Interface reconstruction structures IDF (Interface Description factor) = (IDF) 1 ,IDF 2 ,...,IDF K3 )，K3>And =0. Wherein, IDF i3 Including bus interface unique identification IDF-ID i3 Z4 (i 3) bus interface signals (Sig) i3 1 ,Sig i3 2 ,...,Sig i3 z4(i3) )，Sig i3 i4 Including signal direction, signal width Wid (i 3, i 4), reSeT (ReSeT) value (RST) i3i4 1 ，RST i3i4 2 ，...，RST i3i4 Wid(i3,i4) ) And a Default (Default) value (Def) i3i4 1 ，Def i3i4 2 ，...，Def i3i4 Wid(i3,i4) ). i3 is from 1 to K3, i4 is from 1 to Z4 (i 3), and Z4 (i 3) is a function of i 3. IDF-ID i3 Associated with the bus protocol type. The bus protocol types include AXI bus protocol, AHB bus protocol, APB bus protocol, PCIE bus protocol, HBM bus protocol, and SATA bus in AMBAThe device mainly aims at the nonstandard self-defined bus protocol, and the standard bus protocol can be based on the corresponding verification IP in the prior art. The signal direction may be set to an Input direction (Input), an Output direction (Output), and a bidirectional direction (InOut). The signal width Wid (i 3, i 4) is signal Sig i3 i4 The number of signal lines (Wire) used. When one of the component modules is used as a design to be tested for verification, a corresponding chip verification IP needs to be set for each external bus interface to replace a brother component module corresponding to the design to be tested to interact with the design to be tested for verification.
The invention sets the universal chip verification device of the nonstandard protocol for hardware acceleration to adapt to all nonstandard bus protocols, instantiates the verification IP directly based on the chip verification device of the nonstandard protocol for hardware acceleration in the chip verification process, can simulate hardware acceleration in the verification process, and improves the efficiency and the accuracy of chip verification.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A chip verification device for hardware accelerated non-standard protocol is characterized in that,
the device comprises a first verification IP and a second verification IP, wherein the first verification IP comprises a sequence generator, a sequence driving module, a first control vector component and a first data vector component; the second verification IP comprises a second control vector component, a second data vector component and an interface module; the first verification IP is not synthesizable; the second verification IP is synthesizable; the first verification IP and the second verification IP are connected through a conversion interface; the data in the first verification IP is transaction data which cannot be integrated, the transaction data of the first verification IP is converted into a structural body through a conversion interface, and then the structural body is transmitted to the second verification IP, and the structural body can be integrated; the device is connected with a design to be tested through the interface module, and the interface module comprises a control vector interface unit, an input data vector interface unit and an output data vector interface unit;
the sequence generator is used for acquiring excitation sequence items and sending the excitation sequence items to the sequence driving module;
the sequence driving module is used for caching the excitation sequence items and distributing the excitation sequence items to a first control vector component or a first data vector component according to bus interface signals corresponding to the excitation sequence items;
the first control vector component is used for splicing the received excitation sequence items into control vectors, converting the control structure through a corresponding conversion interface and sending the control vectors to the second control vector component;
the second control vector component is used for sending the control structure body to a design to be tested through a control vector interface unit;
the first data vector component is used for splicing the received excitation sequence items into input data vectors, converting the input data vectors into an input structural body through a corresponding conversion interface, and sending the input structural body to the second data vector component;
the second data vector component is used for sending the input data vector interface unit to the design to be tested; the output data vector interface unit is used for receiving response data sent by the design to be tested, splicing the response data to generate an output data vector structure, converting the output data vector structure into an output data vector through a corresponding conversion interface, and sending the output data vector structure to the first data vector component; the control vector, the input data vector and the output data vector are all variable length vectors, and the vector length is related to the bus protocol.
2. The apparatus of claim 1,
the second verification IP further comprises a clock component and a reset component, the interface module comprises a clock interface unit and a reset interface unit, wherein,
the clock component is used for generating a clock signal and sending the clock signal to the design to be tested through the clock interface unit;
the reset assembly is used for generating synchronous or asynchronous reset signals and sending the synchronous or asynchronous reset signals to the design to be tested through the reset interface unit.
3. The apparatus of claim 2,
the clock component is also used for monitoring the clock interface unit and generating a clock signal recording structure body actually sent by the clock interface unit;
the reset assembly is also used for monitoring the reset interface unit and generating a reset signal recording structure body actually sent by the reset interface unit;
the second control vector component is also used for monitoring the control vector interface unit, generating a control vector record structural body actually sent by the control vector interface, sending the control vector record structural body to the corresponding conversion interface and converting the control vector record structural body into a control vector record;
the first control vector component is also used for monitoring a conversion interface corresponding to the second control vector component and acquiring a control vector record;
the second data vector component is also used for monitoring the input data vector interface unit and the output data vector interface unit, generating an input data vector recording structural body and an output data vector recording structural body which are actually transmitted by the input data vector interface unit and the output data vector interface unit, sending the input data vector recording structural body and the output data vector recording structural body to corresponding conversion interfaces, and converting the conversion interfaces into input data vector records and output data vector records;
the first data vector component is also used for monitoring a conversion interface corresponding to the second data vector component and acquiring an input data vector record and an output data vector record;
the clock signal record, reset signal record, control vector record, input data vector record, and output data vector record are transaction data.
4. The apparatus of claim 3,
the first authentication IP further comprises an authentication component;
the conversion interface corresponding to the clock component is used for converting the clock signal recording structural body into a clock signal record and sending the clock signal record to the verification component;
the conversion interface corresponding to the reset assembly is used for converting the reset signal recording structure into a reset signal record and sending the reset signal record to the verification assembly;
the conversion interface corresponding to the second control vector is used for converting the control vector record structure into a control vector record;
the first control vector component is also used for monitoring a conversion interface corresponding to the second control vector component, acquiring a control vector record and sending the control vector record to the verification component;
the conversion interface corresponding to the second data vector is used for converting the input data vector record structure body and the output data vector record structure body into an input data vector record and an output data vector record and sending the input data vector record and the output data vector record to the verification component;
the first data vector component is also used for monitoring a conversion interface corresponding to the second data vector component, acquiring an input data vector record and an output data vector record, and sending the input data vector record and the output data vector record to the verification component;
the verification component is used for verifying the design to be tested based on the clock signal record, the reset signal record, the control vector record, the input data vector record and the output data vector record.
5. The apparatus of claim 4,
the first authentication IP further comprises a system monitor for obtaining at least one of a clock signal record, a reset signal record, a control vector record, an input data vector record, and an output data vector record for presentation.
6. The apparatus of claim 5,
the device is divided into an application layer and a physical layer, and the sequence generator, the sequence driving module and the system monitor are arranged on the application layer; the first control vector component, the first data vector component and the second verification IP comprise a second control vector component, a second data vector component and an interface module which are arranged on the physical layer.
7. The apparatus of claim 1,
the bus protocol is a non-standard self-defined bus protocol.
8. The apparatus of claim 1,
the sequence driving module is also used for carrying out time sequence control on the excitation sequence items based on the bus protocol.
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