CN107544911A - A kind of proof of algorithm device - Google Patents
A kind of proof of algorithm device Download PDFInfo
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- CN107544911A CN107544911A CN201711037339.9A CN201711037339A CN107544911A CN 107544911 A CN107544911 A CN 107544911A CN 201711037339 A CN201711037339 A CN 201711037339A CN 107544911 A CN107544911 A CN 107544911A
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- 238000004891 communication Methods 0.000 claims abstract description 16
- 230000005540 biological transmission Effects 0.000 claims description 7
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- 238000010276 construction Methods 0.000 claims description 2
- 238000004088 simulation Methods 0.000 claims description 2
- 238000012360 testing method Methods 0.000 abstract description 3
- 238000012795 verification Methods 0.000 abstract description 2
- 238000013461 design Methods 0.000 description 4
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- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
In proof of algorithm, simple software emulation is often not accurate enough, and is verified again if being converted to hardware, then than relatively time-consuming.The present apparatus makes full use of the function of existing instrument, and directly the communication of algorithms is put into actual environment and tested, and accelerates the iteration of proof of algorithm.It combines the advantages of software emulation and hardware testing, can fast and effectively verification algorithm.
Description
Technical field
The present apparatus is related to FPGA and the communications field, and in particular to a kind of device of proof of algorithm, available for fast and effectively
Verify the communication of algorithms.
Background technology
In communication products development process, the exploitation and checking of physical layer algorithm are first carried out with matlab or C language etc., so
After could carry out hardware design.A critically important step is the checking to physical layer algorithm among these.
Two kinds of the general component software mode of traditional proof of algorithm and hardware mode：
（1）Software mode is needed to establish channel model, and then the algoritic module of sending and receiving is communicated by the model.By model
The limitation of the degree of accuracy, it is difficult to press close to real physical channel, even differ greatly sometimes.
（2）Hardware mode will design circuit, or algorithm is converted into HDL language, compiling, placement-and-routing, download to
On FPGA.Hardware design takes long enough, easily the even several months in several weeks.And algorithm changes every time, will change hardware and set
Meter, cause the iteration cycle of checking very long.
It can be seen that software mode ratio is very fast, but it is not actual physical channel；Hardware mode is slow, but can be in actual channel
Upper test.
If both modes combined, maximize favourable factors and minimize unfavourable ones, then can fast and effectively verify the communication of algorithms.
Presently relevant way is：Algorithm software（On computer）, data buffer storage device is connect, then connect AFE(analog front end).Wherein, number
It is used to store the transmission data of algorithm generation according to buffer storage and is transmitted to the DAC of AFE(analog front end), and the adc data of AFE(analog front end)
It is transmitted to computer.Receiving portion in AFE(analog front end) is typically complex, including circuit coupling, gain-adjusted, filtering, ADC etc.,
Most of is analog circuit.It can be seen that the buffer storage, AFE(analog front end) in this mode are required for specially designing hardware, still need
Want no small workload.
The present apparatus further reduces the workload of hardware design, and directly the communication of algorithms is put into actual environment and tested,
Accelerate the iteration of proof of algorithm.
The content of the invention
The mentality of designing of the present apparatus is, reduces the hardware development required for proof of algorithm as far as possible, i.e., with general device and
Instrument is substituted for the hardware verified certain algorithm and specially developed.Specifically：
The present apparatus, which is divided into, sends and receives two parts：
Transmitting portion includes computer, FPGA plates, AFE(analog front end), and computer connects FPGA plates, the connection simulation of FPGA plates by JTAG lines
Front ends, matlab and Quartus softwares are run wherein on computer, the communication of algorithms is run on matlab and generates transmission data,
Quartus downloads to transmission data in FPGA embedded RAM by JTAG, and FPGA ADC interface control circuit is in RAM
Data are transmitted to the ADC of AFE(analog front end), and the analog signal of ADC outputs is connected to communication line by line interface；
Receiving portion includes computer, digital oscilloscope, AFE(analog front end), and oscilloprobe picks up at the line interface of AFE(analog front end)
Reception signal, the data that oscillograph is adopted are transmitted to computer by USB line, and the matlab operation communications of algorithms run on computer are simultaneously located
The data that reason oscillograph receives.
Specific operation process is accordingly：
The first step, newly built construction is established in Quartus, comprising RAM and ADC interface circuit, compile and be configured in FPGA；
Second step, algorithm to be verified are run on matlab, and generation sends data and is converted into the file of mif forms；
3rd step, Quartus calls its instrument, and " In-System Memory Content Editor " are literary by the mif of second step
Part is updated into RAM；
Data in RAM are sent to ADC by the 4th step, ADC interface circuit, and generation analog signal is passed on communication line；
5th step, reception signal is picked up at the line interface of AFE(analog front end) with oscilloprobe, adjust hanging down for oscillograph manually
Straight gain knob makes waveform enter OK range, manually during regulation oscillograph base knob to obtain suitable sample rate；
6th step, the data adopted with the oscillograph driving acquirement oscillograph on computer are simultaneously stored to hard disk with document form；
7th step, matlab reads the data file received, and runs algorithm to handle the data, the number of results demodulated
According to；
8th step, the result data of demodulation is compared with original transmission data, carrys out the transmitting-receiving effect of check algorithm, if
It is not up to standard to receive and dispatch effect, then changes algorithm and repeats second step to the 8th step.
In said apparatus, transmitting portion make use of FPGA and Quartus softwares general in the industry, make use of often in receiving portion
The digital oscilloscope seen.The function replacements such as sampling, gain-adjusted, DAC in oscillograph traditional analog front end receiver portion
Correlation function.So, the hardware designed for verification algorithm is just seldom, only ADC portion and line interface circuit.
The beneficial effect of the device is that the communication of algorithms can be placed directly in actual environment and test, so as to direct and effective
Examine algorithm；Simultaneously as general instrument and device have been used, it is easily operated, and cause to verify the hardware done
Exploitation is reduced to minimum.Such checking is not only effectively but also quick.
Brief description of the drawings
Fig. 1 is the block diagram of the present apparatus.
Claims (2)
1. a kind of proof of algorithm device, is divided into and sends and receives two parts, it is characterised in that：
Transmitting portion includes computer, FPGA plates, AFE(analog front end), and computer connects FPGA plates, the connection simulation of FPGA plates by JTAG lines
Front ends, matlab and Quartus softwares are run wherein on computer, the communication of algorithms is run on matlab and generates transmission data,
Quartus downloads to transmission data in FPGA embedded RAM by JTAG, and FPGA ADC interface control circuit is in RAM
Data are transmitted to the ADC of AFE(analog front end), and the analog signal of ADC outputs is connected to communication line by line interface；
Receiving portion includes computer, digital oscilloscope, AFE(analog front end), and oscilloprobe picks up at the line interface of AFE(analog front end)
Reception signal, the data that oscillograph is adopted are transmitted to computer by USB line, and the matlab operation communications of algorithms run on computer are simultaneously located
The data that reason oscillograph receives.
2. a kind of usage right requires the method that 1 described device realizes communication of algorithms checking, it is characterised in that including following steps
Suddenly：
The first step, newly built construction is established in Quartus, comprising RAM and ADC interface circuit, compile and be configured in FPGA；
Second step, algorithm to be verified are run on matlab, and generation sends data and is converted into the file of mif forms；
3rd step, Quartus calls its instrument, and " In-System Memory Content Editor " are literary by the mif of second step
Part is updated into RAM；
Data in RAM are sent to ADC by the 4th step, ADC interface circuit, and generation analog signal is passed on communication line；
5th step, reception signal is picked up at the line interface of AFE(analog front end) with oscilloprobe, adjust hanging down for oscillograph manually
Straight gain knob makes waveform enter OK range, manually during regulation oscillograph base knob to obtain suitable sample rate；
6th step, the data adopted with the oscillograph driving acquirement oscillograph on computer are simultaneously stored to hard disk with document form；
7th step, matlab reads the data file received, and runs algorithm to handle the data, the number of results demodulated
According to；
8th step, the result data of demodulation is compared with original transmission data, carrys out the transmitting-receiving effect of check algorithm, if
It is not up to standard to receive and dispatch effect, then changes algorithm and repeats second step to the 8th step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711037339.9A CN107544911B (en) | 2017-10-31 | 2017-10-31 | Algorithm verification device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711037339.9A CN107544911B (en) | 2017-10-31 | 2017-10-31 | Algorithm verification device |
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| CN107544911A true CN107544911A (en) | 2018-01-05 |
| CN107544911B CN107544911B (en) | 2024-06-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855890A (en) * | 2019-11-24 | 2020-02-28 | 北京长峰科威光电技术有限公司 | Multi-mode infrared detector image algorithm analysis and verification method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1828617A (en) * | 2006-03-31 | 2006-09-06 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
| CN203423697U (en) * | 2013-08-21 | 2014-02-05 | 陕西理工学院 | FPGA (field programmable gate array) based simple digital signal transmission performance analyzer |
| CN103685103A (en) * | 2013-11-26 | 2014-03-26 | 广州市花都区中山大学国光电子与通信研究院 | Integral verification platform based on FPGA communication base bands |
| CN207397263U (en) * | 2017-10-31 | 2018-05-22 | 南京火零信息科技有限公司 | A kind of proof of algorithm device |
-
2017
- 2017-10-31 CN CN201711037339.9A patent/CN107544911B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1828617A (en) * | 2006-03-31 | 2006-09-06 | 电子科技大学 | Software and hardware synergistic simulation/ validation system and vector mode simulation/ validation method |
| CN203423697U (en) * | 2013-08-21 | 2014-02-05 | 陕西理工学院 | FPGA (field programmable gate array) based simple digital signal transmission performance analyzer |
| CN103685103A (en) * | 2013-11-26 | 2014-03-26 | 广州市花都区中山大学国光电子与通信研究院 | Integral verification platform based on FPGA communication base bands |
| CN207397263U (en) * | 2017-10-31 | 2018-05-22 | 南京火零信息科技有限公司 | A kind of proof of algorithm device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110855890A (en) * | 2019-11-24 | 2020-02-28 | 北京长峰科威光电技术有限公司 | Multi-mode infrared detector image algorithm analysis and verification method |
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| CN107544911B (en) | 2024-06-07 |
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