CN203423697U

CN203423697U - FPGA (field programmable gate array) based simple digital signal transmission performance analyzer

Info

Publication number: CN203423697U
Application number: CN201320512256.1U
Authority: CN
Inventors: 卢超
Original assignee: Shaanxi University of Technology
Current assignee: Shaanxi University of Technology
Priority date: 2013-08-21
Filing date: 2013-08-21
Publication date: 2014-02-05
Anticipated expiration: 2023-08-21

Abstract

The utility model relates to an FPGA (field programmable gate array) based simple digital signal transmission performance analyzer, which comprises an FPGA, a touch screen display and input module, an off-chip storage module, a D/A converter, a JTAG interface and an EPCS interface, wherein the FPGA is configured with a Nios II soft-core CPU, a signal generation module and a relevant interface control logic circuit, the touch screen display and input module, the off-chip storage module, the D/A converter, the JTAG interface and the EPCS interface are all connected with the FPGA, the FPGA is connected with a PC (personal computer) through the JTAG interface or the EPCS interface, and the FPGA is connected with an oscilloscope through the D/A converter so as to display the waveform and test data. The FPGA based simple digital signal transmission performance analyzer adopts a TFT touch screen, and is convenient to operate, good in human-computer interaction, and capable of being widely popularized.

Description

A kind of simple and easy digital data transmission performance evaluation instrument based on FPGA

Technical field

The utility model relates to a kind of digital data transmission performance evaluation instrument, is a kind of simple and easy digital data transmission performance evaluation instrument based on FPGA specifically.

Background technology

Develop rapidly along with the communication technology and computer technology, digital data transmission with it at a high speed, high bandwidth has obtained application more and more widely, particularly the application in the communications field has very important meaning, the demand of the communication test instrument that the thing followed detects towards such communication equipment is simultaneously the situation of high speed development, the requirement of test is also more and more stricter, testing equipment is had higher requirement, Digital Transmission Analyzer is most important in digital communication, the most basic tester, be mainly used in the transmission quality of testing digital communication signal, its main test parameter comprises error code, alarm, expense, jitter and wander etc., it is widely used in the development of digital communication equipment, produce, maintenance and metrology and measurement, also can be applicable to the construction of digital communications network, open and check and accept and maintenance test.Adopt FPGA to design a kind of simple and easy digital data transmission performance evaluation instrument, can realize baud rate stepping and be the m sequencer of 10Kbps and Manchester's code respectively as the test signal of tester, and the noise signal of the baud rate pseudo random sequence that is 100Kbps.Filter by signal by different cut-off frequencies constructs different transmission channel environment, signal by this channel after on oscilloscope with walking out of the eye pattern of signal, by measuring the amplitude of eye pattern, analyze different channels environment on the signal integrity of signal transmission and the impact of intersymbol interference, to judge whether this channel meets the transmission requirement of signal.

Summary of the invention

The problem existing for above-mentioned prior art, the utility model provides a kind of simple and easy digital data transmission performance evaluation instrument based on FPGA.

To achieve these goals, the technical solution adopted in the utility model is: a kind of simple and easy digital data transmission performance evaluation instrument based on FPGA, comprise FPGA, touch-screen shows and input module, sheet external memory module, D/A converter, jtag interface and EPCS interface, in FPGA, configure NiosII soft nucleus CPU, signal generating module and relevant interface control logic circuit, described touch-screen shows and input module, sheet external memory module, D/A converter, jtag interface is all connected with FPGA with EPCS interface, FPGA is connected with PC by jtag interface or EPCS interface, FPGA connects oscilloscope display waveform and test data by D/A converter.

As preferably, touch-screen shows and input module is TFT liquid crystal touch screen, responsible interface display and outside input control.

As preferably, sheet external memory module is SDRAM memory.

Compared with prior art, the utility model has the advantage of: the simple and easy digital data transmission performance evaluation instrument of design adopts TFT touch-screen, and easy to operate, man-machine interaction is good, can extensively promote.

accompanying drawing explanation:

Fig. 1 is the structural representation of a kind of simple and easy digital data transmission performance evaluation instrument based on FPGA described in the utility model.

embodiment:

Below in conjunction with accompanying drawing, the utility model is further illustrated.

As a kind of execution mode of the present utility model, consult Fig. 1, the utility model comprises FPGA, touch-screen shows and input module, sheet external memory module, D/A converter, jtag interface and EPCS interface, in FPGA, configure NiosII soft nucleus CPU, signal generating module and relevant interface control logic circuit, described touch-screen shows and input module, sheet external memory module, D/A converter, jtag interface is all connected with FPGA with EPCS interface, FPGA is connected with PC by jtag interface or EPCS interface, FPGA connects oscilloscope display waveform and test data by D/A converter.Touch-screen shows and input module is TFT liquid crystal touch screen, is responsible for interface display and outside input control.Sheet external memory module is SDRAM memory.

In Matlab, utilize DSPBuilder modeling tool to complete the foundation of sequence and the derivation of HDL, digital signal by M_list is

m sequence, signaling rate is can be adjustable by 10kbps stepping in 10 ~ 100kbps; Pseudo-random signal Noise_list is

noise sequence; Data transfer rate is 10Mbps, and Error Absolute Value is not more than 1%; Manchester_cod is to the output signal after the Synchronization of M_list signal, and object is to be more convenient to extract bit synchronization signal.

In described FPGA, configure the soft core of NiosII and set up realization by calling IP storehouse in SOPC Builder, mainly by NiosII CPU, sdram controller, universal I/O, EPCS controller, system ID, JTAG UART, main five parts of port with external linkage, respectively system clock and reset, TFT LCD control signal wire, touch-screen control signal wire, sdram interface control line, sequence signal generator control signal wire etc., formed the bottom most software hardware platform part of whole system, system clock 100MHZ.

In described external memory module, adopt SDRAM control interface IP on sheet, the interface of the IP module of calling is connected to the outer sdram interface of sheet, the clock signal clk of SDRAM adopts the inside PLL of FPGA to generate.

Described jtag interface and EPCS interface are FPGA download configuration circuit, are the processes that the content of FPGA is programmed, and after powering on, need to be configured at every turn, are features based on SRAM technique FPGA.In the configuration circuit of system, having designed two kinds of configuration modes is AS configuration and JTAG configuration mode, when AS is configured in system power failure, configuration data can be kept in the configuring chip of EPCS16, and configuration file is .pof file; JTAG configuration is special setting for the ease of the debugging of system, and power down is not preserved, and configuration file is .sof file.

Although be recognized as a most practical and preferred embodiment and described the utility model in conjunction with current, but be to be understood that, the utility model is not limited to the disclosed embodiments, and is intended on the contrary contain multiple modification and equivalent arrangements included in the spirit and scope of the appended claims.

Claims

1. the simple and easy digital data transmission performance evaluation instrument based on FPGA, comprise FPGA, touch-screen shows and input module, sheet external memory module, D/A converter, jtag interface and EPCS interface, in described FPGA, configure NiosII soft nucleus CPU, signal generating module and relevant interface control logic circuit, described touch-screen shows and input module, sheet external memory module, D/A converter, jtag interface is all connected with FPGA with EPCS interface, described FPGA is connected with PC by jtag interface or EPCS interface, described FPGA connects oscilloscope display waveform and test data by D/A converter.

2. a kind of simple and easy digital data transmission performance evaluation instrument based on FPGA according to claim 1, is characterized in that: described touch-screen shows and input module is TFT liquid crystal touch screen, is responsible for interface display and outside input control.

3. a kind of simple and easy digital data transmission performance evaluation instrument based on FPGA according to claim 1, is characterized in that: described external memory module is SDRAM memory.