CN104954044A - Jitter tolerance testing method and circuit for high-speed serial IO interface based on BIST - Google Patents

Abstract

The invention discloses a jitter tolerance testing method and circuit for a high-speed serial IO interface based on BIST (built-in self-test). The circuit mainly consists of a CDR circuit module, a jitter injection module, and an error code detection module. A CDR circuit at the receiving end of the high-speed serial IO interface is additionally provided with the jitter injection module and the error code detection module, and can achieve the self-testing of the jitter tolerance of the receiving end. The jitter injection module comprises a Jitter Memory, a PI (phase interpolator) and a PRBS (pseudorandom binary sequence) circuit, and is used for generating a test sequence containing jitter information. The error code detection module comprises a sequence detector (PRBS Checker), an XOR gate and an error code counter (Error Detection), and is used for detecting an error code and obtaining the number of error codes. The method and circuit achieve the self-testing of the jitter tolerance of the receiving end, and can achieve the different types of jitter injection, such as RJ (random jitter), PJ (periodic jitter), and DCD (duty cycle distortion). The BIST circuit is simple in implementation, effectively shortens the testing time, reduces the testing cost, can be used for various types of high-speed serial IO interface circuits, and is higher in practicality.

Description

A kind of high speed serialization I/O interface jitter toleration method of testing based on BIST and circuit

Technical field

The invention discloses a kind of high speed serialization I/O interface jitter toleration method of testing and circuit, specifically realize shake in the receiving terminal circuit inside of HSSI High-Speed Serial Interface and inject and Error detection, complete the test of receiving terminal jitter toleration.

Background technology

I/O (I/O) plays pivotal player in computer and commercial Application always.In Parallel I in early days/O bus, the alignment of data problems affect of interface the efficient communication with external equipment.But along with the increase of processor speed, I/O becomes the bottleneck of restriction system level performance, improve I/O performance for raising systematic function very crucial.In current high-speed communication system, originally be used for the serial communication technology SerDes (serializer/de-serializers) of optical fiber communication due to the flexibility of multiple high-speed communication protocol standard and use can be met, become the key technology of high-speed communication system.HSSI High-Speed Serial Interface based on SerDes technology is becoming general I/O interface standard, and it adopts high-speed differential signal transmission, shields the interference noise in transmission path, not only improves transmission speed, can also improve signal transmission quality.

For the communication temporal model between IC, when transmission rate is less than 100MHz, adopt system synchronization structure; Along with the increase of speed, the skew of clock between transmitting terminal and receiving terminal may exceed one-period (time delay on such as line), and in order to compensate this clock skew, designer adopts source synchronization structure; But when speed is more than 1GHz, skew between parallel data have impact on the further lifting of transmission rate greatly, people start to adopt motor synchronizing structure---at transmitting terminal, clock signal is embedded into transmitting data stream, at receiving terminal, from transmission data, recover clock by CDR (clock and data recovery) circuit, and receive data with this.

Along with data transfer rate constantly increases, signal quality will be affected, and make the degeneration of waveform, likely cause the mistake identification of data, namely error code.For high speed serialization I/O interface circuit, due to the impact of the effect of dispersion etc. of the noise in system, some random processes, periodic process, data correlation effect and passage, the data of receiving terminal receiving terminal are also nonideal, but the superposition of impact in ideal signal and transmitting procedure.Shake causes error code, makes the key factor of high-speed I/O interface circuit malfunction, can be divided into RJ (randomized jitter) and DJ (determining shake).Can the ce circuit of receiving terminal recover clock signal from the data flow being superimposed with dither signal, and sample correct data, and be the important performance index of high speed serialization I/O interface one, this also just needs to carry out jitter toleration test to receiving terminal.

Jitter toleration test pack is containing two aspects: under certain BER (error rate) level, whether jitter toleration meets Spec regulation, and receiving terminal is to the tolerance of shake.The former is under the error rate level required, whether the jitter toleration of test circuit-under-test is greater than the threshold value specified in Spec; The latter tests the maximum jitter value that receiving terminal circuit can be tolerated.Jitter toleration test needs the dither signal injecting controllable frequency and size at input, and whether the BER detecting the output signal of system under test (SUT) meets the demands.Jitter toleration tests the two large problems faced: 1. most bus standard all needs in BER≤10 ^-12under carry out jitter toleration test, then equipment at least will send 10 ¹³the data of individual bit, and jitter toleration test needs to test multiple frequency, and this all can make the testing time very long; 2. jitter toleration test needs produce different types of shake and mix, and it is complicated to produce the controlled shake comparison of ingredients close to actual proportions.

The test of jitter toleration comprises validation test and volume production test, desk-top instrument is generally used for validation test, when carrying out jitter toleration test, the specific instrument of general employing produces data flow and different types of shake, Cai and Wemer utilizes FM (frequency modulation(FM)) source to inject PJ (dither cycle), random noise generator injects RJ, longer optical cable or pcb board inject DDJ (data dependence shake) etc., these dither signals are tested for jitter toleration jointly, but this method of testing more complicated, and be difficult to mix and characterize these shake compositions accurately, the J-BERT N4903B instrument that Agilent company released in 2013 uses the built-in jitter sources through calibration, can carry out accurate jitter toleration test fast to receiving terminal.

ATE (Automatic Test Equipment) is generally used for volume production test, when using ATE to carry out jitter toleration test, usually needs to add some circuit for injecting or characterizing shake on test board or at inside circuit.From the end of the nineties, offshore company and university start high speed circuit field tests and study widely and obtain certain achievement, Fan and Zilic uses ATE to inject PJ, according to the linear relationship of Q value and BER, use the method minimizing testing time of extrapolating; Laquai and Cai proposes a kind of method injecting DDJ based on passive filter, only in load board, take very little area, but this method can not provide multiple shake neatly; Sunter and Roy tests by measuring the parameter affecting jitter toleration, but this method needs in load board, settle ULTRA module, and area occupied also makes design become complicated; Hafed and Watkins produces by the input of modulation transmitting terminal PLL (phase-locked loop) module the signal having shake, and this method can not produce unnecessary shake, but this method chattering frequency that can inject limits by the bandwidth of PLL; Keezer uses ATE to carry out modulation clock signal by dynamically changing phase place, and injects shake, eliminates the restriction of PLL bandwidth.

Test at present based on desk-top instrument and ATE can realize high-precision measurement, but testing cost is high, the testing time long and can not automatically test.Volume production for Facing to Manufacturing is tested, and this testing cost and testing time are very expensive, and we can use the method for DFT (Testability Design) to reduce testing cost, reduces the testing time.Use for reference the above-mentioned method of testing based on desk-top instrument and ATE, the test that can obtain jitter toleration needs 4 steps: 1. produce different types of frequency and the controlled dither signal of size; 2. test data stream is produced; 3. dither signal is applied in measured data stream; 4. the error rate of output signal is measured.Then according to measurement result, we judge that the increase of the error rate whether in claimed range or whether in obvious index is to obtain the result of jitter toleration test.Thought based on BIST realizes the injection of different types of shake and the measurement of error rate BER in receiving terminal circuit inside, can effectively reduce testing cost and testing time.

Next to consider how to realize different types of frequency and the controlled shake of size at inside circuit.The shake kind being applied to jitter toleration test generally has RJ, PJ and DCD (Duty Cycle Distortion), and these three kinds shakes produce than being easier to and characterizing.A lot of scholar is also studied this aspect.Cai and Fang adopts SSC (spread spectrum clock) to inject PJ shake, is generally the PJ of single-frequency, namely SJ (sinusoidal jitter), and the pass of the shake of injection and the frequency of dither signal and size is:

$\mathrm{SJ}=\frac{A_{\mathrm{SJ}}}{2}\×\sin (2\mathrm{\π}\×f_{\mathrm{SJ}}\×t),$ Wherein $A_{\mathrm{SJ}}\left(\mathrm{UI}\right)=\frac{{\mathrm{ofst}}_{\mathrm{ppm}}\×F_{\mathrm{baud}}}{\mathrm{\π}\×f_{\mathrm{SJ}}}$

F _bauddata rate, ofst _ppmthe amplitude of sinusoidal jitter signal, F _sJit is the frequency of sinusoidal jitter signal.

Huang and Wang adopts sine wave generator generated frequency and the controlled sinusoidal signal of amplitude, control N/N+1 bimodulus prescaler after Δ-δ modulator, and the pass of the shake of injection and the frequency of dither signal and size is:

$\mathrm{\φ}=\frac{{\mathrm{\ω}}_{\mathrm{out}}}{N+0.5}+\frac{{\mathrm{\ω}}_{\mathrm{out}}{N}_A}{{\mathrm{\ω}}_m{(N+0.5)}^2}\cos \left({\mathrm{\ω}}_{m}t\right)$

Wherein ω _outdata frequency, N _athe amplitude of sinusoidal jitter signal, ω _mit is the frequency of sinusoidal jitter signal.These methods can well inject SJ, carry out jitter toleration test to circuit-under-test, but these methods all can only inject the PJ of single-frequency, can not good simulating actual conditions.Ahmed and Kwasniewski realizes the injection of multiple shake by Digital Integrator, Adder, Delay Control Logic and Variable Vernier Delay, but circuit realiration more complicated, not intuitively.The present invention, according to the concrete testing procedure of high-speed serial I/O interface iSCSI receiving end jitter toleration, devises the Method and circuits that the high speed serialization I/O interface jitter toleration based on BIST is tested.

Summary of the invention

Technical purpose of the present invention is: carry out DFT design to the receiving terminal circuit of high speed serialization I/O interface, shake injection module is added in ce circuit, produce different types of frequency and the controlled dither signal of jitter value and obtain comprising the cycle tests of dither signal, and obtain BER by error code detection module, realize the test of receiving terminal jitter toleration.

The present invention is based on the thought of BIST, utilize phase interpolator PI to change clock phase, carry out shake and inject.The phase change of phase interpolator PI is determined by control word (Control Word), the chattering frequency specified by Spec and numbers translate become data to write Jitter Memory, change the control word of phase interpolator PI, the change of the clock phase needed can be obtained.When testing high speed serialization I/O interface, cycle tests generally has class clock " 0101 " sequence and PRBS two kinds.Wherein PRBS more can simulating actual conditions, can ensure extraordinary test coverage; And class clock " 0101 " sequence can get rid of the wobble type introducing ISI (intersymbol interference), be more suitable for the modulation of dither signal.In order to make test result closer to actual conditions, select PRBS as cycle tests in the present invention.

The technical scheme that the present invention realizes object is:

Technical scheme of the present invention comprises two parts content: the DFT of high speed serialization I/O interface design and method of testing and flow scheme design.The fundamental block diagram of test circuit of the present invention as shown in Figure 1, comprises ce circuit, (Jitter Injection) module and Error detection (Error Detection) module is injected in shake.Shake injection in BIST and error rate detection module is described in detail below in conjunction with Fig. 2.Shake injection module comprises Jitter Memory, phase interpolator PI and PRBS (pseudo-random binary sequence) circuit.Jitter Memory, for storing different types of shake data, can need to be write by bus before startup test pattern according to Spec regulation and test; Phase interpolator PI changes the phase place of the clock signal that VCO generates in ce circuit according to the wobble information write in Jitter Memory; PRBS circuit is made up of LFSR (linear feedback shift register), with the output of phase interpolator PI for clock signal, generates the cycle tests comprising wobble information.Error code detection module comprises sequential detector (PRBS Checker), XOR gate and error code counter (Error Counter), for detecting error code and obtaining number of bit errors.Compared with the method injected with the shake mentioned in background technology, the present invention can inject different types of shake, comprise randomized jitter RJ, determine to shake DJ, dither cycle PJ etc., and circuit realiration is simple, not needing extra pin when encapsulating, only needing before starting test pattern by the address write shake data of bus to Jitter Memory place.That when writing different types of shake data in Jitter Memory, phase interpolator PI is to the change of clock signal phase as shown in Figure 3; Fig. 3 (a) is the change of phase place when injecting square wave shake (Square Jitter), and Fig. 3 (b) is the change of phase place when injecting sinusoidal jitter SJ, and Fig. 3 (c) is the change of phase place when injecting randomized jitter RJ.

Fig. 4 describes method of testing of the present invention and testing process.Insert BIST circuit (comprising shake to inject and error code detection module) in receiving terminal circuit after, first shake waveform is drawn according to Spec regulation, write Matlab program, sampling dithering waveform, and the shake data obtained are write in Jitter Memory, then arrange test control signal, system enters test pattern.The jitter toleration test of receiving terminal has two parts content: under certain BER requires, test jitter toleration whether meet Spe regulation, and receiving terminal is to the maximum tolerance ability of shake, this two parts content measurement all needs to measure multiple Frequency point, needs the shake of cycle tests being injected to different frequency.For the former, inject quantitative shake according to the regulation of Spec, measure error rate BER and whether meet Spec regulation.If such as Spec is defined in 10 ^-12bER level under jitter toleration be 80ps, then inject the shake of 80ps, measure obtain BER, if BER≤10 ^-12, then system is 10 ^-12bER level under meet Spec regulation, otherwise for not meet; For test receiving terminal to the maximum tolerance ability of shake, progressively increase jitter value, and be written in Jitter Memory, measure corresponding error rate BER, when the jitter value injected exceedes the maximum tolerance ability of receiving terminal, then BER can increase in obvious index, then be that the jitter value once injected before obvious index increases is receiving terminal to the maximum tolerance ability of shaking at BER.

Technique effect of the present invention is:

First, the method adopted in the present invention does not change the original ce circuit of receiving terminal, can be applied to all ce circuits, carry out jitter toleration test;

Second, compared with testing with desk-top instrument and ATE, all test processs in the present invention complete at chip internal, the shake of not only injecting is not by the impact of external factor, add the accuracy of test, and decrease the dependence of the testing equipment to costliness, and then reduce testing cost, embody the meaning of BIST;

3rd, the present invention can inject different types of frequency and controlled shake---RJ, PJ, the DCD etc. of size, is not limited to the SJ of single-frequency.

Finally, circuit realiration of the present invention is simple, and hardware costs is little, compared to primary circuit, the just shake increased is injected and error code detection module, and this part BIST circuit is in "Off" state when circuit normally works, and the impact therefore caused primary circuit is smaller.Significance of the present invention is to greatly reduce testing cost, shortens the testing time, and is easy to realize, and is for a kind of pratical and feasible and effective method of testing of the jitter toleration of the high-speed serial I/O interface system based on BIST.

Accompanying drawing explanation

Fig. 1 circuit design fundamental block diagram of the present invention.

Fig. 2 BIST circuit structure design of the present invention schematic diagram.

The sequential chart that in injection module, clock signal phase changes is shaken in Fig. 3 the present invention.

Fig. 4 method of testing of the present invention and test flow chart.

Embodiment

For making method of the present invention and advantage clearly understandable, describing the high speed serialization I/O interface jitter toleration based on BIST provided by the present invention test design in detail below in conjunction with accompanying drawing, but not being construed as limiting the invention.

The present invention is based on the high speed serialization I/O interface jitter toleration method of testing of BIST, implementation step comprises:

First stage: set up BIST circuit

Step1: after high-speed serial I/O interface circuit design completes, inserts the BIST circuit for jitter toleration test.As shown in Figure 1, BIST of the present invention comprises two parts: shake is injected and Error detection.As shown in Figure 2, shake injection module is for generation of the binary sequence comprising the wobble information of testing needs, comprise Jitter Memory, phase interpolator PI and PRBS (pseudo-random binary sequence), that when writing different types of shake data in Jitter Memory, phase interpolator PI is to the change of clock signal phase as shown in Figure 3; Error code detection module is missed for detecting and obtains number of bit errors, comprises sequential detector (PRBS Checker), XOR gate and code error detector (Error Counter).

Step2: after inserting BIST circuit, according to test needs, draw shake waveform, write Matlab program, sample waveform obtains shaking data, is then written in Jitter Memory, measures eye pattern and jitter value (the randomized jitter measurement RMS value of the output signal of shake injection module, determine jitter measurement peak-to-peak value), shake injection module circuit is verified.

Second stage: measure jitter toleration and whether meet Spec regulation under certain BER condition

Step3: draw shake waveform according to Spec regulation, write Matlab program, sample waveform obtains shaking data, is then written in Jitter Memory.

Step4: arrange test control signal, enters test pattern.The control word signal of phase interpolator PI reads wobble information from Jitter Memory, changes the phase place of the clock signal that VCO exports, and PRBS circuit is using the output of PI as clock signal, and output packet is containing the cycle tests of wobble information.Then detect error code by error code detection module, and obtain number of bit errors, calculate error rate BER _test.

Step5: the BER specified in contrast Spec _specif, BER _test≤ BER _spec, then on this chattering frequency point, system under test (SUT) meets the requirement of dithering threshold in Spec, otherwise for not meet.

Step6: change the frequency injecting shake, repeat Step3 ~ Step5, until test all Frequency points, test completes.

Phase III: measure the maximum tolerance ability of receiving terminal to shake

The jitter toleration threshold value under certain BER level is defined in Step7:Spec.Progressively increase jitter value according to circuit test precision, and be written to Jitter Memory.

Step8: arrange test control signal, enters test pattern.Shake injection module obtains corresponding cycle tests according to the shake data be written in Jitter Memory, then detects error code by error code detection module, and obtains number of bit errors, calculates error rate BER _test.

Step9: calculate BER _testwhether increase in obvious index, if exponentially increase, then the last jitter value injected is the jitter toleration ability of receiving terminal, carries out Step10; Otherwise repeat Step7 ~ Step9, until BER is obvious exponential increase.

Step10: change the frequency injecting shake, repeat Step7 ~ Step9, until test all Frequency points, test completes.

The present invention proposes method for designing and the circuit of the test of a kind of high speed serialization I/O interface jitter toleration, based on BIST thought, set up test circuit, comprise shake injection module and error code detection module, according to the requirement of Spec, formulate test plan, realize testing the jitter toleration of high-speed serial I/O interface iSCSI receiving end, provide condition and the scheme of system level testing.The ce circuit of receiving terminal is the important component part of high speed serialization I/O interface circuit, can it recover clock signal from the data flow being superimposed with dither signal, and sample correct data, the important performance index of high speed serialization I/O interface one, namely extremely important to the jitter toleration test of receiving terminal circuit.BIST circuit realiration is simple, and realization price of hardware is little, convenient test, flexibly.In sum, the present invention effectively can reduce testing cost and shorten the testing time, is a kind of effective method of testing.

The various embodiments described above are only for illustration of the present invention, and wherein the specific implementation of each module all can change to some extent, and every equivalents of carrying out on the basis of technical solution of the present invention and improvement, all should not get rid of outside protection scope of the present invention.

Claims (3)

1., based on high speed serialization I/O interface jitter toleration method of testing and a circuit of BIST, it is characterized in that:

Comprise three parts: design BIST circuit, shake for cycle tests injects, realize jitter toleration test based on BIST.Wherein BIST circuit comprises two modules:

1) injection module is shaken, be made up of Jitter Memory, phase interpolator PI and PRBS (pseudo-random binary sequence) circuit, wherein Jitter Memory is for storing shake data, and phase interpolator PI and PRBS circuit are that cycle tests injects shake.

2) error code detection module, by sequential detector (PRBS Checker), XOR gate and code error detector (Error Counter) composition, detect the error code of cycle tests and count.

2. method as described in claim 1, is characterized in that:

Shake injection module circuit can inject different types of frequency and the controlled shake of size for cycle tests.Specify according to Spec or the kind of shake of testing requirement, frequency and jitter value draw shake waveform, write Matlab program, sampling dithering waveform obtains the concrete data of shaking, and writes in Jitter Memory.Shake data in phase interpolator PI reading Jitter Memory are as control word, change the phase place of the clock signal that VCO (voltage controlled oscillator) produces in CDR (clock and data recovery) circuit, PRBS circuit is with the output of phase interpolator PI for clock signal, and output packet is containing the cycle tests of wobble information.

3. method as described in claim 1, is characterized in that:

Based on testing process of the present invention, first shake data to be written in Jitter Memory, then test signal be set and start test pattern, the jitter toleration of test receiving terminal.