CN202216989U - Direct current electronic load based on FIFO architecture bus control mode - Google Patents

Abstract

The utility model discloses a direct current electronic load based on an FIFO architecture bus control mode. The direct current electronic load includes a DSP module (1) and an FPGA module (2). The DSP module (1) includes a DPS main control chip, an XINTF interface (3), a DSP input clock (4). The FPGA module (2) includes a three-state bus transmitting and receiving unit (5) which can carry out the bidirectional data exchange in order, an FIFO transmitting and receiving unit (6), a parallel-series and series-parallel converting unit (7), and a state machine interface unit (8). The XINTF interface (3) has the data exchange with the three-state bus transmitting and receiving unit (5). The state machine interface unit (8) transmits and receives data to an FPGA peripheral interface unit (8 '). The direct current electronic load based on the FIFO architecture bus control mode can fully play the advantages of the DPS in terms of algorithm and the advantages of the FPGA in terms of sequential control, the algorithm is more accurate and rapid, the control interface cutting is convenient, the compatibility and the transplantability are strong, and the sequential control is rapid and flexible.

Description

DC electronic load based on the fifo structure bus mastering mode

Technical field

The utility model relates to the electronic load field, specifically is a kind of DC electronic load based on the fifo structure bus mastering mode.

Background technology

1, the DC electronic load is a kind of Basic Measuring Instrument, can simulate actual load and special load waveform, is used for the test of DC power supply etc.

At present, DC electronic load control mode adopts the control mode of MCU+ discrete device combination mostly.MCU generally adopts single-chip microcomputer, ARM7 and DSP etc., discrete device according to application demand generally be divided into the bus extended chip, latch chip, bus driver/isolating chip, RAM, coding chip, basic gate circuit chip, string also/and go here and there conversion chip and simple programmable logic chip (for example GAL) or the like.

2, the control mode of conventional art is suitable for the exploitation of simple and easy electronic load, and function is simple, and performance requirement is lower.

Along with the technical development of various equipment under tests, the particularly application of new forms of energy industry such as LED DRIVER, has proposed requirements at the higher level to electronic load; Require Electronic Negative to be loaded with more perfect functions, reaction velocity faster, measuring accuracy more accurately, even upgrading ability or the like faster.

The control mode of conventional art is used to realize complicated function and reaches the superior performance requirement, MCU had higher requirements, and such as abundant special purpose interface (like SPI, CAN etc.) is arranged, universaling I/O port, even high primary frequency CPU etc.Simultaneously, need a large amount of digital integrated chips as peripheral circuit.This kind design major defect is following:

(1) MCU is had relatively high expectations, need abundant peripheral interface, the restriction type selecting;

(2) complex circuit designs, the MCU peripheral chip is more, influence buying and later maintenance;

(3) the circuit versatility is relatively poor, and such as the ADC that changes a distinct interface, the circuit that needs to change maybe be more;

(4) sequential control is slow, the computing of difficult realization complex logic, and difficulty satisfies the part high performance requirements.

Summary of the invention

To defective that exists in the prior art and deficiency, the utility model provides the bus control structure of DC electronic load, with implementation algorithm more quick and precisely, convenient, compatible strong, portable strong, the sequential control fast and flexible of control interface cutting.

For realizing above-mentioned purpose, the utility model provides a kind of DC electronic load based on the fifo structure bus mastering mode, comprises DSP module 1, FPGA module 2; Said DSP module 1 comprises DSP main control chip, XINTF interface 3, DSP input clock 4; Said FPGA module 2 comprises tristate bus line Transmit-Receive Unit 5, FIFO Transmit-Receive Unit 6, and string/string also converting unit 7, the state machine interface unit 8 of bidirectional data interaction successively; XINTF interface 3 and 5 data interactions of tristate bus line Transmit-Receive Unit; State machine interface unit 8 sends and accepts data to FPGA peripheral interface units 8'.

The XINTF interface 3 of said DSP comprises that 16 bit data bus, 8 bit address buses, read-write control line, sheet select control line, FPGA reset signal; Make tristate bus line Transmit-Receive Unit 5 data interactions of 16 bit data bus, 8 bit address buses, read-write control bus and FPGA module 2 in the XINTF interface 3 of DSP module.

Said FPGA module 2 also comprises FPGA input clock 10, and it provides independent clock through clock distribution unit 9 for each functional unit of FPGA module.

Said XINTF interface 3 is the DSP external memory interface, is configured to the Asynchronous SRAM interface shape.

Said tristate bus line Transmit-Receive Unit 5 is the Asynchronous SRAM interface, and the sampling interface frequency is three times of DSP activation frequency, can carry out reading or writing of data second sampling period, and when no datat read or write, data bus was in high-impedance state.

Said FIFO Transmit-Receive Unit 6 comprises a plurality of, receives the asynchronous FIFO structure; Supply to accomplish the buffering of different types of data, each asynchronous FIFO structure comprises 16 bit parallel data input pin Data [15..0], enable signal input end wrreq, clock signal input terminal wrclk, 16 bit parallel data output end q [15..0], enable signal output terminal rdreq, clock signal output terminal rdclk, spacing wave end rdempty.

Said FIFO Transmit-Receive Unit 6 comprises that 3 are sent asynchronous FIFO structure and 4 reception asynchronous FIFO structures; Said transmission asynchronous FIFO structure supplies the address, write and enable Wr and chip selection signal CS2 and judge and produce the enable signal of reading that sends, and said reception asynchronous FIFO structure supplies the address, read to enable Rd and chip selection signal CS2 judges and produce the enable signal of writing that receives.

Said clock distribution unit 9 comprises FPGA phase-locked loop pll and frequency-dividing counter, can produce asynchronous clock, as the read and write clock of asynchronous FIFO structure.

The major advantage of the utility model is following:

1, circuit design is simple, DSP+FPGA;

2, DSP realizes core algorithm, and algorithm is accurately quick;

3, FPGA realizes various digital interfaces, and interface is realized flexibly, highly versatile;

4, FPGA realizes various sequential logics, and sequential control is accurately quick, and maintainability is strong.

This structure can be given full play to the advantage of DSP aspect algorithm, brings into play the advantage of FPGA aspect sequential control simultaneously.DSP and FPGA have complementary advantages, and algorithm realizes that more quick and precisely the control interface cutting is convenient, and be compatible strong, portable strong, the sequential control fast and flexible.

Description of drawings

Fig. 1 is the bus control structure block diagram based on fifo structure;

Fig. 2 is the inner block diagram of realizing of FPGA;

Fig. 3 is the asynchronous FIFO interface block diagram;

Fig. 4 is the asynchronous FIFO sequential chart;

Fig. 5 is that FPGA state machine interface unit is connected block diagram with external interface.

Drawing reference numeral:

1, DSP module, 2, the FPGA module, 3, DSP XINTF (outside expansion) interface; 4, DSP input clock, 5, the tristate bus line unit, 6, the FIFO Transmit-Receive Unit; 7, and string/string converting unit also, 8, the state machine interface unit, 9, clock distribution unit; 10, FPGA input clock, 8', FPGA peripheral interface units.

Below in conjunction with accompanying drawing the utility model is further specified.

Embodiment

Like Fig. 1, shown in 2.DSP is a main control chip, and the bus of its XINTF interface comprises: 16 bit data bus, 8 bit address buses, read-write control line, sheet select control line, FPGA reset signal; 16 bit data bus, 8 bit address buses, read-write control line, sheet in the XINTF interface of use DSP selects the data interaction of control line completion and FPGA; The interface of FPGA and DSP is the tristate bus line interface, and the read-write incoming line of tristate bus line interface and 8 bit address lines produce the enable signal of 8 road FIFO, promptly control the read-write of 8 road FIFO; The bit wide of fifo structure is 16, and the inner FIFO that sends of FPGA exports 16 bit wide data, sends into parallel serial conversion unit, convert serial data into after, accomplish data by the state machine interface unit and send; The state machine interface unit receives serial data, sends into string and converting unit, convert parallel data into after, send into the inner fifo structure that receives of FPGA, send to DSP by the tristate bus line interface then; The fifo structure degree of depth is traditionally arranged to be 8 to 16 bytes, and the read-write clock separates, and plays the good data buffer action.

To be described in detail each unit below.

DSP XINTF (outside expansion) interface is the DSP external memory interface, is configured to the Asynchronous SRAM interface shape.The sequential of any read or write to the XINTF space can be divided into three phases: set up, activate and follow the tracks of.At establishment stage, the chip selection signal of interrogation signal becomes low level, produces address signal; In the activation stage, read or write signal and become low level, data latching is on the array bus; At tracking phase, read or write signal and put height, chip selection signal is low.In should using, only judge the activation stage, and read or write in activation stage completion data.So,, only set up minimum latent period at establishment stage and tracking phase; In state of activation, the cycle of foundation is three times of sampling period.

The tristate bus line Transmit-Receive Unit, the Asynchronous SRAM interface that is connected with DSP XINTF for FPGA.The sampling interface frequency is three times of DSP activation frequency, carries out reading or writing of data second sampling period, can effectively guarantee the correctness of data.When no datat read or write, data bus was in high-impedance state.

The FIFO Transmit-Receive Unit comprises 7 asynchronous FIFO structures, accomplishes the buffering of different types of data, and is as shown in Figure 3.Data [15..0] expression input 16 bit parallel data; Wrreq representes to import enable signal (high level is effective); Wrclk representes input clock signal (rising edge sampling), q [15..0] expression output 16 bit parallel data, and rdreq representes output enable signal (high level is effective); Rdclk representes clock signal (rising edge sampling), and whether rdempty signal indication data are empty (low high level representes that data are arranged).

Asynchronous FIFO, the degree of depth are 16 bytes, and sequential chart sees also Fig. 4.After data are effective, after writing the rising edge clock sampled data, delay time two and read clock, spacing wave (rdempty) is put low, and expression FIFO has data; Judge that spacing wave is low, start read data, the rising edge reading of data, after last data read among the FIFO, spacing wave (rdempty) was put height.

FIFO Transmit-Receive Unit, totally 7 asynchronous FIFO structures: 3 are sent FIFO and 4 reception FIFO.Address A1, read to enable (Rd) and chip selection signal (CS2) and judge and produce the enable signal of writing that receives FIFO_1, and the like, address A7, write and enable (Wr) and judge the enable signal of reading that produces transmission FIFO_3 with chip selection signal (CS2).

The read and write clock of asynchronous FIFO structure is an asynchronous clock, is produced respectively by the clock distribution unit.

And string/string and converting unit, mainly accomplish the conversion of data width, realize the good mutual of serial data and parallel data.

The state machine interface unit is the interface unit of FPGA and external circuit, and the interface block diagram sees also Fig. 5.This element is mainly accomplished the control to ADC, DAC and switching signal, and the functions such as judgement of various guard signals.

The clock distribution unit mainly is made up of FPGA phaselocked loop (PLL) and frequency-dividing counter, main effect: for each functional unit of FPGA provides independent clock.

Though the utility model discloses as above with preferred embodiment; Right its is not in order to limit the utility model; Under the situation that does not deviate from the utility model spirit and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the utility model.

Claims (8)

1. DC electronic load based on the fifo structure bus mastering mode is characterized in that: comprise DSP module (1), FPGA module (2); Said DSP module (1) comprises DSP main control chip, XINTF interface (3), DSP input clock (4); Said FPGA module (2) comprises tristate bus line Transmit-Receive Unit (5), FIFO Transmit-Receive Unit (6), and string/string also converting unit (7), the state machine interface unit (8) of bidirectional data interaction successively; XINTF interface (3) and tristate bus line Transmit-Receive Unit (5) data interaction; State machine interface unit (8) sends and accepts data to FPGA peripheral interface units (8').

2. the DC electronic load based on the fifo structure bus mastering mode according to claim 1 is characterized in that: the XINTF interface (3) of said DSP comprises that 16 bit data bus, 8 bit address buses, read-write control line, sheet select control line, FPGA reset signal; Make tristate bus line Transmit-Receive Unit (5) data interaction of 16 bit data bus, 8 bit address buses, read-write control bus and FPGA module (2) in the XINTF interface (3) of DSP module.

3. the DC electronic load based on the fifo structure bus mastering mode according to claim 2; It is characterized in that: said FPGA module (2) also comprises FPGA input clock (10), and it provides independent clock through clock distribution unit (9) for each functional unit of FPGA module.

4. according to claim 1 or 2 or 3 described DC electronic loads based on the fifo structure bus mastering mode, it is characterized in that: said XINTF interface (3) is the DSP external memory interface, is configured to the Asynchronous SRAM interface shape.

5. according to claim 1 or 2 or 3 described DC electronic loads based on the fifo structure bus mastering mode; It is characterized in that: said tristate bus line Transmit-Receive Unit (5) is the Asynchronous SRAM interface; The sampling interface frequency is three times of DSP activation frequency; Can carry out reading or writing of data second sampling period, when no datat read or write, data bus was in high-impedance state.

6. according to claim 1 or 2 or 3 described DC electronic loads based on the fifo structure bus mastering mode; It is characterized in that: said FIFO Transmit-Receive Unit (6) comprises a plurality of, receives the asynchronous FIFO structure; Supply to accomplish the buffering of different types of data, each asynchronous FIFO structure comprises 16 bit parallel data input pins (Data [15..0]), enable signal input end (wrreq), clock signal input terminal (wrclk), 16 bit parallel data output ends (q [15..0]), enable signal output terminal (rdreq), clock signal output terminal (rdclk), spacing wave end (rdempty).

7. the DC electronic load based on the fifo structure bus mastering mode according to claim 6; It is characterized in that: said FIFO Transmit-Receive Unit (6) comprises that 3 are sent asynchronous FIFO structure and 4 reception asynchronous FIFO structures; Said transmission asynchronous FIFO structure supplies the address, write and enable (Wr) and judge with chip selection signal (CS2) and produce the enable signal of reading that sends, and said reception asynchronous FIFO structure supplies the address, read to enable the enable signal of writing that (Rd) and chip selection signal (CS2) are judged the generation reception.

8. the DC electronic load based on the fifo structure bus mastering mode according to claim 3; It is characterized in that: said clock distribution unit (9) comprises FPGA phaselocked loop (PLL) and frequency-dividing counter; Can produce asynchronous clock, as the read and write clock of asynchronous FIFO structure.

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