CN101509805A - Multipath paralleling data acquisition system based on on-site programmable gate array - Google Patents

Multipath paralleling data acquisition system based on on-site programmable gate array Download PDF

Info

Publication number
CN101509805A
CN101509805A CN 200910048440 CN200910048440A CN101509805A CN 101509805 A CN101509805 A CN 101509805A CN 200910048440 CN200910048440 CN 200910048440 CN 200910048440 A CN200910048440 A CN 200910048440A CN 101509805 A CN101509805 A CN 101509805A
Authority
CN
Grant status
Application
Patent type
Prior art keywords
adc
module
memory
core
chip
Prior art date
Application number
CN 200910048440
Other languages
Chinese (zh)
Inventor
尚建华
王向伟
岩 贺
陈卫标
Original Assignee
中国科学院上海光学精密机械研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

A multiplex parallel data acquisition system based on a field programmable gate array is composed of a simulated modulation module, an ADC module, a power module, a press key, USB, an FPGA chip, JTAG, EPCS, an SDRAM memory, an SRAM memory, a Flash memory and an upper computer. The USB realizes the communication between the FPGA chip and the upper computer. The peripheral equipment of the SDRAM memory, the JTAG and the EPCS are respectively connected to an Avalon bus inside the FPGA chip through respective control core and the SRAM memory and the Flash memory are connected to the Avalon bus through a tristate bus line; and the power module supplies power to all the devices above. The system effectively solves the contradiction that CPU resources are occupied for long time in ADC conversion and processing process, and is characterized by simple structure and rapid data reading and storage.

Description

基于现场可编程门阵列的多路并行数据采集系统 Parallel data acquisition system based on multiple field programmable gate array

技术领域 FIELD

本发明涉及数据采集,特别是一种基于现场可编程门阵列(Field Programmable Gate Array,简称为FPGA)的多路并行数据采集系统。 The present invention relates to multi-channel data acquisition, in particular a field programmable gate array (Field Programmable Gate Array, abbreviated as FPGA) parallel data acquisition system. 背景技术 Background technique

在激光多普勒测声系统中,发射一束激光到空气与水的界面上,检测所得的信号经过速度解调和频率检波即可实现由水界面的振动频率测量获知水下声场的发射频率,所得信号再通过光电转换,得到携带相位信息的电信号,然后通过数据采集系统实现水下目标与水上平台的通信。 In the laser Doppler sound system, a laser beam emitted to the air and water interface, resulting in the detection signal through the frequency detector and velocity demodulating transmit frequency can be realized by a known measuring vibration frequency of water contact the underwater sound field , then the resultant signal by photoelectric conversion, to obtain an electric signal carrying the phase information, and communicate with the water platform underwater object by a data acquisition system.

由于水面的波动和波浪的扰动,激光探测信号很多时候不能到达接收系统,为了能让激光探测信号尽可能多的返回到达接收望远镜系统,采用了阵列探测的方法;该方法要求水上平台的数据采集系统能够实时采集和处理多路探测信号。 Since the disturbance signal laser detection systems often can not reach the receiver and the fluctuation of the surface waves, in order to allow as many laser detection signals reach the receiving telescope is returned, the method uses a probe array; this method requires data collection platform Water real-time acquisition and processing system can multiplex detection signal. 数据采集卡在各个领域得到广泛应用,但是现有的各种数据采集卡产品,不能同时满足多路并行、高速、高精度的要求,这不仅仅因为模数转换器(Analog to Digital Converters ,简称为ADC)方面的制约因素,同时也有成本的因素和处理器的因素。 Data acquisition card been widely in various fields, but a variety of data acquisition cards conventional products, can not meet the multi-channel simultaneously in parallel, high speed, high accuracy requirements, not only because of analog to digital converter (Analog to Digital Converters, Acronym as constraints ADC) aspects, but also factors factor and processor costs. 在解决多路同步采集方案中,传统的设计方法是基于FPGA+数字信号处理器(Digital Signal Processing,简称为DSP)。 In the multi-channel simultaneous acquisition solve embodiment, the method is based on the traditional design FPGA + DSP (Digital Signal Processing, abbreviated as DSP). 图一描述了一种基于FPGA和DSP的并行多路数据采集系统(参见王文武,曹治国等.基于FPGA和DSP的并行数据采集系统的设计[J].微计算机信息,2004, 20(11): 68, 69, 36)。 FIG describes a parallel multi-channel data acquisition system (see Wenwu, Caozhi Guo like FPGA and DSP based design FPGA and DSP-based parallel data acquisition system [J]. Microcomputer Information, 2004, 20 (11 ): 68, 69, 36). 多路模拟信号通过阻抗匹配电路11后,由FPGA13控制ADC转换电路12把模拟信号转换为数字信号, 转换后的数据经过缓冲后,由DSP14通过数据总线读取数据并进行相应处理,处理后的数据送到上位机15显示。 Multiple analog signals by the impedance matching circuit 11, 12 converts the analog signal converted by the ADC FPGA13 the control circuit into digital signals, the converted data after buffering by the DSP14 reads the data via the data bus and the corresponding treatment, after treatment 15 shows the data to the host computer. 该系统采用FPGA实现控制,用DSP实现信号处理, 这不仅使得系统需要同时采用FPGA和DSP,同时系统传输速率受FPGA电路板和DSP 电路板之间连接的影响。 The control system is implemented using FPGA, DSP for signal processing, which not only makes the system need to employ FPGA and DSP, and the system affected by the transmission rate connection between a circuit board and the FPGA DSP circuit board. 采用随机存取存储器(Random Access Memory,简称为RAM) 作为数据存储介质,而FPGA的内部RAM资源很有限,这就限制了数据传输速率。 Random access memory (Random Access Memory, referred to as a RAM) as a data storage medium, and the FPGA internal RAM resources are limited, which limits the data transmission rate. 在系统扩展的时候,由于DSP上的资源不能够随意改变使得系统的调整和扩展受到一定的限制。 For system expansion, because of the DSP resources can not be arbitrarily changed so that the expansion of the system to adjust and subject to certain restrictions.

发明内容 SUMMARY

3本发明的目的就是要克服上述数据采集系统的不足,提供一种基于现场可编程门阵列的多路并行数据采集系统,本发明应有效地解决ADC转换和处理过程中对CPU 资源长期占用的矛盾,具有结构简单、数据的快速读取和存储的特点。 3 The purpose of the present invention to overcome the shortcomings of the above-described data acquisition system, there is provided a parallel data acquisition system based on multiple field programmable gate arrays, and the present invention should effectively solve the ADC conversion process and the long-term occupation of CPU resources contradictions, has a simple structure, quick to read and store data features.

本发明的技术解决方案如下: Technical solutions of the present invention are as follows:

一种基于现场可编程门阵列的多路并行数据采集系统,该系统的构成由模拟调 A parallel data acquisition system based on multiple field programmable gate array, configured by an analog modulation system

理模块、ADC模块、电源模块、按键、通用串行总线(Universal Serial BUS ,简称为USB), FPGA芯片、联合测试调试接口(Joint Test Action Group ,简称为JTAG)、增强型串行配置器件(Enhanced Configuration Devices Serial,简称为EPCS)、同步动态随机存储器(Synchronous Dynamic Random Access Memory ,简称为SDRAM存储器)、静态随机存储器(Static Random Access Memory ,简称为SRAM存储器)、Flash存储器和上位机构成;所述的FPGA芯片的内部组成包括:NiosII 处理器、Avalon总线、按键控制核、JTAG控制核、EPCS控制核、SDRAM控制核、三态总线、USB控制核、DMA控制核、ADC控制模块,所述的USB实现FPGA芯片与上位机之间的通信;所述的外围设备SDRAM存储器、JTAG、 EPCS分别通过各自的控制核连接到FPGA芯片内部的Avalon总线上,SRAM存储器、Flash存储器通过三态总线连接到Avalon总线上;所述的电源模块为上述所有的 Processing module, the ADC module, power module, a key, a universal serial bus (Universal Serial BUS, simply referred to as USB), FPGA chip, a Joint Test debug interface (Joint Test Action Group, referred to as the JTAG), enhanced serial configuration device ( Enhanced Configuration Devices Serial, referred to as the EPCS), synchronous dynamic random access memory (synchronous dynamic random Access memory, referred to as SDRAM memory), SRAM (static random Access memory, referred to as SRAM memory), the Flash memory and upper body into; the said internal FPGA chip composition comprising: NiosII processor, the Avalon bus, button control core, the JTAG control core, the EPCS control core, SDRAM control core, three-state bus, USB control core, the DMA control core, the ADC control module, the the USB communication between the FPGA chip and the host computer; SDRAM memory of the peripheral device, JTAG, EPCS are respectively connected to the internal bus of the FPGA chip Avalon through the respective control core, SRAM memory, Flash memory via three-state bus Avalon to the bus; said power supply module for all of the above 备提供电源;所述的按键启动本系统进入工作状态,需要采集的模拟信号经过所述的模拟调理模块,调节模拟信号的电压幅度至ADC模块接受的范围内,调理后的模拟信号经ADC模块转换为并行的16位数字信号,进入FPGA芯片,通过FPGA芯片内的DMA控制核把数据直接存储到所述的SDRAM中,SDRAM中的数据经过FPGA芯片处理后,通过USB传输至所述的上位机显示。 Providing backup power; button to start the system into operation, the analog signals need to be collected through the analog conditioning module, adjusting the voltage amplitude of the analog signal to the ADC module within the acceptable range, the ADC analog signal conditioning module is converted to 16-bit parallel digital signal, into the FPGA chip, the DMA controller core FPGA chip by storing the data directly to the SDRAM, the SDRAM data after processing FPGA chip, USB host to transfer through the machine display.

所述的模拟调理模块由64个相同的子调理电路组成。 The analog conditioning module 64 by the same sub-conditioning circuit.

所述的ADC模块由8片16位的ADC芯片构成,每片ADC芯片可实现8路16位数据同步采集和转换,所述的ADC控制模块由8个ADC控制核构成,每个控制核用于驱动一片ADC芯片,所述的DMA控制模块相应的由8个DMA控制核构成。 The ADC module consists of eight 16-bit ADC chip configuration, each chip-chip ADC can achieve synchronous 8-bit data path 16 acquisition and conversion, the ADC control module consists of eight ADC core, each core with the control to drive an ADC chip, the DMA control module respective control core consists of eight DMA.

所述的USB为最高传输速率可达480Mbps的USB2. 0。 USB is the maximum transfer rate of up to 480Mbps USB2. 0.

本发明系统中的电路板采用底层版+核心板的结构,所述的底层版集成所述的模拟调理模块、ADC模块、电源模块、按键、USB;所述的核心板集成FPGA芯片、 JTAG、 EPCS、 SDRAM、 SRAM、 Flash存储器;所述的底层版与核心板之间通过三排插座和插针互相连接在一起。 The system of the present invention using a circuit board structural bottom plate + core plate, the bottom plate integrated analog conditioning module according to claim, the ADC module, power module, a key, the USB; the FPGA chip integrated core board, JTAG, EPCS, SDRAM, SRAM, Flash memory; between the bottom plate and a core plate connected to each other by three rows of pins and sockets.

本系统利用S0PC设计方法进行软硬件开发,其设计流程如图3 ,设计总共分为三大块:硬件系统开发工具SOPC Builder中的硬件设计,NiosII集成开发环境(Integrated Development Environment,简称为IDE)中的软件设计,QuartusII中进 The system uses hardware and software development S0PC design method, the design process shown in Figure 3, a total design divided into three parts: the hardware design of the hardware system development tool in SOPC Builder, NiosII IDE (Integrated Development Environment, referred to as IDE) software design, QuartusII in advance

行逻辑综合布局布线。 Line logic synthesis layout. 通过SOPCBuilder系统开发工具提供的直观的向导驱动图形用户界面,配置处理器,选择与配置外部设备控制核,分配地址、中断,通过Avalon 总线将它们连接起来创建所需的硬件系统。 SOPCBuilder provided by the system development tool intuitive wizard-driven graphical user interfaces, configure the processor, an external device selection and configuration control core, assign addresses, interrupt, Avalon bus by connecting them to create the required hardware. 在QuartusII中调用创建的硬件系统,根据电路板布局给硬件系统中的各个模块分配FPGA芯片上的管脚,编写测试文件和用户设计的其他硬件描述语言(Hardware Description Language,简称为HDL)文件,对硬件系统进行逻辑综合、布局布线和仿真生成硬件配置文件。 QuartusII hardware system call created, assigned to the pins on the FPGA chip hardware modules in accordance with the layout of the circuit board, the test preparation of documents and other users to design hardware description language (Hardware Description Language, abbreviated as HDL) files, The system hardware logic synthesis, simulation, and layout generation hardware profiles. 在软件设计中, 调用各个外部设备驱动头文件和库,基于可剥夺内核的实时操作系统进行多任务调度,使处理器能即时响应各个任务,编译调试后生成可执行代码。 In software design, call each external device driver header files and libraries, multi-task scheduling based on real-time operating system kernel deprivation, so that the processor can immediately respond to each task, the compiler generates executable code debugging. 最后把硬件配置文件和可执行代码通过下载线下载至电路板中进行片上调试。 Finally, the hardware configuration files and by downloading the executable code downloaded to the board line in the on-chip debugging. 本发明的技术效果如下: Technical effects of the present invention are as follows:

1、 通过FPGA控制8片ADC实现了64路模拟信号的同步采集,采集到的数据通过FPGA内部的DMA控制核实现了数据的快速读取和存储,同时可以有效地解决ADC 转换和处理过程中对CPU资源长期占用的矛盾。 1, the control 8 through the FPGA implements synchronous sampling ADC analog signal 64, the collected data enables fast reading and storing data by the DMA control core inside the FPGA, and can be solved efficiently and the ADC conversion process long-term occupation of the contradictions of CPU resources.

2、 采用Altera推出的SOPC设计方法,在一片FPGA上实现了多路数据的并行采集。 2, the design method using Altera SOPC introduced to achieve a parallel acquisition of multiplexed data in an FPGA.

3、 FPGA芯片上的管脚和存储资源可根据设计方案进行自由分配,具有很大的灵活性。 3, the pin and storage resources on the FPGA chip can be freely allocated according to the design, great flexibility.

4、 软件设计中,采用基于实时操作系统的任务调度设计方法,增强了系统的实时性。 4, software design, design methodology based task scheduling real-time operating system, and enhance the system in real time.

5、 通过USB与上位机通信,数据传输速率可达192Mbps,使得系统能应用于高速数据采集系统中。 5, the host computer via USB communication, data transfer rates of up to 192Mbps, so that the system can be applied to high-speed data acquisition system.

6、 设计了底层版+核心板的结构,核心板适用于不同的底层版,方便系统更新和扩展。 6, a structural bottom plate design + core board, core board for different underlying version, updated and expanded to facilitate system.

附图说明 BRIEF DESCRIPTION

图1为现有基于FPGA和DSP的多路信号采集系统结构示意图图2是本发明基于FPGA的多路同步采集系统结构示意图图3为系统软硬件设计流程图图4为ADC采集控制结构示意图图5为多任务调度流程图 FIG 1 is a conventional FPGA and DSP multi-channel signal acquisition system based on FIG. 2 is a schematic structural diagram of the present invention is based on the synchronous multiplex FPGA acquisition system structural diagram of the system hardware and software design of FIG. 3 is a flowchart of FIG. 4 is a schematic structural diagram of acquisition and control ADC 5 is a flowchart illustrating multitasking scheduler

图中:21-模拟调理模块、22-ADC模块、23-FPGA芯片、24-电源模块、25-按 FIG: Analog conditioning modules 21, 22-ADC module, 23-FPGA chip, the power module 24-, 25- press

5键、26- JTAG、 27- EPCS、 28- SDRAM、 29- S画、210- Flash存储器、211-USB、 212-上位机、231-NiosII处理器、232-Avalon总线、233-按键控制核、234-JTAG 控制核、235-EPCS控制核、236-SDRAM控制核、237-三态总线、238-USB控制核、 2310-DMA控制模块、2311-ADC控制模块;41-ADC芯片、42-ADC控制核、421-FIFO 缓冲器、43-第一子调理电路、44-第二子调理电路、45-第三子调理电路、46-第四子调理电路、47-第五子调理电路、48-第六子调理电路、49-第七子调理电路、410-第八子调理电路。 5 key, 26- JTAG, 27- EPCS, 28- SDRAM, 29- S Videos, 210- Flash memory, 211-USB, 212- PC, 231-NiosII processor, 232-Avalon bus, 233- key control core , 234-JTAG control core, 235-EPCS control core, 236-SDRAM control core, three-state bus 237-, 238-USB control core, 2310-DMA control module, 2311-ADC control module; 41-ADC chip, 42- ADC control core, 421-FIFO buffer, the first sub-conditioning circuit 43, a second sub-conditioning circuit 44-, 45- third sub-conditioning circuit, the fourth sub-conditioning circuit 46-, 47- fifth sub-conditioning circuit, 48- sixth sub-conditioning circuit, a seventh sub-conditioning circuit 49-, 410- eighth sub conditioning circuit. 具体实施方式 detailed description

下面结合附图和实施例对本发明作进一步说明。 The present invention is further described below in conjunction with the accompanying drawings and embodiments.

先请参阅图2,图2是本发明基于FPGA的多路同步采集系统最佳实施例的结构示意图,由图可见,本发明基于现场可编程门阵列的多路并行数据采集系统,该系统由模拟调理模块21、 ADC模块22、电源模块24、按键25、 USB211, FPGA芯片23、 JTAG26、 EPCS27、 SDRAM存储器28、 SRAM存储器29、 Flash存储器210和上位机212构成; Please refer to FIG. 2, FIG. 2 of the present invention is based on the multiplexing FPGA schematic construction of a preferred embodiment of a system synchronization acquisition can be seen, the present invention is a parallel multi-channel data acquisition system based on a field programmable gate array, the system consists of an analog conditioning module 21, ADC module 22, power module 24, the button 25, USB211, FPGA chip 23, JTAG26, EPCS27, SDRAM memory 28, SRAM memory 29, Flash memory 210 and the host computer 212 configured;

所述的FPGA芯片的内部组成包括:NiosII处理器231、 Avalon总线232、按键控制核233、 JTAG控制核234、 EPCS控制核235、 SDRAM控制核236、三态总线237、 USB控制核238、 DMA控制模块2310、 ADC控制模块2311,所述的USB211实现FPGA 芯片23与上位机212之间的通信;所述的外围设备SDRAM存储器28、 JTAG26、EPCS27 分别通过各自的控制核连接到FPGA芯片23内部的Avalon总线上,SRAM存储器29、 Flash存储器210通过三态总线237连接到Avalon总线上;所述的电源模块24为上述所有的设备提供电源;所述的按键25启动本系统进入工作状态,需要采集的模拟信号经过所述的模拟调理模块21,调节模拟信号的电压幅度至ADC模块22接受的范围内,调理后的模拟信号经ADC模块22转换为并行的16位数字信号,进入FPGA 芯片23,通过FPGA芯片内的DMA控制模块2310的DMA控制核把数据直接存储到所述的SDRAM存储器28中,SDRAM存 Inside the FPGA chip composition comprising: NiosII processor 231, Avalon bus 232, the key control core 233, JTAG control core 234, EPCS control core 235, SDRAM controller core 236, three-state bus 237, USB control core 238, DMA the control module 2310, ADC control module 2311, implemented according USB211 FPGA chip 23 and the communication between the host computer 212; SDRAM memory of the peripheral device 28, JTAG26, EPCS27 respectively, through respective internal control core 23 is connected to the FPGA chip Avalon on the bus, SRAM memory 29, Flash memory 210 through the tri-state bus 237 is connected to the Avalon bus; said power module 24 provides power to all of the above-described apparatus; the key 25 activates the system into operation, it is necessary acquisition of the analog signal through an analog conditioning module 21, adjusting the voltage amplitude of the analog signal to the ADC module 22 within the acceptable range, ADC analog signal conditioning block 22 converts the 16-bit parallel digital signal, into the FPGA chip 23 nuclear DMA DMA data is controlled by the control module within the FPGA chip 2310 is directly stored into the SDRAM memory 28, SDRAM memory 器28中的数据经过FPGA芯片23处理后,通过USB211传输至所述的上位机212显示。 The data in FPGA chip 28 after processing 23, USB211 transmitted by the host computer 212 to the display.

在本实施例中,所述的模拟调理模块21由64个相同的子调理电路组成。 In the present embodiment, the analog conditioning module 21 consists of 64 identical sub-conditioning circuit. 所述的ADC模块22由8片16位的ADC芯片构成,每片ADC芯片可实现8路16位数据同步采集和转换,ADC控制模块2311由8个ADC控制核构成,每个控制核用于驱动一片ADC芯片,所述的DMA控制模块2310相应的由8个DMA控制核构成。 The ADC module 22 by the eight 16-bit ADC chip configuration, each chip-chip ADC can achieve synchronous 8-bit data path 16 acquisition and conversion, the control module 2311 by the ADC ADC control core 8 constituting, for each control core driving an ADC chip, the DMA control module 2310 of the respective control core consists of eight DMA.

本实施例的系统中的电路板采用底层版和核心板相结合的结构,底层版集成所述的模拟调理模块21、 ADC模块22、电源模块24、按键25、 USB211;所述的核心 System according to the present embodiment of the bottom plate and the circuit board using a combination of core board structure, the bottom plate of the integrated analog conditioning module 21, ADC module 22, power module 24, the button 25, USB211; the core

6板集成FPGA芯片23、 JTAG26、 EPCS27、 SDRAM存储器28、 SRAM存储器29、 Flash 存储器210;所述的底层版与核心板之间通过三排50只引脚的插针和插座互相连接在一起。 6 FPGA chip integrated plate 23, JTAG26, EPCS27, SDRAM memory 28, SRAM memory 29, Flash memory 210; between the bottom plate and a core plate connected to each other by a pin and socket three rows of 50 pins. 所述的USB211为最高传输速率可达480Mbps的USB2. 0。 USB211 the highest transfer rate of up to 480Mbps USB2. 0.

所述的电源模块24的土15V电源作为整个电路板的输入电源,通过电压转换芯片分别产生3. 3V、 2. 5V和1. 8V电压为各个外围设备和FPGA芯片供电。 The power module 24 Soil 15V power supply as an input power to the entire circuit board 3. 3V respectively generated by the voltage converter chip, 2. 5V 1. 8V voltage and respective peripheral devices and power FPGA chip. 图4为ADC Figure 4 ADC

采集控制结构示意图 Schematic configuration acquisition control

图4为ADC采集控制结构示意图,底层版上的每个子调理模块的两路差分输出模拟信号连接ADC芯片41的一对差分输入端,每片ADC有8对差分输入端,分别连接8个子调理模块的差分模拟信号,每片ADC通过一个ADC控制核42连接到Avalon 总线232上。 FIG 4 collected the ADC diagram of the control structure, two differential outputs an analog signal for each sub-conditioning modules on the bottom plate connected to a pair of differential input of the ADC chip 41, each piece ADC has eight pairs of differential input terminals, respectively connected to 8 sub-conditioning differential analog signal modules, each chip ADC ADC by a control core 42 is connected to the bus 232 Avalon. 按键25、 JTAG26、 EPCS27、 SDRAM28、 USB211分别通过相应的控制核连接到FPGA内部的Avalon总线232上,SRAM存储器29和Flash存储器210通过三态总线连接到Avalon总线上237。 Button 25, JTAG26, EPCS27, SDRAM28, USB211 are connected to the inside of the FPGA Avalon bus 232 by respective control core, SRAM and Flash memory 29 through the tri-state memory 210 is connected to the bus 237 Avalon bus. FPGA内部的NiosII处理器231和DMA控制模块2310连接到Avalori总线上,与其他器件进行通信。 Inside the FPGA NiosII processor 231 and the DMA control module 2310 is connected to the Avalori bus to communicate with other devices. USB211数据线连接电路板上的USB端口和上位机212上的USB端口进行通信。 USB and USB port on the PC connected to the data line 212 USB211 board ports for communication.

所述的模拟调理模块21由64个相同的子调理电路组成,每个子调理电路调理一路模拟信号,调理后的模拟信号以差分输出的方式输出到ADC模块22。 The analog conditioning module 21 consists of 64 identical sub-conditioning circuit, each sub-channel analog signal conditioning circuit conditioning, the conditioned output analog signal to the ADC module 22 in the manner of a differential output. 所述的ADC 模块22由8片ADC芯片组成,每片ADC芯片可输入8路差分信号实现8路模拟信号同步采集和转换,且转换精度需要达到16位。 The ADC module 8 by the ADC 22 chips, 8 chips per chip ADC differential input signal can be implemented eight analog signals synchronous acquisition and conversion, and the conversion required to achieve 16-bit accuracy. DMA控制模块2310由8个相同的DMA 控制核组成。 Nuclear DMA control module 2310 controls the composition of the same. 8 th DMA. ADC转换后的数据通过DMA控制核快速传输到SDRAM存储器28中。 Data transmitted to the ADC fast SDRAM memory 28 through the DMA control core.

所述的控制核,需要自行设计ADC控制核和USB的控制核。 Said control core, need to design ADC control of nucleus and USB.

本实施例所述的FPGA芯片23为Altera公司的CycloneII系列,采用基于S0PC 软硬件协同设计的方法。 FPGA chip according to the present embodiment as Altera's 23 CycloneII series of hardware and software co-design method based S0PC. 基于NiosII处理器进行软件开发,软件设计中采用实时操作系统来提高系统的实时性。 NiosII processor-based software development, software design, real-time operating system to improve the system in real time.

所述的外部存储器系统由8MB 32位的SDRAM存储器、512KB 32位的SRAM存储器和8MBYTE 16位的Flash存储器构成大容量存储器。 Said external memory system is composed of 8MB 32-bit SDRAM memory, 512KB 32 bit SRAM memory and 8MBYTE 16-bit Flash Memory mass memory.

由于系统中的数据传输速率需要达到112Mbps, 一般的串口和网口难以达到要求,采用周边元件扩展接口(PedpherdComponent Interconnect,简称为PCI)可满足此传输速率要求,但是这样不仅增加系统的体积,且不支持热插拔;我们采用了通过支持热插拔的USB2. 0与上位机212通信,传输速率能够达到112 Mbps以上。 Since the data transfer rate of the system needs to reach 112Mbps, general serial port and the network port is difficult to meet the requirements, using the Peripheral Component Interconnect (PedpherdComponent Interconnect, abbreviated as PCI) can satisfy this capacity requirement, but this not only increases the volume of the system, and does not support hot swap; we use the support USB2 0 through 212 communicate with the host computer, the transmission rate can reach 112 Mbps hot-swappable.

在系统软硬件设计中,通过S0PC设计方法调用各个外围设备的控制核构建硬件系统,在QuartusII中调用创建的硬件系统,分配FPGA芯片上的管脚,编写测 In the system hardware and software design, build hardware design system call S0PC method for controlling nuclear respective peripheral devices, hardware system calls created in the QuartusII, dispensing pins on the FPGA chip, measured prepared

7试文件和用户设计的其他HDL文件,对硬件系统进行逻辑综合、布局布线和仿真生成硬件配置文件,通过JTAG26利用下载线下载配置文件于电路板。 7 HDL test files and other files of a user design system hardware logic synthesis, simulation, and layout generation hardware configuration file, by using the download cable JTAG26 download the configuration file on the circuit board. 基于微控制器操作系统(Microcontroller Operating System ,简称为UC/OSII)编写软件程序, 釆用多任务调度的方法。 Microcontroller-based operating system (Microcontroller Operating System, referred to as the UC / OSII) to write software programs, multi-task scheduling method Bian. 在NiosII处理器中编写并调试软件程序,编译通过后, 通过下载线把软件程序下载到电路板执行在线硬件调试,调试结束后把配置文件下载到EPCS中,通过下载线把程序下载到Flash存储器210中。 NiosII processor in writing and debugging software program, compiled by the software program downloaded into the board hardware debugging through the implementation of online download cable, after the commissioning to download the file to EPCS, the program is downloaded to the Flash memory via download cable 210. 系统上电后,自动加载Flash存储器中的程序和数据至SRAM存储器29中运行。 After the power system, automatically load a program in the Flash memory and SRAM data memory 29 to run. 工作过程如下: It works as follows:

如图4所示,每路模拟信号分别经过不同的模拟子调理电路后进入ADC模块22 进行转换,每8路模拟信号通过一片ADC芯片转换后通过一个输出口串行输出,串行输出的数据通过FPGA控制串并转换,并存入ADC控制模块2311的ADC控制核内部由宏模块定制的先入先出(First Input First Output,简称为FIFO)缓冲器进行缓冲。 As shown, each of the analog signals through the various sub analog conditioning circuit into the ADC after conversion module 422, each of eight analog signals by an ADC chips output by converting a serial output, the serial output data FPGA control by serial-parallel conversion, and stored in the ADC ADC control module 2311 controls the internal core by a custom macroblock FIFO (first Input first Output, simply referred to as FIFO) buffer to buffer. 当8路模拟信号都转换结束后,产生中断启动,图2中的DMA模块2310 传输数据至SDRAM存储器29中。 When the end 8 are converted to analog signals, an interrupt is generated to start, in FIG. 2 DMA module 2310 transmit data to the SDRAM memory 29. SDRAM存储器29中的数据经过NiosII处理器231 处理后,通过USB211传输至上位机212的控制面板实时显示。 The data of the SDRAM memory 29 NiosII processor 231 after processing, to the upper control panel 212 is transmitted through the real-time display USB211. 在采集过程中,可通过按键启动ADC转换、使ADC进入低功耗模式、使能8片ADC同步采集。 During acquisition, the ADC conversion is initiated through the button, the ADC into low power mode, enabling synchronous acquisition eight ADC. 在软件设计中,采用图5所示的多任务调度方法,基于实时操作系统创建了键盘任务、低功耗模式任务、同步采集任务、DMA传输任务、数据处理任务和输出显示任务。 In the software design, multi-task scheduling method shown in FIG. 5, the keyboard task is created based on the real-time operating system, a low power mode task, synchronization acquisition task, the DMA transfer tasks, data processing tasks, and a display output tasks. 给每个任务分配一个优先级,采用动态优先级调度法,使得各个任务能即时得到处理, Each task is assigned a priority, dynamic priority scheduling method, such that each task can immediately be processed,

各个任务之间通过信号量集和信号量进行通信。 Communicating between each task and a semaphore set by the semaphore.

通过按键25来启动ADC模块22转换后的串行数据的读取和传输,每片ADC芯片的采集转换过程如图4: 8路子调理电路43〜410分别调理8路模拟信号,调理后的模拟信号差分输出到ADC芯片41, FPGA内部的ADC控制核42控制ADC芯片41的采集和输出数字信号的串并转换,转换后的并行16位数字信号缓存到FIFO缓冲器421,当每片ADC芯片的8个通道全部转换结束后产生中断,启动DMA控制模块2310 传输数据至SDRAM存储器28,数据经NiosII处理器处理后,通过外围通用串行总线USB211传输至上位机212的控制面板实时显示。 To start reading and transmission of the serial data by the ADC module 22 converts the keys 25, each sheet 4 ADC chip acquisition conversion process shown in FIG: 8, respectively 43~410 conditioning circuit conditioning path 8 analog signals, the analog conditioning differential output signal to the ADC chip 41, an internal control core 42 of the FPGA ADC acquisition and control string digital signal output of ADC chip 41 and converted, parallel 16-bit digital signal to the FIFO buffer 421 buffers the converted ADC chip when each sheet after converting all eight channels generate an interrupt, DMA control module 2310 starts transferring data to the SDRAM memory 28, the data processor after NiosII, the upper computer peripheral USB USB211 transmitted through the control panel display 212 in real time.

所述的电源模块24可采用L7805,AMS1117-3. 3, AMS1117-2. 5,或AMS1117-1. 8。 The power module 24 may employ L7805, AMS1117-3. 3, AMS1117-2. 5, or AMS1117-1. 8. ADC转换模块22采用了德州仪器(Texas Instruments,简称为TI)公司最新推出的ADS1178,模拟调理模块21主要由0PA350、 0PA1632、 REF1004组成。 ADC conversion module 22 uses Texas Instruments (Texas Instruments, referred to as TI) company's new ADS1178, analog conditioning module 21 is mainly composed of 0PA350, 0PA1632, REF1004 composition. FPGA芯片23 FPGA chip 23

8采用Altera的CycloneII系列的EP2C35F484C8。 8 Altera's EP2C35F484C8 CycloneII series. USB芯片211采用Cypress公司的USB2.0芯片CY7C68013。 211 Cypress USB chip uses the company's USB2.0 chip CY7C68013. 外围存储器由两片8MB 32位的K4S641632 SDRAM28、 512KB 32位的IS61LV25616AL SRAM29和一片8MBYTE 16位的JS28F640 Flash存储器210 构成。 Peripheral memory by a two-bit 8MB 32 K4S641632 SDRAM28, 512KB 32 bit IS61LV25616AL SRAM29 8MBYTE 16 and a bit JS28F640 Flash memory 210 configured.

在SOPC Builder中构建硬件系统时,Altera只提供了通用模块的控制核,按系统需要编写了ADC和USB2. 0的控制核。 When building hardware system in SOPC Builder, Altera provides only a general nuclear control module, according to the system need to write the ADC and control of nuclear USB2. 0 in. 系统通过FPGA芯片23控制ADC模块22 数据的采集、缓存和串并转换,并通过DMA直接传输数据到外围存储器。 Acquisition System by FPGA chip 23 controls the data ADC module 22, and a serial-parallel conversion buffer, and transmit data directly to the peripheral memory by DMA.

本发明采用了Altera公司推出的基于SOPC的软硬件协同设计的方法,设计自定义外设的控制核,通过USB2.0与上位机通信,在电路板设计中采用底层版+核心板的设计方法。 The present invention uses a method based on hardware and software co-design SOPC Altera Corporation introduced, from the control nuclear design defined peripherals communicate with the host machine via USB2.0, the underlying design method EDITION + core board in the circuit board design . 为提高系统的实时性,软件程序设计中采用了基于UC/OSII实时操作系统的设计方案。 In order to improve real-time systems, software programming using design UC / OSII real-time operating system. 不仅在一片FPGA芯片上实现了多路数据并行采集和实时显示,方便快捷的实现软硬件系统开发,同时具有很大的灵活性和可扩展。 Not only in the midst of the FPGA chip to achieve a multi-channel parallel data acquisition and real-time display, convenient and efficient realization of software and hardware system development, but also it has great flexibility and scalability.

Claims (5)

  1. 1、一种基于现场可编程门阵列的多路并行数据采集系统,特征在于该系统由模拟调理模块(21)、ADC模块(22)、电源模块(24)、按键(25)、USB(211),FPGA芯片(23)、JTAG(26)、EPCS(27)、SDRAM存储器(28)、SRAM存储器(29)、Flash存储器(210)和上位机(212)构成;所述的FPGA芯片的内部组成包括:NiosII处理器(231)、Avalon总线(232)、按键控制核(233)、JTAG控制核(234)、EPCS控制核(235)、SDRAM控制核(236)、三态总线(237)、USB控制核(238)、DMA控制模块(2310)、ADC控制模块(2311),所述的USB(211)实现FPGA芯片(23)与上位机(212)之间的通信;所述的外围设备SDRAM存储器(28)、JTAG(26)、EPCS(27)分别通过各自的控制核连接到FPGA芯片(23)内部的Avalon总线上,SRAM存储器(29)、Flash存储器(210)通过三态总线(237)连接到Avalon总线上;所述的电源模块(24)为上述所有的设备提供电源;所述的按键(25)启动本系统进入工作状态,需要采 A parallel multi-channel data acquisition system based on a field programmable gate array, characterized in that the system by an analog conditioning module (21), ADC module (22), the power module (24), the key (25), USB (211 ), FPGA chip (23), JTAG (26), EPCS (27), SDRAM memory (28), SRAM memory (29), Flash memory (210) and a host computer (212) configured; inside of the FPGA chip composition comprising: NiosII a processor (231), Avalon bus (232), the key control core (233), JTAG control core (234), EPCS control core (235), SDRAM control core (236), three state bus (237) , USB control core (238), DMA control module (2310), ADC control module (2311), the USB (211) for communication between the FPGA chip (23) with the host computer (212); said periphery device SDRAM memory (28), JTAG (26), EPCS (27) are connected to the FPGA chip (23) through respective control core on the inside of the Avalon bus, SRAM memory (29), Flash memory (210) through a three-state bus (237) connected to the Avalon bus; said power module (24) provides power to all of the above-described apparatus; said key (25) to start the system into operation, requires mining 集的模拟信号经过所述的模拟调理模块(21),调节模拟信号的电压幅度至ADC模块(22)接受的范围内,调理后的模拟信号经ADC模块(22)转换为并行的16位数字信号,进入FPGA芯片(23),通过FPGA芯片内的DMA控制核把数据直接存储到所述的SDRAM存储器(28)中,SDRAM存储器(28)中的数据经过FPGA芯片(23)处理后,通过USB(211)传输至所述的上位机(212)显示。 An analog signal through the set of analog conditioning module (21), adjusting the voltage amplitude of the analog signal to the ADC module (22) within the acceptable range, the ADC analog signal conditioning module (22) is converted to 16-bit parallel digital signal, into the FPGA chip (23), the data through the DMA controller core in an FPGA chip directly stored into the SDRAM memory (28), the data (28) in the SDRAM memory (23) after processing pass FPGA chip by USB (211) is transmitted to the host computer (212) is displayed.
  2. 2、 根据权利要求1所述的多路并行数据采集系统,其特征在于所述的模拟调理模块(21)由64个相同的子调理电路组成。 2, according to claim 1, said multiple parallel data acquisition system, characterized in that said analog conditioning module (21) consists of 64 identical sub-conditioning circuit.
  3. 3、 根据权利要求1所述的多路并行数据采集系统,其特征在于所述的ADC模块(22)由8片16位的ADC芯片构成,每片ADC芯片可实现8路16位数据同步釆集和转换,ADC控制模块(2311)由8个ADC控制核构成,每个控制核用于驱动一片ADC 芯片,所述的DMA控制模块(2310)相应的由8个DMA控制核构成。 3, according to claim 1, said multiple parallel data acquisition system, characterized in that said ADC module (22) consists of eight 16-bit ADC chip configuration, each chip-chip ADC 8 can achieve data synchronization preclude 16 and a set conversion, ADC control module (2311) is controlled by a eight ADC core configuration, each control core for driving an ADC chip, the DMA control module (2310) a respective control core consists of eight DMA.
  4. 4、 根据权利要求1所述的多路并行数据采集系统,其特征在于所述的USB(211) 为最高传输速率可达480Mbps的USB2. 0。 4, according to claim 1, said multiple parallel data acquisition system, wherein the USB (211) is the highest transfer rate up to 480Mbps USB2. 0.
  5. 5、 根据权利要求1所述的多路并行数据采集系统,其特征在于系统中的电路板采用底层版和核心板的结构,所述的底层版集成所述的模拟调理模块(21)、 ADC模块(22)、电源模块(24)、按键(25)、 USB(211);所述的核心板集成FPGA芯片(23)、 JTAG (26)、 EPCS (27)、 SDRAM存储器(28) 、 SRAM存储器(29)、 Flash存储器(210); 所述的底层版与核心板之间通过三排插座和插针互相连接在一起。 5, according to claim 1, said multiple parallel data acquisition system, wherein the system board using the structural bottom plate and the core plate, the bottom plate of the integrated analog conditioning module (21), ADC module (22), the power module (24), the key (25), USB (211); the FPGA chip integrated core plate (23), JTAG (26), EPCS (27), SDRAM memory (28), SRAM memory (29), Flash memory (210); and by three rows of socket pins connected to each other between said core plate and the bottom plate.
CN 200910048440 2009-03-27 2009-03-27 Multipath paralleling data acquisition system based on on-site programmable gate array CN101509805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200910048440 CN101509805A (en) 2009-03-27 2009-03-27 Multipath paralleling data acquisition system based on on-site programmable gate array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200910048440 CN101509805A (en) 2009-03-27 2009-03-27 Multipath paralleling data acquisition system based on on-site programmable gate array

Publications (1)

Publication Number Publication Date
CN101509805A true true CN101509805A (en) 2009-08-19

Family

ID=41002274

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200910048440 CN101509805A (en) 2009-03-27 2009-03-27 Multipath paralleling data acquisition system based on on-site programmable gate array

Country Status (1)

Country Link
CN (1) CN101509805A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102243097A (en) * 2010-05-13 2011-11-16 西安博能电力技术有限公司 Online audio diagnosis system and method for full-closed combined electric appliance
CN102346455A (en) * 2011-04-29 2012-02-08 山东科汇电力自动化有限公司 Design method of sampling module
CN101714103B (en) 2009-12-15 2012-11-28 中国华录·松下电子信息有限公司 Task dispatcher based on programmable logic device
CN102030018B (en) 2009-09-28 2013-01-16 西门子信号有限公司 Attached peripheral data acquisition and distribution device for axis counting system
CN103235542A (en) * 2013-02-01 2013-08-07 哈尔滨理工大学 Field programmable gate array (FPGA)-based multipath standard signal acquisition and transmission device
CN103246225A (en) * 2013-05-03 2013-08-14 奇瑞汽车股份有限公司 FPGA (Field Programmable Gata Array)-based multiway simultaneous sampling system realized by LVDS (Low Voltage Differential Signaling) interfaces
CN103297055A (en) * 2013-03-19 2013-09-11 中国科学院声学研究所 Device for achieving multipath serial ADC synchronization by adopting FPGA
CN103970701A (en) * 2014-05-28 2014-08-06 吉林大学 Field-programmable gate array based real-time synchronous data acquisition intellectual property core
CN104021098A (en) * 2014-06-19 2014-09-03 福州闽台机械有限公司 Multi-board collaboration architecture based on DMA transparent transmission
CN104408001A (en) * 2014-12-11 2015-03-11 哈尔滨工程大学 High-accuracy multipath data synchronous acquisition device
CN105116793A (en) * 2015-07-20 2015-12-02 中国科学院西安光学精密机械研究所 Acquisition system and acquisition method for information of reconfigurable control panel
CN105243040A (en) * 2015-11-11 2016-01-13 中国电子科技集团公司第四十一研究所 Instrument programmed control system and method supporting USBTMC protocol based on PCIe bus
CN105425028A (en) * 2015-10-27 2016-03-23 中国电子科技集团公司第四十一研究所 Microwave power measurer based on FPGA
CN105650064A (en) * 2016-03-06 2016-06-08 浙江大学 Pneumatic position servo controller based on DSP
CN107885694A (en) * 2017-10-18 2018-04-06 广东高云半导体科技股份有限公司 Support system-level integrated circuit chip

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102030018B (en) 2009-09-28 2013-01-16 西门子信号有限公司 Attached peripheral data acquisition and distribution device for axis counting system
CN101714103B (en) 2009-12-15 2012-11-28 中国华录·松下电子信息有限公司 Task dispatcher based on programmable logic device
CN102243097A (en) * 2010-05-13 2011-11-16 西安博能电力技术有限公司 Online audio diagnosis system and method for full-closed combined electric appliance
CN102346455A (en) * 2011-04-29 2012-02-08 山东科汇电力自动化有限公司 Design method of sampling module
CN102346455B (en) 2011-04-29 2013-07-10 山东科汇电力自动化有限公司 Design method of sampling module
CN103235542A (en) * 2013-02-01 2013-08-07 哈尔滨理工大学 Field programmable gate array (FPGA)-based multipath standard signal acquisition and transmission device
CN103297055A (en) * 2013-03-19 2013-09-11 中国科学院声学研究所 Device for achieving multipath serial ADC synchronization by adopting FPGA
CN103246225A (en) * 2013-05-03 2013-08-14 奇瑞汽车股份有限公司 FPGA (Field Programmable Gata Array)-based multiway simultaneous sampling system realized by LVDS (Low Voltage Differential Signaling) interfaces
CN103246225B (en) * 2013-05-03 2016-06-08 奇瑞新能源汽车技术有限公司 Based on the multiple fpga lvds simultaneous sampling system interface
CN103970701A (en) * 2014-05-28 2014-08-06 吉林大学 Field-programmable gate array based real-time synchronous data acquisition intellectual property core
CN103970701B (en) * 2014-05-28 2017-08-25 吉林大学 Nuclear data based on intellectual property field programmable gate array of real-time synchronization acquisition
CN104021098A (en) * 2014-06-19 2014-09-03 福州闽台机械有限公司 Multi-board collaboration architecture based on DMA transparent transmission
CN104021098B (en) * 2014-06-19 2017-05-17 福州闽台机械有限公司 Multi plate dma transparent transmission Coordination Architecture
CN104408001B (en) * 2014-12-11 2017-05-31 哈尔滨工程大学 Precision synchronization acquisition device multiplexed data
CN104408001A (en) * 2014-12-11 2015-03-11 哈尔滨工程大学 High-accuracy multipath data synchronous acquisition device
CN105116793A (en) * 2015-07-20 2015-12-02 中国科学院西安光学精密机械研究所 Acquisition system and acquisition method for information of reconfigurable control panel
CN105425028A (en) * 2015-10-27 2016-03-23 中国电子科技集团公司第四十一研究所 Microwave power measurer based on FPGA
CN105243040A (en) * 2015-11-11 2016-01-13 中国电子科技集团公司第四十一研究所 Instrument programmed control system and method supporting USBTMC protocol based on PCIe bus
CN105650064A (en) * 2016-03-06 2016-06-08 浙江大学 Pneumatic position servo controller based on DSP
CN105650064B (en) * 2016-03-06 2018-01-12 浙江大学 Based on the position of pneumatic servo controller dsp
CN107885694A (en) * 2017-10-18 2018-04-06 广东高云半导体科技股份有限公司 Support system-level integrated circuit chip

Similar Documents

Publication Publication Date Title
US6064626A (en) Peripheral buses for integrated circuit
US7212961B2 (en) Interface for rapid prototyping system
Bjerregaard et al. An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip
CN201518052U (en) Portable all-digital relay protection transient closed-loop tester
CN1604088A (en) Fault collection and detection apparatus and method
CN101408902A (en) Method for acquiring and transporting high speed data based on FPGA and USB bus
CN201886122U (en) PXI (PCI extension for instrumentation) bus-based digital testing module
US20080270667A1 (en) Serialization of data for communication with master in multi-chip bus implementation
US20080270650A1 (en) Serialization of data for multi-chip bus implementation
CN102136970A (en) LXI-based parallel multi-channel reconfigurable instrument
CN101819556A (en) Signal-processing board
CN201583944U (en) PCI bus based real-time acquisition card realized by adopting FPGA
CN1869959A (en) System for multi-user sharing internal and external storage of computer
CN102833002A (en) Data transmission device and method supporting fibre channel protocol
Salminen et al. HIBI-based multiprocessor SoC on FPGA
CN101482856A (en) Serial-parallel protocol conversion apparatus based on field programmable gate array
CN101907881A (en) Programmable digital pulse generator
CN103885919A (en) Multi-DSP and multi-FPGA parallel processing system and implement method
CN201708773U (en) Arbitrarywaveform generator
CN101713813A (en) SOC (system on chip) chip and method for testing same
CN103176068A (en) Bus-based test module
Anikeev et al. CDF level 2 trigger upgrade
CN101588175A (en) FPGA array processing board
CN103092194A (en) Performance test device and method of general servo mechanism based on universal serial bus (USB)
CN101963948A (en) BMCH protocol data transceiver module based on CPCI bus

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C02 Deemed withdrawal of patent application after publication (patent law 2001)