CN101509805A - Multi-channel Parallel Data Acquisition System Based on Field Programmable Gate Array - Google Patents
Multi-channel Parallel Data Acquisition System Based on Field Programmable Gate Array Download PDFInfo
- Publication number
- CN101509805A CN101509805A CNA2009100484403A CN200910048440A CN101509805A CN 101509805 A CN101509805 A CN 101509805A CN A2009100484403 A CNA2009100484403 A CN A2009100484403A CN 200910048440 A CN200910048440 A CN 200910048440A CN 101509805 A CN101509805 A CN 101509805A
- Authority
- CN
- China
- Prior art keywords
- adc
- module
- control
- fpga chip
- storer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 19
- 230000002093 peripheral effect Effects 0.000 claims abstract description 11
- 230000003750 conditioning effect Effects 0.000 claims abstract description 6
- 230000001360 synchronised effect Effects 0.000 claims description 12
- 238000012546 transfer Methods 0.000 claims description 10
- 230000005540 biological transmission Effects 0.000 claims description 8
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 19
- 238000012545 processing Methods 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 4
- 230000007774 longterm Effects 0.000 abstract 1
- 238000013461 design Methods 0.000 description 13
- ATHVAWFAEPLPPQ-VRDBWYNSSA-N 1-stearoyl-2-oleoyl-sn-glycero-3-phosphocholine Chemical compound CCCCCCCCCCCCCCCCCC(=O)OC[C@H](COP([O-])(=O)OCC[N+](C)(C)C)OC(=O)CCCCCCC\C=C/CCCCCCCC ATHVAWFAEPLPPQ-VRDBWYNSSA-N 0.000 description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000036541 health Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 241000218691 Cupressaceae Species 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000033772 system development Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
Abstract
A multipath parallel data acquisition system based on a field programmable gate array is composed of an analog conditioning module, an ADC module, a power supply module, keys, a USB, an FPGA chip, a JTAG, an EPCS, an SDRAM memory, an SRAM memory, a Flash memory and an upper computer; the USB realizes the communication between the FPGA chip and the upper computer; the peripheral equipment SDRAM memory, JTAG and EPCS are respectively connected to an Avalon bus in the FPGA chip through respective control cores, and the SRAM memory and the Flash memory are connected to the Avalon bus through a three-state bus; the power module provides power for all the devices. The invention effectively solves the contradiction of long-term occupation of CPU resources in the ADC conversion and processing processes, and has the characteristics of simple structure and rapid data reading and storing.
Description
Technical field
The present invention relates to data acquisition, particularly a kind of multipath paralleling data acquisition system based on field programmable gate array (Field ProgrammableGate Array abbreviates FPGA as).
Background technology
Survey in the sound system at laser-Doppler, the emission beam of laser is to the interface of air and water, detecting the signal of gained can realize knowing the transmission frequency of sound field under water by the vibration frequency measurement of water termination through velocity solution mediation frequency discrimination, the gained signal passes through opto-electronic conversion again, obtain carrying the electric signal of phase information, realize communicating by letter of submarine target and above water platform by data acquisition system (DAS) then.
Because the fluctuation of the water surface and the disturbance of wave, the laser acquisition signal many times can not arrive receiving system, in order to allow as much as possible the returning of laser acquisition signal arrive the receiving telescope system, has adopted the method for array detection; This method requires the data acquisition system (DAS) of above water platform can gather and handle the multiplexed detection signal in real time.Data acquisition is stuck in every field and is used widely, but existing various data collecting card product, can not satisfy simultaneously multidiameter delay, at a high speed, high-precision requirement, this is not only because analog to digital converter (Analog to DigitalConverters, abbreviate ADC as) restraining factors of aspect, the factor of cost and the factor of processor are also arranged simultaneously.In solving multichannel synchronous acquisition scheme, traditional method for designing is based on FPGA+ digital signal processor (Digital Signal Processing abbreviates DSP as).Figure one described a kind of parallel duplex data acquisition system (DAS) based on FPGA and DSP (referring to Wang Wenwu, Cao Zhiguo etc. based on the design [J] of the parallel data acquisition system of FPGA and DSP. microcomputer information, 2004,20 (11): 68,69,36).Multichannel analog signals is by behind the impedance matching circuit 11, by FPGA13 control ADC change-over circuit 12 is analog signal conversion digital signal, data after the conversion through buffering after, by the data bus reading of data and carry out respective handling, the data after the processing are delivered to host computer 15 and are shown by DSP14.This system adopts FPGA to realize control, realizes signal Processing with DSP, and this system that not only makes need adopt FPGA and DSP simultaneously, and the simultaneity factor transfer rate is subjected to the influence that connects between FPGA circuit board and the DSP circuit board.Adopt random access memory (Random Access Memory abbreviates RAM as) as data storage medium, and the internal RAM resource of FPGA is very limited, this has just limited message transmission rate.In system extension,, the resource on the DSP make the adjustment of system and expansion be subjected to certain restriction because can not arbitrarily changing.
Summary of the invention
Purpose of the present invention is exactly the deficiency that will overcome above-mentioned data acquisition system (DAS), a kind of multipath paralleling data acquisition system based on field programmable gate array is provided, the present invention should solve the contradiction that in ADC conversion and the processing procedure cpu resource is taken for a long time effectively, has the characteristics that read fast and store simple in structure, data.
Technical solution of the present invention is as follows:
A kind of multipath paralleling data acquisition system based on field programmable gate array, the formation of this system is by simulated modulation module, the ADC module, power module, button, USB (universal serial bus) (Universal Serial BUS, abbreviate USB as), fpga chip, joint test debugging interface (Joint Test Action Group, abbreviate JTAG as), enhancement mode series arrangement device (Enhanced Configuration Devices Serial, abbreviate EPCS as), synchronous DRAM (Synchronous Dynamic Random Access Memory, abbreviate the SDRAM storer as), static RAM (Static Random Access Memory abbreviates the SRAM storer as), Flash storer and host computer constitute; The inside of described fpga chip is formed and comprised: NiosII processor, Avalon bus, by key control nuclear, JTAG control nuclear, EPCS control nuclear, SDRAM control nuclear, tristate bus line, USB control nuclear, DMA control nuclear, ADC control module, described USB are realized communicating by letter between fpga chip and the host computer; Described peripherals SDRAM storer, JTAG, EPCS examine by control separately respectively and are connected on the Avalon bus of fpga chip inside, and SRAM storer, Flash storer are connected on the Avalon bus by tristate bus line; Described power module provides power supply for above-mentioned all equipment; Described button starts native system and enters duty, the simulating signal that needs to gather is through described simulated modulation module, the voltage amplitude of regulating simulating signal is to the scope of ADC module acceptance, simulating signal after the conditioning is 16 parallel position digital signals through the ADC module converts, enter fpga chip, by the control of the DMA in the fpga chip nuclear data are directly stored among the described SDRAM, the data among the SDRAM transfer to described host computer by USB and show after handling through fpga chip.
Described simulated modulation module is made up of 64 identical sub-modulate circuits.
Described ADC module is made of 8 16 ADC chip, every ADC chip can be realized 8 tunnel 16 bit data synchronous acquisition and conversions, described ADC control module is made of 8 ADC control nuclears, each control nuclear is used to drive a slice ADC chip, and described DMA control module is made of 8 DMA control nuclears accordingly.
Described USB is the USB2.0 that maximum transmission rate can reach 480Mbps.
Circuit board in the system of the present invention adopts the structure of bottom version+core board, the integrated described simulated modulation module of described bottom version, ADC module, power module, button, USB; The integrated fpga chip of described core board, JTAG, EPCS, SDRAM, SRAM, Flash storer; Be connected to each other with contact pin by three plug sockets between described bottom version and the core board and be in the same place.
Native system utilizes the SOPC method for designing to carry out hardware and software development, its design cycle such as Fig. 3, design is divided into three bulks altogether: the hardware design among the hardware system developing instrument SOPC Builder, NiosII Integrated Development Environment (Integrated Development Environment, abbreviate IDE as) in software design, carry out logic synthesis placement-and-routing among the QuartusII.The drive pattern of the guide intuitively user interface that provides by SOPC Builder system development tool, configuration processor, select and configuring external device control nuclear, distribute address, interruption, by the Avalon bus they are coupled together and create required hardware system.In QuartusII, call the hardware system of establishment, give pin on each module assignment fpga chip in the hardware system according to circuit-board laying-out, write other hardware description languages (Hardware Description Language of test file and user design, abbreviate HDL as) file, carry out logic synthesis, placement-and-routing and emulation to hardware system and generate hardware profile.In software design, call each external unit and drive headers and libraries, carry out multi-task scheduling based on the real time operating system that can deprive kernel, make each task of processor energy summary responses, compiling debugging back generates executable code.At last hardware profile and executable code are downloaded to and carry out in the circuit board debugging on the sheet by downloading line.
Technique effect of the present invention is as follows:
1, realized the synchronous acquisition of 64 tunnel simulating signals by 8 ADC of FPGA control, the data that collect are examined by the DMA control of FPGA inside and have been showed reading fast and storing of data, can solve the contradiction that in ADC conversion and the processing procedure cpu resource is taken for a long time simultaneously effectively.
2, adopt the SOPC method for designing of Altera release, on a slice FPGA, realized the parallel acquisition of multichannel data.
3, pin on the fpga chip and storage resources can carry out freely distributing according to design proposal, have very big dirigibility.
4, in the software design, adopt task scheduling method for designing, strengthened the real-time of system based on real time operating system.
5, communicate by letter with host computer by USB, message transmission rate can reach 192Mbps, and the system that makes can be applied in the high-speed data acquistion system.
6, designed the structure of bottom version+core board, core board is applicable to different bottom versions, makes things convenient for system update and expansion.
Description of drawings
Fig. 1 is existing multiplexed signal sampling system architecture synoptic diagram based on FPGA and DSP
Fig. 2 is the multichannel synchronous acquisition system architecture synoptic diagram that the present invention is based on FPGA
Fig. 3 is the system hardware and software design flow diagram
Fig. 4 is an ADC acquisition controlling structural representation
Fig. 5 is the multi-task scheduling process flow diagram
Among the figure: the 21-simulated modulation module, the 22-ADC module, the 23-FPGA chip, the 24-power module, the 25-button, 26-JTAG, 27-EPCS, 28-SDRAM, 29-SRAM, the 210-Flash storer, 211-USB, the 212-host computer, the 231-NiosII processor, the 232-Avalon bus, 233-is by key control nuclear, 234-JTAG controls nuclear, 235-EPCS controls nuclear, 236-SDRAM controls nuclear, the 237-tristate bus line, 238-USB controls nuclear, the 2310-DMA control module, the 2311-ADC control module; 41-ADC chip, 42-ADC control nuclear, 421-FIFO impact damper, the 43-first sub-modulate circuit, the 44-second sub-modulate circuit, 45-the 3rd sub-modulate circuit, 46-the 4th sub-modulate circuit, 47-the 5th sub-modulate circuit, 48-the 6th sub-modulate circuit, 49-the 7th sub-modulate circuit, 410-the 8th sub-modulate circuit.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.
See also Fig. 2 earlier, Fig. 2 is the structural representation that the present invention is based on the multichannel synchronous acquisition system most preferred embodiment of FPGA, as seen from the figure, the present invention is based on the multipath paralleling data acquisition system of field programmable gate array, this system is by simulated modulation module 21, ADC module 22, power module 24, button 25, USB211, and fpga chip 23, JTAG26, EPCS27, SDRAM storer 28, SRAM storer 29, Flash storer 210 and host computer 212 constitute;
The inside of described fpga chip is formed and comprised: NiosII processor 231, Avalon bus 232, by key control nuclear 233, JTAG control nuclear 234, EPCS control nuclear 235, SDRAM control nuclear 236, tristate bus line 237, USB control nuclear 238, DMA control module 2310, ADC control module 2311, described USB211 are realized communicating by letter between fpga chip 23 and the host computer 212; Described peripherals SDRAM storer 28, JTAG26, EPCS27 examine by control separately respectively and are connected on the Avalon bus of fpga chip 23 inside, and SRAM storer 29, Flash storer 210 are connected on the Avalon bus by tristate bus line 237; Described power module 24 provides power supply for above-mentioned all equipment; Described button 25 starts native system and enters duty, the simulating signal that needs to gather is through described simulated modulation module 21, the voltage amplitude of regulating simulating signal is to the scope of ADC module 22 acceptance, simulating signal after the conditioning is converted to 16 parallel position digital signals through ADC module 22, enter fpga chip 23, DMA control nuclear by the DMA control module 2310 in the fpga chip directly stores data in the described SDRAM storer 28, after data in the SDRAM storer 28 are handled through fpga chip 23, transfer to described host computer 212 by USB211 and show.
In the present embodiment, described simulated modulation module 21 is made up of 64 identical sub-modulate circuits.Described ADC module 22 is made of 8 16 ADC chip, every ADC chip can be realized 8 tunnel 16 bit data synchronous acquisition and conversions, ADC control module 2311 is made of 8 ADC control nuclears, each control nuclear is used to drive a slice ADC chip, and described DMA control module 2310 is made of 8 DMA control nuclears accordingly.
Circuit board in the system of present embodiment adopts bottom version and core board structure combining, the integrated described simulated modulation module 21 of bottom version, ADC module 22, power module 24, button 25, USB211; The integrated fpga chip 23 of described core board, JTAG26, EPCS27, SDRAM storer 28, SRAM storer 29, Flash storer 210; Contact pins by 50 pins of three rows between described bottom version and the core board are connected to each other with socket and are in the same place.Described USB211 is the USB2.0 that maximum transmission rate can reach 480Mbps.
Described power module 24 ± the 15V power supply is as the input power supply of entire circuit plate, produces 3.3V, 2.5V respectively and 1.8V voltage is each peripherals and fpga chip power supply by the voltage transitions chip.Fig. 4 is an ADC acquisition controlling structural representation
Fig. 4 is an ADC acquisition controlling structural representation, the two-way difference output simulating signal of each the sub-conditioning module on the bottom version connects a pair of differential input end of ADC chip 41, every ADC has 8 pairs of differential input ends, the differential analog signal that connects 8 sub-conditioning module respectively, every ADC is connected on the Avalon bus 232 by an ADC control nuclear 42.Button 25, JTAG26, EPCS27, SDRAM28, USB211 are connected on the Avalon bus 232 of FPGA inside by control corresponding nuclear respectively, and SRAM storer 29 and Flash storer 210 are connected on the Avalon bus 237 by tristate bus line.The NiosII processor 231 of FPGA inside and DMA control module 2310 are connected on the Avalon bus, communicate with other devices.USB port on the USB211 data line connecting circuit plate and the USB port on the host computer 212 communicate.
Described simulated modulation module 21 is made up of 64 identical sub-modulate circuits, and each sub-modulate circuit is nursed one's health one tunnel simulating signal, and the simulating signal after the conditioning outputs to ADC module 22 in the mode of difference output.Described ADC module 22 is made up of 8 ADC chips, and every ADC chip can be imported 8 road differential signals and realize 8 tunnel simulating signal synchronous acquisition and conversions, and conversion accuracy need reach 16.DNA control module 2310 is made up of 8 identical DMA control nuclears.Data after the ADC conversion are transferred in the SDRAM storer 28 fast by DMA control nuclear.
Described control nuclear need design the control of ADC control nuclear and USB voluntarily and examine.
The CycloneII series that the described fpga chip 23 of present embodiment is an altera corp adopts the method based on the design of SOPC software-hardware synergism.Carry out software development based on the NiosII processor, adopt real time operating system to improve the real-time of system in the software design.
Described external memory system constitutes mass storage by the SDRAM storer of 8MB32 position, the SRAM storer of 512KB32 position and the Flash storer of 8MBYTE16 position.
Because the message transmission rate in the system need reach 112Mbps, general serial ports and network interface are difficult to reach requirement, adopt peripheral element extension interface (Pedpherd Component Interconnect, abbreviate PCI as) can satisfy this transmission rate request, but so not only increase the volume of system, and do not support hot plug; We have adopted the USB2.0 by supporting hot plug to communicate by letter with host computer 212, and transfer rate can reach more than the 112Mbps.
In the system hardware and software design, the control nuclear that calls each peripherals by the SOPC method for designing makes up hardware system, in QuartusII, call the hardware system of establishment, distribute the pin on the fpga chip, write other hdl files of test file and user design, hardware system is carried out logic synthesis, placement-and-routing and emulation generate hardware profile, utilize by JTAG26 and download the line download configuration file in circuit board.Write software program based on microcontroller operating system (Microcontroller Operating System abbreviates UC/OSII as), adopt the method for multi-task scheduling.In the NiosII processor, write and the debugging software program, after compiling is passed through, download to circuit board by download bundle of lines software program and carry out online hardware debug, debugging finishes the back configuration file is downloaded among the EPCS, downloads in the Flash storer 210 by downloading the bundle of lines program.After system powered on, the program and the data that load automatically in the Flash storer were moved to SRAM storer 29.
The course of work is as follows:
As shown in Figure 4, every road simulating signal is changed through entering ADC module 22 behind the different analog submodule modulate circuits respectively, per 8 tunnel simulating signals are exported by a delivery outlet serial by a slice ADC chip conversion back, the data of serial output are by FPGA control string and conversion, and inner first-in first-out (First Input First Output the abbreviates FIFO as) impact damper by the macroblock customization of ADC control nuclear that deposits ADC control module 2311 in cushions.When 8 tunnel simulating signals all behind the EOC, produce IE, the dma module 2310 among Fig. 2 transfers data in the SDRAM storer 29.After data in the SDRAM storer 29 were handled through NiosII processor 231, the control panel that transfers to host computer 212 by USB211 showed in real time.In gatherer process, can start the ADC conversion, make ADC enter low-power consumption mode, enable 8 ADC synchronous acquisition by button.In software design, adopt multi-task scheduling method shown in Figure 5, create keyboard task, low-power consumption mode task, synchronous acquisition task, DMA transformation task, data processing task and output based on real time operating system and shown task.Give priority of each Task Distribution, adopt dynamic priority scheduling, make that each task can obtain handling immediately, communicate by signal quantity set and semaphore between each task.
Start reading of serial data after ADC module 22 conversion and transmit by button 25, collection transfer process such as Fig. 4 of every ADC chip: 8 way modulate circuits 43～410 are nursed one's health 8 tunnel simulating signals respectively, simulating signal difference after the conditioning outputs to ADC chip 41, the collection of the ADC control nuclear 42 control ADC chips 41 of FPGA inside and the string and the conversion of output digital signal, parallel 16 position digital signals after the conversion are cached to fifo buffer 421, behind 8 whole EOCs of passage of every ADC chip, produce and interrupt, start DMA control module 2310 and transfer data to SDRAM storer 28, data are after the NiosII processor processing, and the control panel that transfers to host computer 212 by peripheral general-purpose serial bus USB 211 shows in real time.
Described power module 24 can adopt L7805, AMS1117-3.3, AMS1117-2.5, or AMS1117-1.8.ADC modular converter 22 has adopted the ADS1178 of Texas Instrument's (Texas Instruments abbreviates TI as) up-to-date release of company, and simulated modulation module 21 mainly is made up of OPA350, OPA1632, REF1004.Fpga chip 23 adopts the EP2C35F484C8 of the CycloneII series of Altera.USB chip 211 adopts the USB2.0 chip CY7C68013 of Cypress company.Peripheral storage is made of the K4S641632SDRAM28 of two 8MB32 positions, the IS61LV25616AL SRAM29 of 512KB32 position and the JS28F640Flash storer 210 of a slice 8MBYTE16 position.
When making up hardware system in SOPC Builder, Altera only provides the control nuclear of general module, need write the control nuclear of ADC and USB2.0 by system.System passes through collection, buffer memory and string and the conversion of fpga chip 23 control ADC modules 22 data, and directly transmits data to peripheral storage by DMA.
The method that the software-hardware synergism based on SOPC that the present invention has adopted altera corp to release designs designs the control of self-defined peripheral hardware and examines, and communicates by letter with host computer by USB2.0, adopts the method for designing of bottom version+core board in board design.For improving the real-time of system, adopted design proposal in the software program design based on the UC/OSII real time operating system.Not only on a slice fpga chip, realized multichannel data parallel acquisition and demonstration in real time, conveniently realized the software and hardware system exploitation, had very big dirigibility simultaneously and can expand.
Claims (5)
1, a kind of multipath paralleling data acquisition system based on field programmable gate array, be characterised in that this system by simulated modulation module (21), ADC module (22), power module (24), button (25), USB (211), fpga chip (23), JTAG (26), EPCS (27), SDRAM storer (28), SRAM storer (29), Flash storer (210) and host computer (212) constitute; The inside of described fpga chip is formed and comprised: NiosII processor (231), Avalon bus (232), by key control nuclear (233), JTAG control nuclear (234), EPCS control nuclear (235), SDRAM control nuclear (236), tristate bus line (237), USB control nuclear (238), DMA control module (2310), ADC control module (2311), described USB (211) are realized communicating by letter between fpga chip (23) and the host computer (212); Described peripherals SDRAM storer (28), JTAG (26), EPCS (27) examine by control separately respectively and are connected on the inner Avalon bus of fpga chip (23), and SRAM storer (29), Flash storer (210) are connected on the Avalon bus by tristate bus line (237); Described power module (24) provides power supply for above-mentioned all equipment; Described button (25) starts native system and enters duty, the simulating signal that needs to gather is through described simulated modulation module (21), the voltage amplitude of regulating simulating signal is to the scope of ADC module (22) acceptance, simulating signal after the conditioning is converted to 16 parallel position digital signals through ADC module (22), enter fpga chip (23), by the control of the DMA in the fpga chip nuclear data are directly stored in the described SDRAM storer (28), data in the SDRAM storer (28) transfer to described host computer (212) by USB (211) and show after handling through fpga chip (23).
2, multipath paralleling data acquisition system according to claim 1 is characterized in that described simulated modulation module (21) is made up of 64 identical sub-modulate circuits.
3, multipath paralleling data acquisition system according to claim 1, it is characterized in that described ADC module (22) is made of 8 16 ADC chip, every ADC chip can be realized 8 tunnel 16 bit data synchronous acquisition and conversions, ADC control module (2311) is made of 8 ADC control nuclears, each control nuclear is used to drive a slice ADC chip, and described DMA control module (2310) is made of 8 DMA control nuclears accordingly.
4, multipath paralleling data acquisition system according to claim 1 is characterized in that described USB (211) can reach the USB2.0 of 480Mbps for maximum transmission rate.
5, multipath paralleling data acquisition system according to claim 1, it is characterized in that circuit board in the system adopts the structure of bottom version and core board, the integrated described simulated modulation module of described bottom version (21), ADC module (22), power module (24), button (25), USB (211); The integrated fpga chip of described core board (23), JTAG (26), EPCS (27), SDRAM storer (28), SRAM storer (29), Flash storer (210); Be connected to each other with contact pin by three plug sockets between described bottom version and the core board and be in the same place.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100484403A CN101509805A (en) | 2009-03-27 | 2009-03-27 | Multi-channel Parallel Data Acquisition System Based on Field Programmable Gate Array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2009100484403A CN101509805A (en) | 2009-03-27 | 2009-03-27 | Multi-channel Parallel Data Acquisition System Based on Field Programmable Gate Array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101509805A true CN101509805A (en) | 2009-08-19 |
Family
ID=41002274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2009100484403A Pending CN101509805A (en) | 2009-03-27 | 2009-03-27 | Multi-channel Parallel Data Acquisition System Based on Field Programmable Gate Array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101509805A (en) |
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243097A (en) * | 2010-05-13 | 2011-11-16 | 西安博能电力技术有限公司 | Online audio diagnosis system and method for full-closed combined electric appliance |
| CN102346455A (en) * | 2011-04-29 | 2012-02-08 | 山东科汇电力自动化有限公司 | Design method of sampling module |
| CN101714103B (en) * | 2009-12-15 | 2012-11-28 | 中国华录·松下电子信息有限公司 | Task dispatcher based on programmable logic device |
| CN102030018B (en) * | 2009-09-28 | 2013-01-16 | 西门子信号有限公司 | Attached peripheral data acquisition and distribution device for axis counting system |
| CN103235542A (en) * | 2013-02-01 | 2013-08-07 | 哈尔滨理工大学 | Field programmable gate array (FPGA)-based multipath standard signal acquisition and transmission device |
| CN103246225A (en) * | 2013-05-03 | 2013-08-14 | 奇瑞汽车股份有限公司 | FPGA (Field Programmable Gata Array)-based multiway simultaneous sampling system realized by LVDS (Low Voltage Differential Signaling) interfaces |
| CN103297055A (en) * | 2013-03-19 | 2013-09-11 | 中国科学院声学研究所 | Device for achieving multipath serial ADC synchronization by adopting FPGA |
| CN103970701A (en) * | 2014-05-28 | 2014-08-06 | 吉林大学 | Field-programmable gate array based real-time synchronous data acquisition intellectual property core |
| CN104021098A (en) * | 2014-06-19 | 2014-09-03 | 福州闽台机械有限公司 | Multi-board collaboration architecture based on DMA transparent transmission |
| CN104408001A (en) * | 2014-12-11 | 2015-03-11 | 哈尔滨工程大学 | High-accuracy multipath data synchronous acquisition device |
| CN105116793A (en) * | 2015-07-20 | 2015-12-02 | 中国科学院西安光学精密机械研究所 | Acquisition system and acquisition method for reconfigurable control panel |
| CN105243040A (en) * | 2015-11-11 | 2016-01-13 | 中国电子科技集团公司第四十一研究所 | Instrument programmed control system and method supporting USBTMC protocol based on PCIe bus |
| CN105425028A (en) * | 2015-10-27 | 2016-03-23 | 中国电子科技集团公司第四十一研究所 | Microwave power measurer based on FPGA |
| CN105650064A (en) * | 2016-03-06 | 2016-06-08 | 浙江大学 | Pneumatic position servo controller based on DSP |
| CN107885694A (en) * | 2017-10-18 | 2018-04-06 | 广东高云半导体科技股份有限公司 | One kind supports system on a ship chip |
| CN108803418A (en) * | 2018-06-12 | 2018-11-13 | 上海航天计算机技术研究所 | A kind of AD automated collection systems that FPGA is realized |
| CN108918429A (en) * | 2018-06-20 | 2018-11-30 | 中国科学院西安光学精密机械研究所 | Online and offline spectral data acquisition device based on linear array detector |
| CN109030926A (en) * | 2018-06-28 | 2018-12-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multichannel voltage acquisition module |
| CN109936674A (en) * | 2017-11-22 | 2019-06-25 | 柯尼卡美能达株式会社 | Image forming apparatus and the computer-readable recording medium for storing program |
| CN110109853A (en) * | 2019-04-04 | 2019-08-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing (DAP) device and method |
| CN112257108A (en) * | 2020-10-23 | 2021-01-22 | 天津新开心生活科技有限公司 | Data desensitization method and device, medium and electronic equipment |
| CN112859656A (en) * | 2019-11-27 | 2021-05-28 | 成都锐成芯微科技股份有限公司 | Multi-channel data acquisition control system |
| CN113504847A (en) * | 2021-07-16 | 2021-10-15 | 中航华东光电有限公司 | FPGA-based capacitive touch screen signal sampling system and method |
| CN116388760A (en) * | 2023-06-06 | 2023-07-04 | 上海泰矽微电子有限公司 | Static performance testing device and method for differential input ADC |
-
2009
- 2009-03-27 CN CNA2009100484403A patent/CN101509805A/en active Pending
Cited By (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102030018B (en) * | 2009-09-28 | 2013-01-16 | 西门子信号有限公司 | Attached peripheral data acquisition and distribution device for axis counting system |
| CN101714103B (en) * | 2009-12-15 | 2012-11-28 | 中国华录·松下电子信息有限公司 | Task dispatcher based on programmable logic device |
| CN102243097A (en) * | 2010-05-13 | 2011-11-16 | 西安博能电力技术有限公司 | Online audio diagnosis system and method for full-closed combined electric appliance |
| CN102346455A (en) * | 2011-04-29 | 2012-02-08 | 山东科汇电力自动化有限公司 | Design method of sampling module |
| CN102346455B (en) * | 2011-04-29 | 2013-07-10 | 山东科汇电力自动化有限公司 | Design method of sampling module |
| CN103235542A (en) * | 2013-02-01 | 2013-08-07 | 哈尔滨理工大学 | Field programmable gate array (FPGA)-based multipath standard signal acquisition and transmission device |
| CN103297055A (en) * | 2013-03-19 | 2013-09-11 | 中国科学院声学研究所 | Device for achieving multipath serial ADC synchronization by adopting FPGA |
| CN103246225B (en) * | 2013-05-03 | 2016-06-08 | 奇瑞新能源汽车技术有限公司 | The multichannel that a kind of LVDS interface based on FPGA realizes is sampled system simultaneously |
| CN103246225A (en) * | 2013-05-03 | 2013-08-14 | 奇瑞汽车股份有限公司 | FPGA (Field Programmable Gata Array)-based multiway simultaneous sampling system realized by LVDS (Low Voltage Differential Signaling) interfaces |
| CN103970701B (en) * | 2014-05-28 | 2017-08-25 | 吉林大学 | The IP core of real time data synchronization collection based on field programmable gate array |
| CN103970701A (en) * | 2014-05-28 | 2014-08-06 | 吉林大学 | Field-programmable gate array based real-time synchronous data acquisition intellectual property core |
| CN104021098B (en) * | 2014-06-19 | 2017-05-17 | 福州闽台机械有限公司 | Multi-board collaboration architecture based on DMA transparent transmission |
| CN104021098A (en) * | 2014-06-19 | 2014-09-03 | 福州闽台机械有限公司 | Multi-board collaboration architecture based on DMA transparent transmission |
| CN104408001A (en) * | 2014-12-11 | 2015-03-11 | 哈尔滨工程大学 | High-accuracy multipath data synchronous acquisition device |
| CN104408001B (en) * | 2014-12-11 | 2017-05-31 | 哈尔滨工程大学 | High accuracy multichannel data synchronous acquisition device |
| CN105116793A (en) * | 2015-07-20 | 2015-12-02 | 中国科学院西安光学精密机械研究所 | Acquisition system and acquisition method for reconfigurable control panel |
| CN105425028A (en) * | 2015-10-27 | 2016-03-23 | 中国电子科技集团公司第四十一研究所 | Microwave power measurer based on FPGA |
| CN105243040A (en) * | 2015-11-11 | 2016-01-13 | 中国电子科技集团公司第四十一研究所 | Instrument programmed control system and method supporting USBTMC protocol based on PCIe bus |
| CN105243040B (en) * | 2015-11-11 | 2019-01-18 | 中国电子科技集团公司第四十一研究所 | A kind of instrument stored program controlled and method for supporting USBTMC agreement based on PCIe bus |
| CN105650064B (en) * | 2016-03-06 | 2018-01-12 | 浙江大学 | A kind of Pneumatic position control device based on DSP |
| CN105650064A (en) * | 2016-03-06 | 2016-06-08 | 浙江大学 | Pneumatic position servo controller based on DSP |
| CN107885694A (en) * | 2017-10-18 | 2018-04-06 | 广东高云半导体科技股份有限公司 | One kind supports system on a ship chip |
| CN109936674A (en) * | 2017-11-22 | 2019-06-25 | 柯尼卡美能达株式会社 | Image forming apparatus and the computer-readable recording medium for storing program |
| CN108803418A (en) * | 2018-06-12 | 2018-11-13 | 上海航天计算机技术研究所 | A kind of AD automated collection systems that FPGA is realized |
| CN108918429A (en) * | 2018-06-20 | 2018-11-30 | 中国科学院西安光学精密机械研究所 | Online and offline spectral data acquisition device based on linear array detector |
| CN109030926A (en) * | 2018-06-28 | 2018-12-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multichannel voltage acquisition module |
| CN110109853A (en) * | 2019-04-04 | 2019-08-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Data acquisition and processing (DAP) device and method |
| CN112859656A (en) * | 2019-11-27 | 2021-05-28 | 成都锐成芯微科技股份有限公司 | Multi-channel data acquisition control system |
| CN112257108A (en) * | 2020-10-23 | 2021-01-22 | 天津新开心生活科技有限公司 | Data desensitization method and device, medium and electronic equipment |
| CN113504847A (en) * | 2021-07-16 | 2021-10-15 | 中航华东光电有限公司 | FPGA-based capacitive touch screen signal sampling system and method |
| CN116388760A (en) * | 2023-06-06 | 2023-07-04 | 上海泰矽微电子有限公司 | Static performance testing device and method for differential input ADC |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101509805A (en) | Multi-channel Parallel Data Acquisition System Based on Field Programmable Gate Array | |
| CN102184148B (en) | AT96 bus controller IP (internet protocol) core based on FPGA (field programmable gate array) and construction method thereof | |
| US8532975B2 (en) | System and method implementing a simulation acceleration capture buffer | |
| CN102662835A (en) | Program debugging method of embedded system and embedded system | |
| CN108647368A (en) | Partially dynamical reconfiguration system and method based on FPGA | |
| CN104133171A (en) | Simple boundary scan test system and method based on single-chip microcomputer | |
| CN101706762A (en) | Intelligent type signal transfer system | |
| CN100458731C (en) | Method for checking IC design with hardware logic | |
| CN103049361A (en) | FPGA (Field Programmable Gata Array) with embedded logical analysis function and logical analysis system | |
| CN112187341B (en) | Data simulation source based on FPGA and construction and control method thereof | |
| CN101615030A (en) | The data acquisition unit that a kind of embedded system test is used | |
| CN206021247U (en) | A kind of FVLA based on ARM | |
| CN203260028U (en) | Sensor network SoC prototype verification platform based on FPGA | |
| CN101998135A (en) | System for collecting and playing mobile television signal and control method | |
| CN103926846B (en) | The system that aircraft ammunition simulation generates with fault | |
| CN202795364U (en) | Dynamically reconfigurable test measuring instrument | |
| Guo et al. | A SPI interface module verification method based on UVM | |
| CN205656610U (en) | High performance assembly line ADC frequency domain parameter evaluation system based on soPC | |
| CN201134098Y (en) | Data collecting card based on PXI bus | |
| CN114660383A (en) | Universal ground detection test board card for load manager | |
| CN102662812B (en) | Performance testing system for PCI (peripheral Component Interconnect) bus-based single-way reception demodulator | |
| CN112711213A (en) | Navigation acquisition resolving Soc processing system based on RiscV kernel and method thereof | |
| CN114020603B (en) | Universal integrated FPGA embedded software test verification system | |
| CN108153276A (en) | DCS performance testing devices and method based on SOPC | |
| Zhang et al. | ARM and FPGA heterogeneous accelerated processing system based on HLS and PCIe |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090819 |