CN202362460U

CN202362460U - Intermediate frequency data acquisition and playback device of GNSS receiver

Info

Publication number: CN202362460U
Application number: CN2011203789783U
Authority: CN
Inventors: 潘树国; 王庆; 陈冲
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2011-10-09
Filing date: 2011-10-09
Publication date: 2012-08-01
Anticipated expiration: 2021-10-09

Abstract

The utility model relates to an intermediate frequency data acquisition and playback device of a GNSS receiver. An antenna is connected with a radio frequency front unit. An SPI module is bidirectionally connected with the radio frequency front unit. The radio frequency front unit is connected with an FPGA control unit. The FPGA control unit is bidirectionally connected with a USB interface transmission unit. The USB interface transmission unit is bidirectionally connected with a host computer. The radio frequency front unit receives a satellite signal and outputs an intermediate frequency signal. The SPI module configures the working mode of the radio frequency front unit and carries out the switching of multiple satellite navigation systems. The FPGA control unit carries out the series-to-parallel conversion to the intermediate frequency signal, and then stores the conversion result into an asynchronous FIFO buffer module. A USB interface time sequence module reads the data in the FIFO buffer module, and then writes the data to the USB interface transmission unit. The host computer reads the data from the USB interface transmission unit, and then stores the data to a local hard disk. During the data playback, a data stream after the format conversion is transmitted to an intermediate frequency input terminal of a base band under the triggering of a base-band clock and the control of the host computer.

Description

A kind of intermediate frequency data collection and playback reproducer of GNSS receiver

Technical field

The present invention relates to the GNSS Satellite Navigation Set, especially a kind of intermediate frequency data collection and playback reproducer of GNSS receiver are specially adapted to the research and development based on multimode GNSS receiver of satellite navigation system.

Background technology

Along with building up with perfect of the various navigational satellite systems in the whole world, being widely used of satellite navigation location receiver changed many constellations into and deposited the compatible GNSS New Times from the single GPS epoch, caused the globalization of satellite navigation system and strengthened multimodeization.And progressively the improving and strengthen of GNSS system makes compatible and interoperability becomes one of focus of new concern, and how makes full use of and bring into play the advantage of multisystem from optimal angle, is a kind of trend of future development.GNSS receiver based on software and radio technique has very big advantage at aspects such as feeble signal processing and many signal compatibilities.And in the GNSS receiver, in order to carry out emulation and checking to catching, follow the tracks of and locate scheduling algorithm, the optimized Algorithm performance often needs real-time True Data to go algorithm is carried out emulation and test.

Summary of the invention

The utility model provides a kind of intermediate frequency data collection and playback reproducer of GNSS receiver, its objective is, when the PC platform carries out algorithm development, needs real intermediate frequency data to come the function and the performance of algorithm are verified.And in the debugging of carrying out receiver, we need satellite data stream continuous, that satisfy the base band requirement, and the realization of data readback function; Solved the problem that to go to the open air to debug; Making the algorithm development and the debugging of receiver only needs once open-air data acquisition, and follow-up can all carrying out indoor; Improve development efficiency, shortened the development time.

The utility model purpose is achieved in that a kind of intermediate frequency data collection and playback reproducer of GNSS receiver, it is characterized in that: comprise antenna, be provided with multimode GNSS receiver chip the radio-frequency front-end unit, be provided with SPI program module, string and modular converter, asynchronous FIFO buffer module, USB interface tfi module and total state machine module the FPGA control module, be provided with the USB interface transmission unit and the host computer of firmware program and driver; Antenna connects the radio-frequency front-end unit, the two-way connection radio-frequency front-end of SPI program module unit, and the radio-frequency front-end unit connects FPGA control module, the two-way connection USB interface of FPGA control module transmission unit, the two-way connection host computer of USB interface transmission unit; The radio-frequency front-end unit is through antenna received RF satellite-signal; Export intermediate-freuqncy signal through after LNA, mixing and the A/D sample conversion; The SPI program module is configured the mode of operation of radio frequency front end unit; Realization is to the switching of a plurality of satellite navigation systems of comprising 2 generations of GPS, the Big Dipper, GLANASS and Galileo; After the FPGA control module is gone here and there to the intermediate-freuqncy signal of radio frequency front end unit output and changed, become parallel data and be deposited into the asynchronous FIFO buffer module, after the USB interface tfi module is read the data in the asynchronous FIFO buffer module; Be written in the USB interface transmission unit, the data storage that host computer procedure will read from the USB interface transmission unit is to the hard disk of this locality.During data readback, under the control of host computer procedure, will pass through the data stream of format conversion, under the triggering of base band clock, be transferred to the middle frequency input terminal of base band.

Host computer transmits when control through program to the FPGA control module, adopts asynchronous I/O and multi-threading and round-robin queue's dispatching method, continuity and real-time in the assurance high speed data transfer, at last with the data storage that collects in the hard disk of this locality.

When system carries out data acquisition,, just need make the writing speed of the reading speed of host computer greater than radio-frequency front-end in order to guarantee the continuity of data.Therefore, the firmware program configuration in the USB interface transmission unit as follows: transfer rate is set to (High-Speed) at a high speed, and transport-type is set to bulk transfer (BULK transmission), and mode of operation is set to asynchronous SLAVEFIFO pattern.When system carries out data readback, need dispose as follows by the USB firmware program: transfer rate is set to (Full-Speed) at a high speed, and transport-type is set to bulk transfer (BULK transmission), and mode of operation is set to asynchronous SLAVEFIFO pattern.Simultaneously, in hardware connects, asynchronously read the CLK pin that pin SLRD need be directly connected to the base band clock.

The utility model compared with prior art has following advantage and remarkable result:

(1) under the current a plurality of satellite navigation systems and the situation of depositing; Adopt multimode GNSS receiver chip; Radio frequency front end chip is carried out the switching of pattern through SPI program among the FPGA; Solve data acquisition system (DAS) in the past and be directed against perhaps a kind of problem of signal of GPS L1 signal merely, multimode GNSS receiver chip, the external antenna active/passive is optional.Can gather a plurality of satellite system signal, the mode of operation switching of radio-frequency front-end is configured by the SPI program and gets final product, and be convenient to the user and carry out the selectivity exploitation, applied range, more later user carries out many compatible systems exploitations and facilitates.

(2) data cache module utilizes the inner in-line memory of FPGA to realize asynchronous FIFO; Compare with the existing external SRAM chip buffering that adopts; Provide cost savings; And more can easily revise the FIFO depth size, and adapt to the occasion of different fpga chips, different IF sampling rate, be more conducive to versatility, the portability of program.

(3) epigynous computer section adopts multithreading and round-robin queue's request technology to solve the problem of loss of data in the high speed data transfer; Make the transmission speed of system be improved significantly; Data acquisition system (DAS) can be operated at a high speed, real-time occasion, is convenient to carry out the research and development of real-time software receiving machine.

(4) on the function basis of data acquisition, increased data readback, hardware need not any change, only needs to revise host computer procedure and firmware driver, can realize the intermediate frequency data playback.Have only the platform of acquisition function to compare with similar, function is more powerful, and cost performance is higher.For the user carries out receiver base band algorithm, the navigation calculation exploitation provides real-time, stable intermediate-freuqncy signal stream; Make at the beginning of the whole R&D process, only need carry out once outdoor collection, the receiver debugging of follow-up reality can be carried out indoor fully; Save debug time, improved development efficiency.

Description of drawings

Fig. 1 is the theory diagram of the utility model;

Fig. 2 is FPGA of the present invention and radio frequency front end chip interface principle figure;

Fig. 3 is the fpga chip part interface principle figure of the utility model;

Fig. 4 is the FPGA and the USB chip interface schematic diagram of the utility model;

Fig. 5 is inner each the module RTL level schematic diagram of the FPGA program of the utility model;

Fig. 6 is the total state machine module state transition diagram in the FPGA program of the utility model;

Fig. 7 is that the mode of operation of the radio-frequency front-end unit of the utility model is switched the SPI sequential chart;

Fig. 8 is the USB chip firmware program process flow diagram of the utility model;

Fig. 9 is the host computer application flows figure of the utility model.

Embodiment

As shown in Figure 1; The utility model is to gather and the playback platform based on the multimode GNSS intermediate frequency data of multimode GNSS satellite receiving chip, fpga chip, USB chip, host computer, constitutes to comprise radio-frequency front-end unit, FPGA control module, USB interface transmission unit and host computer.

Wherein, the SPI program of FPGA inside is accomplished the switching of radio-frequency front-end mode of operation separately as a module and the two-way communication of radio-frequency front-end unit.In the data acquisition function, FPGA control module inside comprises four modules: string and modular converter, asynchronous FIFO buffer module, USB interface tfi module and total state machine (FSM) module.Unidirectional string and the modulus of conversion module of being connected in radio-frequency front-end unit, follow-up is asynchronous FIFO buffer module, USB interface tfi module, total state machine module.FPGA is connected with the USB chip is two-way.USB chip and host computer also are two-way communication.Its workflow is following:

At first, the data total amount that read is set in host computer; Then, host computer sends initiation command through control transmission end points 0, makes the PA.7 pin output high level of USB chip.Fpga chip carries out poll to the PA.7 pin of USB chip always, in case detect high level signal, just begins the MAG and the SIGN signal of radio frequency front end chip are passed through string and conversion and buffering, and carries out one-way transmission through USB interface tfi module and USB chip.We make address variables A ddr be " 2 ", just can parallel data be saved in the EP6 end points IN buffer zone of USB chip through FD [15:0].After buffer zone was full, the level of FLAG_FULL pin dragged down, and in PC, notifies the host computer reading of data with data transmission simultaneously.Host computer suspends current thread after the request of receiving the asynchronous I/O that the USB chip is sent, the data in the USB chip are read and are saved in the local hard drive.After the USB chip detection is read to data, make FLAG_FULL that pin is changed to high level, the end points buffer zone of writing that then starts is next time operated.Move in circles like this,, just accomplished the intermediate frequency data collection of one whole when the data total amount that reads reaches the requirement of predesignating.

As shown in Figure 2, the pin interface of multi-mode radio frequency front-end chip and FPGA comprises 6 pins.Wherein, preceding 3 is the pin of spi bus, and remaining 3 is the intermediate frequency data pin.E_CS represents the SCS in the spi bus, and E_CLK is the SCLK in the spi bus, and E_DATA is the bi-directional pin SDA in the spi bus.D0, D1 represent the pin of intermediate frequency data amplitude (MAG) and phase place (SIGN) signal respectively.RF2_CLK is the SF of radio-frequency front-end output, for fpga chip provides system clock.

As shown in Figure 3, fpga chip adopts Cyclone III family chip---the EP3C40Q240C8 of ALTERA company.This device comprises 39600 logical blocks, and total built-in RAM is 1161216 Bits.256 of built-in embedded multipliers, PLL have 4, core voltage 1.2V.PQFP is adopted in encapsulation.Total number of pins has 240, and wherein, maximum available I/O mouth is 120.Concrete pin function is: the RF2_CLK of radio-frequency front-end connects No. 33 pins of fpga chip, and D1, D0 connect pin 37, No. 38, and E_DATA, E_CLK and E_CS connect pin respectively 39,41, No. 43.The FD15 of USB chip, FD14 and FD13 connect

56,55, No. 52, and SLRD connects pin No. 57.All the other pins are pin and the power supply VCC and ground GND of serial FLASH memory.

As shown in Figure 4, the USB chip adopts the famous EZ-USB FX2 of Cypress company family chip---the CY7C68013A of industry.This chip mainly comprises the RAM of USB2.0 transceiver, SIE (SIE), enhancement mode 8051,8.5KB, FlFO storer, I/O, data bus, address bus and 4 the integrated buffer zones of 4K.In the utility model platform, through the configuration to firmware program in the USB chip, external logic can carry out read or write to these end points fifo buffers.Under this pattern, the USB chip with the pin of communicating by letter of fpga chip is:

FIFOADR [1:0] selects address wire for chip terminals, when FIFOADR [1:0] is 00, selects end points 2; When being 10, select end points 6;

FLAGA, FLAGB, FLAGC and FLAGD are empty full zone bit, are used for indicating the full state of sky of the buffer zone of FIFOADR [1:0] indication end points;

SLOE and SLRD be the USB chip the output enable pin with read pin, SLWR is for writing pin, PKEND is the IN packet pin that FPGA enables to force a USB, on behalf of sheet, SLCS select, FD [15:0] is a BDB Bi-directional Data Bus;

SCL, SDA are the EEPROM pin, are used for carrying out the download of firmware program and enumerating.

As shown in Figure 5, be the RTL view of FPGA internal processes.The FPGA control module comprises 4 modules, is respectively string and modular converter, asynchronous FIFO buffer module, USB interface tfi module and total state machine module.The output sampling frequency rate of radio frequency front end chip is 16.368M, and form is SIGN and the MAG signal of 2bit.String and modular converter utilize the shift unit register, transfer serial data the parallel data of 8Bit or 16Bit to, improve system transmissions speed.And also counting has produced the clock of one 8 frequency division, as the clock of writing of asynchronous FIFO module.The buffer depth of asynchronous FIFO module is 8K, and data bit width is 16, and writing clock is 2.046M, and reading clock is 16.368M.The asynchronous FIFO Module Design mainly is continuity and a real-time of having considered the GNSS data acquisition, and this means that also it is continuously effective that writing of asynchronous FIFO enables.Therefore read rate must be greater than writing speed, only in this way could guarantee that data do not lose.The USB interface tfi module mainly accomplish to data in the asynchronous FIFO in the FPGA read and to the function that writes of follow-up USB chip terminals 6 buffer zones.

As shown in Figure 6, be the state transition diagram of the total state machine module of FPGA.It is a most important parts.Not only need carry out poll to the control pin of host computer; Also to consider the read-write requests of asynchronous FIFO buffer module; Also to judge simultaneously the empty full scale will of USB chip terminals buffer zone; After taking all factors into consideration, could arbitrate and control the state transitions in the USB interface tfi module to the read-write of asynchronous FIFO.

As shown in Figure 7, the mode of operation switching of radio-frequency front-end unit is mainly accomplished by the SPI modular program.It comprises 3 pins.Sheet selects SCS, clock pin SCLK and two-way signaling bus SDA.When SCS was low level, the SPI interface was effective.When SCS was high level, the SPI module of radio-frequency front-end did not respond.In read-write sequence, the data of SDA are that the rising edge at the SCLK clock latchs, and the negative edge sampling.Whenever carrying out a read or write, all must send out the control command of 8Bit earlier, is the data of 32Bit then.Just in read operation, SDA need be an input pin by output pin, and reads data on the SDA in FPGA.

As shown in Figure 8, the kit that USB chip firmware program provides based on Cypress company is made amendment and is formed.Have in main: at first, increased by 1 User Defined control transmission function, the PA.7 pin of putting the USB chip is a high level, starts the operation of FPGA with this.Secondly, configuration TD_Init () function makes USB work in asynchronous Slave fifo mode, and the IN end points is EP6, the Bulk transmission, and 512 byte/bags, 4 heavily cushion.The OUT end points is EP2, the Bulk transmission, and 512 byte/bags, 4 heavily cushion.AUTOIN=AUTOOUT=1, the input and output of the automatic process endpoint data of USB chip, word length (WORDWIDE) is that 16 or 8 are optional.The PA.7 pin is the I/O delivery outlet, and FPGA is this pin of poll always.When carrying out data acquisition, end points 6 transfer rates are configured to High-Speed.When carrying out data readback, end points 2 transfer rates are configured to Full-Speed.

As shown in Figure 9, the upper computer software program has been set up 2 threads after initialization.Main thread is responsible for the response of gui interface, and worker thread then is responsible for the collection and the processing of data.2 thread co-ordinations, main detection, the startup of accomplishing USB device (VID/PID)/stop transmission operating.When master routine moves, create USB earlier and connect, obtain USB device handle and end points pointer.Then, wait for that the user clicks " starting transmission " button and starts worker thread.In worker thread, adopt round-robin queue's request, disposable foundation, an initialization N buffer zone, and send N asynchronous transmission requests continuously.Like this, when data are come, can carry out write operation to the data buffer area always and need not the interrupting device transmission.3 functions such as the BeginDataXfer () in the CYAPI.lib library file that concrete transmission realization function employing Cypress company provides, WaitDataXfer ()/FinishDataXfer () are accomplished initiation, wait and the reception operation of asynchronous I/O transmission.After the total data volume that receives reaches the predefined value of user, just withdraw from circulation, and the data of buffer zone are write in the middle of the file of hard disk.Discharge all buffer zones at last, finish a data acquisition.

When carrying out data readback, hardware aspect, need received the SLRD pin clock (CLK) pin of base band; The software aspect need be revised USB firmware program and host computer procedure simultaneously.In the firmware program, the end points that only needs transmission is used changes the EP2 end points into by the EP6 end points, and remainder remains unchanged and gets final product.In the host computer procedure, at first, the data of utilizing documentation function to read to have gathered in the local hard drive, and be put in the buffer zone.Then, change the end points of bulk transfer into the EP2 end points by the EP6 end points, and change the parameter in 3 functions such as BeginDataXfer (), WaitDataXfer ()/FinishDataXfer () into OUT by IN.

Claims

1. the intermediate frequency data collection and the playback reproducer of a GNSS receiver is characterized in that: comprise antenna, be provided with multimode GNSS receiver chip the radio-frequency front-end unit, be provided with SPI program module, string and modular converter, asynchronous FIFO buffer module, USB interface tfi module and total state machine module the FPGA control module, be provided with the USB interface transmission unit and the host computer of firmware program and driver; Antenna connects the radio-frequency front-end unit, the two-way connection radio-frequency front-end of SPI program module unit, and the radio-frequency front-end unit connects FPGA control module, the two-way connection USB interface of FPGA control module transmission unit, the two-way connection host computer of USB interface transmission unit; Intermediate-freuqncy signal is exported through after LNA, mixing and the A/D sample conversion through antenna received RF satellite-signal in the radio-frequency front-end unit, after the FPGA control module is gone here and there to the intermediate-freuqncy signal of radio frequency front end unit output and changed; Become parallel data and be deposited into the asynchronous FIFO buffer module, the USB interface tfi module is written in the USB interface transmission unit after the data in the asynchronous FIFO buffer module are read; The data storage that host computer procedure will read from the USB interface transmission unit is to the hard disk of this locality; During data readback, under the control of host computer procedure, will pass through the data stream of format conversion; Under the triggering of base band clock, be transferred to the middle frequency input terminal of base band.

2. the intermediate frequency data collection and the playback reproducer of GNSS receiver according to claim 1 is characterized in that: during data readback, asynchronously read the CLK pin that pin SLRD is directly connected to the base band clock.