CN201478881U

CN201478881U - Power controller based on SOPC

Info

Publication number: CN201478881U
Application number: CN 200920187550
Authority: CN
Inventors: 段玲琳; 吴剑旗; 段晓超; 黄翌; 谭剑波
Original assignee: CETC 38 Research Institute
Current assignee: CETC 38 Research Institute
Priority date: 2009-09-16
Filing date: 2009-09-16
Publication date: 2010-05-19
Anticipated expiration: 2019-09-16

Abstract

The utility model relates to a power controller based on SOPC, in particular to an embedded power controller suitable for the large-scale power distribution control situation of industrial equipment. The power controller comprises a communication interface circuit, an SOPC circuit, a relay control circuit, a relay fault collection circuit, a sensor signal collection circuit and an FPGA (field programmable gate array) configuration circuit. An FPGA is adopted as a core; and at the inner part of the FPGA, the SOPC technology is used to complete the on-off control of a 48-way power supply, the detection of the current and the voltage of the 48-way power supply in the operating state and the collection of 48 fault points; and Ethernet, UART and SPI protocol interfaces are used to communicate with an upper computer. The power controller overcomes the defects of poor reliability and real-timeliness in the prior art, and has the advantages of simple peripheral circuit, small circuit board area, low power consumption, larger control scale, high reliability and good real-timeliness.

Description

Power-supply controller of electric based on SOPC

Technical field

The utility model relates to a kind of power-supply controller of electric, particularly a kind of power-supply controller of electric that is applicable to the extensive distribution control of industrial equipment occasion.

Background technology

Many times require the complicated distribution of industrial equipment is carried out Long-distance Control at the Industry Control scene, control requires scale big for power supply, and Control Node is many, while reliability height, and real-time is good.Existing power-supply controller of electric is divided into two kinds: a kind of possess multiple communication interface based on high-performance CPU Module Design, can move real time operating system, satisfies the requirement of real-time, but power consumption height, cost height, volume are big, poor reliability; Another kind of SCM Based design, power consumption is little, cost is low, reliability is high, but disposal ability is poor, and task is carried out in proper order, and real-time is poor, and particularly the limited hardware resource can't satisfy the demand of extensive control.Two kinds of power-supply controller of electric all can not satisfy the requirement of extensive power control system, therefore just need a kind of rich hardware resource, reliability height, the design that real-time is good.

The utility model content

The technical problems to be solved in the utility model is to propose a kind of good miniaturized electric source controller of reliability height, real-time that can adapt to the extensive distribution control of industrial equipment occasion.

The technical scheme that the utility model adopted is:

Based on the power-supply controller of electric of SOPC, comprise communication interface circuit, SOPC circuit, relay fault collection circuit, control relay circuit, collecting sensor signal circuit, FPGA configuration circuit, wherein,

The FPGA configuration circuit is connected with the SOPC circuit,

48 road electric currents, 48 road voltage sensors are connected with the SOPC circuit by the collecting sensor signal circuit,

No. 48 relay fault-signal input relay fault collection circuit, the output of relay fault collection circuit is connected with the SOPC circuit,

The control signal of SOPC circuit output connects No. 48 relays by control relay circuit,

The SOPC circuit connects host computer by communication interface circuit.

Described communication interface circuit comprises ethernet interface circuit, RS422 level shifting circuit, RS485 level conversion

The SPI interface circuit of road and RS422 differential level.

Described SOPC circuit is made up of FPGA single-chip EP2C35F672I8.

Described relay fault collection circuit comprises fault initializing circuit and two level chip for driving SN74ALVC164245DGG.

Described control relay circuit comprises FPGA output driving circuit and N-channel MOS FET pipe IRF7380.

Described collecting sensor signal circuit comprises voltage-reference AD780BR, gathers resistance and 6 16 tunnel 12 bits serial A C chip AD7490BRU.

Described FPGA configuration circuit is made up of EPCS64 series arrangement chip and JTAG configuration interface circuit.

Good effect of the present utility model is:

1, this power-supply controller of electric is applicable to extensive power supply control occasion, and realized the closed-loop control to 48 road power supplys on the circuit board of a 150mm * 100mm: the control of No. 48 relay switches, No. 48 relay fault detects, 48 tunnel current sensor signal are gathered and 48 tunnel voltage sensor signals are gathered.

2, SOPC monolithic system-on-chip designs has been reduced power consumption, volume and the hardware cost of controller greatly, based on the design of soft nuclear able to programme make system can cut out, scalable, with FPGA is that carrier has high stability and reliability, and the hardware parallel processing capability of the flexibility of SOPC software design and FPGA sequential logic is integrated as power-supply controller of electric very high handling property and high real-time are provided.

3, communication interface all adopts the differential level transmission, and antijamming capability is strong, is applicable to the complex electromagnetic environment of power supply control.

Description of drawings

Fig. 1 the utility model overall block-diagram,

Fig. 2 communication interface circuit---Ethernet interface principle schematic,

Fig. 3 communication interface circuit---RS422/RS485, SPI interface principle schematic diagram,

Fig. 4 control relay circuit figure,

Fig. 5 relay fault collection circuit diagram,

Fig. 6 collecting sensor signal circuit diagram,

Fig. 7 FPGA configuration circuit figure.

Embodiment

Below in conjunction with drawings and Examples utility model is further specified.

Design philosophy of the present utility model is: processor and interface controller are all realized by the SOPC technology in the FPGA single-chip.The hardware parallel processing capability of the flexibility of SOPC software design and FPGA sequential logic is integrated as power-supply controller of electric very high handling property is provided, the FPGA environmental suitability is strong, the reliability height, volume, the power consumption of single-chip are all very little, but the capacity of super large and plenty hardware resources but can realize very large-scale power supply control.Power-supply controller of electric adopts the differential transfer interface, and antijamming capability is strong, and host computer can be away from power work, safety, convenient.

The general frame of the present utility model as shown in Figure 1.Power-supply controller of electric based on SOPC comprises communication interface circuit 1, SOPC circuit 2, relay fault collection circuit 3, control relay circuit 4, collecting sensor signal circuit 5, FPGA configuration circuit 6, wherein,

FPGA configuration circuit 6 is connected with SOPC circuit 2,

48 road electric currents, 48 road voltage sensors 10 are connected with SOPC circuit 2 by collecting sensor signal circuit 5,

No. 48 relay fault-signals 8 input relay fault collection circuit 3, the output of relay fault collection circuit 3 is connected with SOPC circuit 2,

The control signal of SOPC circuit 2 outputs connects No. 48 relays 9 by control relay circuit 4,

SOPC circuit 2 connects host computer 7 by communication interface circuit 1.

Described communication interface circuit 1 comprises ethernet interface circuit, RS422 level shifting circuit, RS485 level conversion

The SPI interface circuit of circuit and RS422 differential level.

Described SOPC circuit 2 is made up of FPGA single-chip EP2C35F672I8.

Described relay fault collection circuit 3 comprises fault initializing circuit and two level chip for driving SN74ALVC164245DGG.

Described control relay circuit 4 comprises FPGA output driving circuit and N-channel MOS FET pipe IRF7380.

Described collecting sensor signal circuit 5 comprises voltage-reference AD780BR, gathers resistance and 6 16 tunnel 12 bits serial A C chip AD7490BRU.

Described FPGA configuration circuit 6 is made up of EPCS64 series arrangement chip and JTAG configuration interface circuit.

Described SOPC circuit 2 is realized by FPGA single-chip EP2C35F672I8.The closed-loop control that realizes 48 road power supplys has only taken 60% of 672 pipe legs, and the actual macrocell that uses only accounts for 30% of FPGA total capacity, also has very big expansion and upgrading space.The SOPC of design FPGA inside under the QUARTUS of altera corp II environment, Eco-power processor of customization in SOPC Build, RAM on configuration SOPC clock and the sheet; The customization timer; Customize 1 general asynchronous serial port controller UART, utilize the UART nuclear that has the Avalon interface in the soft nuclear of NIOS II for providing serial communication between the embedded system of FPGA and the host computer, the data bit that can change its baud rate, parity check bit, position of rest, transmission can realize that by outside level translator and match circuit RS422/RS485 communicates by letter.The customized network control unit interface is connected on the Avalon bus on chip by the adaptation module in the soft nuclear of NIOSII, to the control of LAN91C111 adaptive net card chip, realizes the Ethernet interface of NIOS II processor; Customize 1 SPI controller, the SPI nuclear that utilizes the Avalon interface that has in the soft nuclear of NIOS II is for providing the synchronous serial communication of four-wire system full duplex between the embedded system of FPGA and the host computer; Customization general purpose I/O interface PIO utilizes the soft mapping of examining existing processor read/write register to peripheral IO port operation of PIO with Avalon interface, finishes reading of relay control, fault collection and sensor values.Disposed after the major function interface of processor, by system tool configuration interface address and interruption, the compiling back generates processor module.This processor module is put into top layer design document BDF, in top document, add PLL phase-locked loop clock frequency multiplication module, the system clock of coupling is provided for processor module, compile together comprehensively with other functional modules then, the downloaded pof file that will generate after compiling successfully downloads in the EPCS64 by jtag interface, has so just finished building of whole SOPC.Operation UC/OS II real time operating system is carried out software design under NIOS IDE environment on SOPC.

The Ethernet interface circuit as shown in Figure 2 in the described communication interface circuit 1.

Among the figure LAN91C111I-NE network card chip D6 integrated follow the MAC (Media layer) and the PHY (physical layer) of SMSC/CD agreement, support the 10/100M full-duplex transmission mode, consult and function such as Flow Control automatically, adopt the isa bus interface, bus signals is divided into three major types: address wire A1 ~ 15, data wire D0 ~ 31, control line RESET, ADS#, LCLK, AEN and BE0# ~ 3# or the like, be connected on the pipe leg of two bank of D1, concrete corresponding relation as shown in Figure 2.In EP2C35F672I8 inside, these pipe legs are assigned on the input and output pipe leg of network controller IP kernel, SOPC utilizes network controller that network card chip is controlled.LAN91C111I-NE adopts the crystal oscillator of 25MHz to be connected on XTAL1 and the XTAL2.The network PHY interface TPO+ of LAN91C111I-NE, TPO-, TPI+, TPI-

connect

8,6,3, the 1 pipe leg of N3 network transformer CL2248X1 respectively.The LEDA# of LAN91C111I-NE is connected the negative terminal that RJ45 socket XS3 goes up Huang, green light-emitting diode respectively with LEDB#.

RS422/485 and SPI are from interface circuit as shown in Figure 3 in the described communication interface circuit 1.

SPI is a Transistor-Transistor Logic level from interface originally, in order to increase the antijamming capability of this interface, adopts the RS422 differential level, and R16, R17, R18, R21 are 120 required Ω build-out resistors of RS422 transmission.When using the SPI interface, in FPGA, the AE12 pin configuration is become high level, the AA12 pin configuration becomes low level, and the V14 pin configuration becomes high level, thereby enables the level conversion function of D2.The outer SPI_CLK+ and SPI_CLK-synchronizing clock signals, SS_N+ and the SS_N-slave unit that are derived from the SPI main equipment of inserting of plate selected signal, MOSI+ and the MOSI-main equipment data to slave unit, and process level translator D2 converts the differential level of RS422 to AE11, AE10 and AF10 pin that the Transistor-Transistor Logic level signal enters D1.The AD10 of D1 is as the holding wire of SPI interface slave unit to main equipment data output MISO, and process level translator D4 converts MISO+ to, the MISO-differential signal is sent outside the plate.In FPGA inside AE11, AE10, AF10 and four pipes of AD10 leg are assigned on the 4 line system interfaces of SPI slave unit controller, utilize SOPC to realize the data communication of SPI interface.

The RS422 interface is the transmitting-receiving full-duplex communication, so in FPGA inside V13, Y12 are configured to high level, V11 is configured to low level, enables the level conversion that whole 4 tunnel of 3,4 two-way of D4 and D3 carries out receiving and transmitting signal.In a single day Tx422_1+, Tx422_1-and Rx422_1+, Rx422_1-are configured to the RS422 transmission means can not be configured to the RS485 mode.

The RS485 interface is the transmitting-receiving half-duplex operation, in process of transmitting, only enable the level conversion of Tx422_1+, Tx422_1-, so only enable 3,4 two-way of D4, is high level in FPGA inside with the V13 pin configuration of D1, this moment, Y12 was configured to low level, V11 is configured to high level, with whole 4 road forbiddings of D3; Only enable Rx422_1+, Rx422_1-and carry out level conversion in receiving course, so 3,4 two-way of D4 are forbidden, enable 4 tunnel of D3, the V13 pin configuration in FPGA inside with D1 is a low level, and Y12 is configured to high level, and V11 is configured to low level.Use the general purpose I/control of O interface V13, Y12, three enable signals of V11 of SOPC.

R20 and R21 are 120 Ω build-out resistors of RS422/485 transmission.The input signal of UART controller is assigned to the AF13 pin of D1 in FPGA inside, output signal is assigned to AE13 pipe leg, utilizes SOPC to realize asynchronous serial data communication.

Control relay circuit 4 is seen accompanying drawing 4, and N-channel MOS FET pipe IRF7380 is withstand voltage to be 80V, and lasting leakage current reaches 3.6A.Drain D end KZ_1 ~ KZ_48 of MOSFET pipe N4 ~ N27 connects the negative terminal of 48 road mains switch relay coils respectively, the needed power level of its adhesive of positive termination of relay coil (for example 28V relay, the positive termination 28V of coil).Conducting trigger end KZ1 ~ KZ48 of N4 ~ N27 is subjected to output Ctrl_1 ~ Ctrl_48 control of FPGA, FPGA output 3.3VTTL signal, by two level chip for driving SN74ALVC164245DGG 3.3V TTL conversion of signals is become 5V TTL signal, for example when Ctrl_1 is the 3.3V high level, through the KZ1 of output 5V after the driving of D12, conducting between the first passage drain D 1 of N4 and the source S 1, KZ_1 ground connection, cause the coil anode of relay to form path, so relay powers up adhesive to negative terminal; When Ctrl_1 is low level, end between the first passage D1 of N1 and the S1, KZ_1 is unsettled, causes the coil negative terminal of relay unsettled, so the relay outage flicks, utilizes this relay control to realize the switch of power supply is controlled.The high-voltage power supply kind that provides relay work required is provided on the power-supply controller of electric, only needs relay coil and power-supply controller of electric to get final product altogether.Power-supply controller of electric is the FPGA loading configuration file in the first few hundred millisecond time that powers on, this moment, the FPGA pin was a high-impedance state, can make the MOSFET pipe in the powered on moment conducting, for fear of this situation, prevent that relay is at this snap action, it is drop-down to add 10K Ω exclusion at Ctrl_1 ~ Ctrl_48 output of FPGA, with Ctrl_1 ~ Ctrl_48 during this period of time drop-down be low level.In FPGA inside the pipe leg of Ctrl_1 ~ Ctrl_48 correspondence is assigned on the universal I interface, SOPC is by writing the control of universal I/O port realization to relay.

Relay fault collection circuit 3 is seen accompanying drawing 5, and the fault indication signal of relay is the Transistor-Transistor Logic level characteristic, and low level is a fault, and high level is normal.Because input signal is the TTL signal of 5V, and FPGA is the 3.3V interface level, so use two-way pair of level driver of SN74ALVC164245DGG to change the bridge of 3.3V signal as the 5V signal here.31,42 pin of SN74ALVC164245DGG meet VCC the A of this chip end are configured to the 5V level, and 7 and 18 pin meet VCC3.3V the B end of this chip is configured to the 3.3V level.1,24 pin of SN74ALVC164245DGG meet VCC3.3V, the driving direction of this chip are configured to by A to B, and 25, the 48 pin ground connection of SN74ALVC164245DGG, this chip enables work all the time.Initialization by the outer input signal BIT1 of plate ~ drop-down realization fault-signal of 48 signals under the situation that does not connect relay, because the effect faulty indication of pull down resistor pulls down to low level, is initialized as fault.48 road fault indication signals insert D1 through chip for driving, in FPGA inside the pipe leg of BIT_1 ~ 48 correspondences is assigned on 3 16 general purpose I/O interfaces of SOPC, SOPC regularly per second reads the fault indication signal of relay by general purpose I/O interface, and the faulty indication that reads reports host computer.

Current/voltage collecting sensor signal circuit is seen accompanying drawing 6, and the sample range of ADC is 0 ~ 5V.Electric current, each 48 tunnel output Iin1 ~ Iin48 of voltage sensor and Vin1 ~ Vin48 are the current signal of 4 ~ 20mA, utilize 96 220 Ω precision resistances the current signal of 96 tunnel 4 ~ 20mA linear change to be transformed into the voltage signal of 1 ~ 4.8V linear change, 16 pin of N28 ~ N32 are as the clock input pipe leg of serial AD, and clock signal is provided by FPGA.19 pin of N28 ~ N32 are as the serial data input of ADC, and content mainly is a channel selecting, is exported by FP6A.15 pin of N28 ~ N32 advance FPGA as the serial data output of ADC, and content is the value of AD conversion.20 pin of N28 ~ N32 are provided by FPGA as the chip selection signal of ADC.6 groups of independently data acquisitions of 6 ADC of sequential logic parallel processing of the inner employing of FPGA.Because the prime that AD gathers does not adopt operational amplifier to do signal condition, so the data after gathering are carried out smoothing processing in the inner mode of filtering that adopts of FPGA, concrete grammar is: SOPC reads the value after the collection, the data degree of depth that every road is gathered is 10 queue processing, rejects minimum and maximum value and gets arithmetic average.

FPGA configuration circuit 6 is seen accompanying drawing 7.The D1 model is EP2C35F672I8 among the figure, the duration of work configuration data is stored in the internal SRAM, but SRAM is a volatile memory, so the program of FPGA configuration file and SOPC need leave among the configuring chip D7, the D7 model is EPCS64, is the flush memory device that 64MB has serial line interface, and volume is little, capacity is big, and cost is low.Serial line interface DATAO, the DCLK of D7, corresponding 4 line N6, N3, E3, the D3 series arrangement interface that connects D1 of ADSO, nCS, the back D1 that powers on reads the configuration file and the program of storing among the D7.XS2 is the DLL (dynamic link library) of series arrangement mode, can directly download programming to D7, XS1 is the JTAG DLL (dynamic link library), and corresponding jtag interface pipe leg M6, M7, L8, the M8 that connects D1 of 1,3,5,9 pin of XS1 can realize the online download programming to D1 and two devices of D7.

The utility model is owing to having used UC/OS II real time operating system, so adopt the software design mode of multithreading.Because power-supply controller of electric is not in case unlatching just allows random stopping using, up to the power-supply controller of electric outage, so the interior mode that adopts circular treatment of each thread.Three threads are created by system once powering on, respectively the collection of control, fault collection and the sensor values of circular treatment relay.Because it is adopt three threads of real time operating system management, so very fast for the response of host computer instruction.The channel selecting of sensor sample, data acquisition, string and conversion be all with the hardware time order logic parallel processing of FPGA, thus little for the required software work amount of the sampling processing of 96 road so many transducers, the system response sensitivity.Software basic procedure: carry out initialization after system powers on, create three threads during initialization, thread 1: order reads the value of No. 96 transducers, and carry out software filtering and handle, report host computer by network interface, asynchronous serial port, three kinds of interfaces of SPI then, judge afterwards whether the value of transducer surpasses the operate as normal value of power supply, if transfinite, produce built-in command control relay power cutoff,, continue to change over to reading state if normal; Thread 2: receive the inside and outside control command, after receiving instruction, if instruction is effectively just according to the command request control relay,, reenter the state of command reception then if invalidly just report host computer instruction ignore by network interface, asynchronous serial port, three kinds of interfaces of SPI.Thread 3: timer second according to the SOPC customization triggers per second collection primary relay fault indication signal, gathers the back packing data, reports host computer by network interface, asynchronous serial port, three kinds of interfaces of SPI.

Claims

1. based on the power-supply controller of electric of SOPC, comprise communication interface circuit (1), SOPC circuit (2), relay fault collection circuit (3), control relay circuit (4), collecting sensor signal circuit (5), FPGA configuration circuit (6), it is characterized in that:

FPGA configuration circuit (6) is connected with SOPC circuit (2),

48 road electric currents, 48 road voltage sensors (10) are connected with SOPC circuit (2) by collecting sensor signal circuit (5),

No. 48 relay fault-signal (8) input relay fault collection circuit (3), the output of relay fault collection circuit (3) is connected with SOPC circuit (2),

The control signal of SOPC circuit (2) output connects No. 48 relays (9) by control relay circuit (4),

SOPC circuit (2) connects host computer (7) by communication interface circuit (1).

2. the power-supply controller of electric based on SOPC as claimed in claim 1 is characterized in that: described communication interface circuit (1) comprises the SPI interface circuit of ethernet interface circuit, RS422 level shifting circuit, RS485 level shifting circuit and RS422 differential level;

Described SOPC circuit (2) is made up of FPGA single-chip EP2C35F672I8;

Described relay fault collection circuit (3) comprises fault initializing circuit and two level chip for driving SN74ALVC164245DGG;

Described control relay circuit (4) comprises FPGA output driving circuit and N-channel MOS FET pipe IRF7380;

Described collecting sensor signal circuit (5) comprises voltage-reference AD780BR, gathers resistance and 6 16 tunnel 12 bits serial A C chip AD7490BRU;

Described FPGA configuration circuit (6) is made up of EPCS64 series arrangement chip and JTAG configuration interface circuit.