CN101666651A - Navigation computer of laser gyro strapdown system - Google Patents

Abstract

The invention provides a navigation computer of a laser gyro strapdown system, consisting of a data collecting module, a navigation calculating module, an interface communication module, an SD card data storing module, a power source circuit and a configuration circuit, wherein the data collecting module, the navigation calculating module, the interface communication module and the SD card data storing module are arranged in an FPGA main chip; the interface communication module comprises a serial port and a USB; and the power source circuit and the configuration circuit are served as assistance. A power source module provides a working power source; output signals of a laser gyro are collected through the data collecting module in the FPGA and are sent to the navigation calculating modulein the FPGA; a navigation calculating program is operated in the navigation calculating module; the calculated navigation information is uploaded to a PC and other external apparatuses through the interface communication module; and the navigation information is stored at real time by the SD card. By using the invention, each function of the navigation computer can be realized on one FPGA so as toimprove the flexibility of the navigation computer, shorten the development period, reduce the number of chips, obviously reduce the volume, the power consumption and the cost of the navigation computer and establish the basis of the miniaturization and the single-chip of the navigation system.

Description

A kind of navigational computer of laser gyro strapdown system

(1) technical field

What the present invention relates to is a kind of device that is used for the control of laser gyro strapdown system.

(2) background technology

Along with the develop rapidly of microelectric technique and the raising of embedded system requirement, the hardware integrated level increases rapidly, rises as SoPC (the System on Programmable Chip) design that physical support carries out chip design with FPGA (Field-Programmable Gate Array).In recent years, use inertia and out of Memory source to realize that the microminiature navigational system of integrated navigation has obtained widespread use, especially obtains tremendous development in fields such as marine navigation and micro air vehicles.The microminiature navigational system is to its nucleus equipment---and navigational computer has proposed higher requirement: when guaranteeing higher arithmetic speed and precision, what the volume of himself, weight, power consumption should be enough is little, to adapt to the needs of miniaturization.

At present, the design focus of navigational computer is processor or the PC/104 industrial computer that adopts personal computer, and volume and power consumption are all undesirable; The double structure method that adopts DSP+MCU (or CPLD) has utilized DSP to be good at computing and characteristics that MCU (or CPLD) is good at control, but the chip that also exists expansion is more, increased the complexity of design and debugging, be difficult to coordinate preferably the coupling undertighten as the DSP of primary processor and the MCU (or CPLD) of control usefulness.Continuous development along with FPGA, the integrated level of FPGA device itself is more and more higher, design resource is also more and more abundanter in the sheet, and the appearance of the FPGA of especially embedded high-performance processor is handled high-speed data and the two-fold advantage of flexible interface control can be integrated in single chip.The development of airmanship impels the performance of navigational system to improve constantly, and cost constantly descends.

Functions such as the required data processing of navigational computer, interface communication, analog acquisition control are integrated in the single chip, and the volume of system and power consumption significantly reduce, and have complied with the harsh requirement of mini system to the space, and the reliability of design improves in the sheet simultaneously; Utilize abundant IP storehouse, in the fpga logic resource, can realize various function peripheral hardwares to the requirement of communication interface and signals collecting function, make navigational computer on the sheet satisfy multi-sensor combined navigation and the configuration of sensor remaining requirement many interfaces according to the integrated navigation application scenario; On SoPC, select high-performance processor for use, and hardware is realized the part algorithm in the fpga logic resource, form the tupe of software-hardware synergism, can realize good real-time performance and higher navigation accuracy.

Use the SoPC method to utilize FPGA to be carrier, the design embedded navigation computer, changed the general layout of the leading navigational computer design of general processor, the Design Mode of its software-hardware synergism and customizability are more appropriate has been fit to the requirement of integrated navigation system to processing power and interface capability, has very strong using value and wide application prospect.

(3) summary of the invention

The object of the present invention is to provide the navigational computer of a kind of laser gyro strapdown system of a kind of miniaturization that can realize navigational system, single chip.

The object of the present invention is achieved like this:

Be by the data acquisition module in the FPGA master chip, navigation calculation module, the interface communication module that comprises serial ports and USB and SD card data memory module, be aided with that power circuit, configuration circuit form; Power module provides working power, the output signal of laser gyro is gathered through the data acquisition module of FPGA inside, deliver to the navigation calculation module of FPGA inside, operation navigation calculation program in the navigation calculation module, navigation information after resolving is uploaded to PC and other peripheral hardwares by the interface communication module, and navigation information sticks into capable real-time storage by SD.

Described power circuit comprises; The input end connection of TPS75733 constitutes input end LC filtering by the second little magnetic bead L2 and the 79 capacitor C the 79, the 80 capacitor C 80, the output terminal of TPS75733 is connected with the LC filtering of the output terminal that is made of the 9th little magnetic bead L9 and the 83 capacitor C the 83, the 84 capacitor C 84, produces the needed 3.3V interface voltage of FPGA; The input end of TPS75725 is connected with by the 3rd little magnetic bead L3 and the 85 capacitor C 85, the input end LC filtering that the 86 capacitor C 86 constitutes, the output terminal of TPS75725 is connected with by the 8th little magnetic bead L8 and the 88 capacitor C 88, the output terminal LC filtering that the 89 capacitor C 89 constitutes, be aided with TPS75718, produce configuration circuit needed 2.5V of chip XCF08P and 1.8V voltage, the input end of TPS75718 is connected with by the 5th little magnetic bead L5 and the 95 capacitor C 95, the input end LC filtering that the 96 capacitor C 96 constitutes, the output terminal of TPS75718 is connected with by the 6th little magnetic bead L6 and the 98 capacitor C 98, the output terminal LC filtering that the 99 capacitor C 99 constitutes; The input end of TPS75701 is connected with by the 4th little magnetic bead L4 and the 90 capacitor C the 90, the 91 capacitor C 91 and constitutes input end LC filtering, the output terminal of TPS75701 is connected with the LC filtering that is made of output terminal the 7th little magnetic bead L7 and the 93 capacitor C the 93, the 94 capacitor C 94, produces the needed 1.2V voltage of FPGA kernel.

Described configuration circuit is: the annexation of configuration circuit is to adopt the form of network label of each pin of configuring chip and FPGA to be connected, and wherein, HSWAP is drop-down by the 4th resistance R 4; DIN links to each other with the D0 pin of PROM; The OE/RESET pin of INIT_B and PROM links to each other; DONE is connected to the CE pin of PROM; PROG_B is connected to the CF pin of PROM; CCLK is by drawing on the 5th resistance R 5; Toggle switch S1 inserts M2, M1, M0 model selection pin by pull-up resistor the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8; TMS, the TCK of main serial connection mouthful P_JTAG and TMS, TCK and the TDO pin that the TDO pin inserts FPGA respectively; The TMS of jtag interface F_JTAG, TCK, TDO, TDI pin insert TMS, TCK, TDO and the TDI pin of FPGA respectively by the 4th current-limiting resistance RS4, the 5th current-limiting resistance RS5, the 6th current-limiting resistance RS6 and the 7th current-limiting resistance RS7; 1.8V power end inserts the first decoupling capacitor C1, the second decoupling capacitor C2 and the 3rd decoupling capacitor C3, the 3.3V power end inserts the 4th decoupling capacitor C4, the 5th decoupling capacitor C5, the 6th decoupling capacitor C6 and the 7th decoupling capacitor C7.

Described data acquisition module is: the output signal of laser gyro is a pulse signal, after treating that signal enters the reversible counting module of FPGA inside, the method that enables by clock produces the reset signal of counter, then the output pulse of gyro is counted, enter FIR digital filtering IP kernel subsequently and carry out digital filtering, with specific frequency filtered signal is sampled at last, the data after will sampling are again delivered to the navigation calculation module and are handled;

Described navigation calculation module is: utilize embedded DSP module of FPGA and PowerPC405 stone, by the APU coprocessor, on the basis of floating-point IP kernel, encapsulate accordingly and cutting, the seamless link of the floating-point operation processor of realization and APU, make up the floating-point arithmetic IP kernel, the data after the sampling enter the module of carrying out a series of navigation operations in the floating-point arithmetic IP kernel; The performing step of concrete navigation operations is: the FPGA that initialization is finished gathers the signal of gyro and accelerometer, initialization quaternary element, carry out the instant correction of the plain Q of quaternary behind speed and the position, just calculate attitude matrix T then, with the value of the acceleration that collects on the carrier coordinate system the acceleration under the navigation coordinate system of being converted to by attitude matrix T, in the period m τ of earth rate and location matrix calculating, integrated acceleration is obtained speed, after compensation is fallen to be harmful to acceleration, calculate position and speed, can resolve then and obtain location matrix C, earth rate and height and gravity acceleration g are asked for the position and the speed of carrier in real time.

Being characterized as of described SD card data memory module: SD card of the present invention is operated under the SPI pattern, FPGA with mainly contain clock line SD_CLK, three single data transmission line SD_DATAIN, SD_DATAOUT, SD_DATAOUT1 and a heel piece route selection SD_CS being connected of SD card, these pins insert the general pin of FPGA respectively, and all pins all are connected to pull-up resistor.

The present invention uses embedded microprocessor stone fpga chip as physical support, by designing reusable IP kernel, make up the hardware platform of laser gyro strapdown system, a series of functions such as data acquisition, navigation calculation and communication interface all realize at single fpga chip inner utilization IP kernel.After system powers on, configuration circuit carries out initialization to FPGA, FPGA begins the output signal of laser gyro is gathered to treat to finish initialization afterwards, the output signal of laser gyro is gathered via the data acquisition module of FPGA inside, deliver to the navigation calculation module with specific frequency, the a series of navigation calculation algorithm of operation in the navigation calculation module, the navigation information that resolves after the processing is uploaded to PC and other peripheral hardwares by the interface communication module, sticks into the real-time storage of line data by SD.

This invention makes every function of navigational computer be able to realize on a slice FPGA, so not only improved the dirigibility of navigational computer, shortened the construction cycle, and reduced core number, make volume, power consumption and the cost of navigational computer significantly reduce, for the miniaturization, the single chip that realize navigational system are laid a good foundation.

(4) description of drawings

Fig. 1 is a structural drawing of the present invention;

Fig. 2 is the configuration circuit synoptic diagram, and wherein Fig. 2 a is that FPGA part, Fig. 2 b of configuration circuit are the configuring chip parts of configuration circuit;

Fig. 3 is the power circuit synoptic diagram;

Fig. 4 is the navigation calculation process flow diagram;

Fig. 5 is a usb circuit;

Fig. 6 is the SD card interface circuit.

(5) embodiment

For example the present invention is done description in more detail below in conjunction with accompanying drawing:

In conjunction with Fig. 1, the navigational computer of laser gyro strapdown system of the present invention is aided with power circuit, configuration circuit, data acquisition module, navigation calculation module, interface communication module (comprising serial ports and USB) and SD card data memory module by the FPGA master chip and forms.Power module provides working power for whole hardware platform, after the system for the treatment of powers on, configuration circuit begins FPGA is configured and initialization, the FPGA initialization begins the output signal of laser gyro is gathered after finishing, the output signal of laser gyro is gathered through the data acquisition module of FPGA inside, deliver to the navigation calculation module of FPGA inside with specific frequency, the a series of navigation calculation algorithm of operation in the navigation calculation module, navigation information after resolving is uploaded to PC and other peripheral hardwares by interface communication module (comprising serial ports and USB), and navigation information sticks into capable real-time storage by SD.

In conjunction with Fig. 3, described power circuit is: the input end of TPS75733 constitutes input end LC filtering by little magnetic bead L2 and C79, C80, voltage output end produces the needed 3.3V interface voltage of FPGA by the LC filtering that little magnetic bead L9 and C83, C84 constitute output terminal; The input end of TPS75725 constitutes input end LC filtering by little magnetic bead L3 and C85, C86, voltage output end constitutes the LC filtering of output terminal by little magnetic bead L8 and C88, C89, be aided with TPS75718, produce needed 2.5V of configuring chip XCF08P and 1.8V voltage; The input end of TPS75701 constitutes input end LC filtering by little magnetic bead L4 and C90, C91, and voltage output end produces the needed 1.2V voltage of FPGA kernel by the LC filtering that little magnetic bead L7 and C93, C94 constitute output terminal;

In conjunction with Fig. 2, described configuration circuit is: the connection of configuration circuit is that the form by the pin network label connects, and HSWAP is drop-down by resistance R 4, keeps stable level to drive at configuration device; DIN links to each other with the D0 pin of PROM, receives the serial data that transmits from the PROM chip; The OE/RESET pin of INIT_B and PROM links to each other, and empties the prom address counter in the configuration incipient stage; DONE is connected to the CE pin of PROM, enables PROM in configuration, closes PROM after configuration is finished; PROG_B is connected to the CF pin of PROM, needs to draw high in layoutprocedure to start flow process; CCLK is by drawing on the R5, and toggle switch S1 inserts M2, M1, M0 model selection pin by pull-up resistor R6, R7, R8; TMS, the TCK of main serial connection mouthful P_JTAG and TMS, TCK and the TDO pin that the TDO pin inserts FPGA respectively; The TMS of jtag interface F_JTAG, TCK, TDO, TDI pin insert TMS, TCK, TDO and the TDI pin of FPGA respectively by current-limiting resistance RS4, RS5, RS6 and RS7; 1.8V power end inserts decoupling capacitor C1, C2 and C3, the 3.3V power end inserts decoupling capacitor C4, C5, C6 and C7;

Described data acquisition module is: the output signal of laser gyro is a pulse signal, after treating that signal enters the reversible counting module of FPGA inside, the method that enables by clock produces the reset signal of counter, then the output pulse of gyro is counted, enter FIR digital filtering IP kernel subsequently and carry out digital filtering, with specific frequency filtered signal is sampled at last, the data after will sampling are again delivered to the navigation calculation module and are handled.

Described navigation calculation module is: utilize embedded DSP module of FPGA and PowerPC405 stone, by the APU coprocessor, on the basis of floating-point IP kernel, encapsulate accordingly and cutting, the seamless link of the floating-point operation processor of realization and APU, make up the floating-point arithmetic IP kernel, the data after the sampling enter carries out a series of navigation operations in the floating-point arithmetic IP kernel.The specific implementation step is: the FPGA that initialization is finished gathers the signal of gyro and accelerometer, initialization quaternary element, carry out the instant correction of the plain Q of quaternary behind speed and the position, just can calculate attitude matrix T (can ask for the attitude of carrier by attitude matrix in real time) then, the conversion by attitude matrix T of the value of the acceleration that collects on the carrier coordinate system can be obtained acceleration under the navigation coordinate system, in the period m τ of earth rate and location matrix calculating, the integration of acceleration can obtain speed, after compensation is fallen to be harmful to acceleration, can calculate position and speed, can resolve then and obtain location matrix C, earth rate and height and gravity acceleration g so just can be asked for the position and the speed of carrier in real time.

In conjunction with Fig. 6, being characterized as of described SD card data memory module: SD card of the present invention is operated under the SPI pattern, FPGA with mainly contain clock line SD_CLK, three single data transmission line SD_DATAIN, SD_DATAOUT, SD_DATAOUT1 and a heel piece route selection SD_CS being connected of SD card, the general pin that these pins insert FPGA respectively gets final product, uncertain in order to prevent that the SD card from pulling out the back level, all pins all are connected to the 10K pull-up resistor of R60-R65.In whole spi bus mode process, the SD_CS chip select line must keep low level; Use the polylith read-write operation that SD is sticked into capable read-write operation, send the command word CMD18 (CMD25) of the piece that reads and writes data during operation to the SD card, after SD snaps fit onto order, to transmit the data of block length from the address that independent variable is set continuously, receive one up to the SD clamping and cease and desist order that (command word is CMD12) SD card just stops read-write.

The present invention is based on the laser gyro strapdown system hardware platform design of SoPC, utilize single fpga chip, design reusable IP kernel, the various piece of navigational system is carried out modularization programming, call the concrete function that IP kernel is realized the various piece of navigational system.FPGA with the embedded processor stone designs navigation computer system on the sheet as physical support, Hardware platform design is core with FPGA, and the data acquisition control of whole navigational system, interface communication, inertial navigation function such as resolve and all realize in that single fpga chip is inner.Fig. 1 is the structural drawing of hardware platform, by the SD card navigation data is carried out high speed storing, and design serial ports and USB2.0 interface are to make things convenient for real-time the communicating with upper PC or other peripheral hardware of navigation computer system.Embodiment is as follows:

1.FPGA master chip and configuration circuit

Hardware platform of the present invention uses the platform class FPGA Virtex-4FX family device of Xilinx as master chip, its has adopted the seamless embedding of IP implanted prosthetics 32 IBM PowerPC405RISC processor cores and Tri-Mode Ethernet MAC.The PowerPC405 of Virtex-4FX device has the APU controller, has made things convenient for the specialized hardware algorithm to realize high bandwidth interface as coprocessor and PowerPC405, and that the present invention selects for use is Virtex-4FX20 FPGA.

Because FPGA is based on the SRAM structure that power down is easily lost, and at first will be configured it after system powers on, and just can possess specific processing power at every turn.FPGA according to selected selects for use XCF08P to dispose Virtex-4FX20.In hardware platform, adopt toggle switch to come S1 to realize freely selecting of configuration mode, adopt main string pattern and jtag boundary scan pattern among the present invention, the configuration circuit of FPGA is seen Fig. 2.Concrete configuration connected mode is as follows: HSWAP is drop-down by 4.7K resistance, keeps stable level to drive at configuration device; DIN links to each other with the D0 pin of PROM, receives the serial data that transmits from the PROM chip; The OE/RESET pin of INIT_B and PROM links to each other, and empties the prom address counter in the configuration incipient stage; DONE is connected to the CE pin of PROM, enables PROM in configuration, closes PROM after configuration is finished; PROG_B is connected to the CF pin of PROM, needs to draw high in layoutprocedure to start flow process; CCLK is by drawing on the R5, and toggle switch S1 inserts M2, M1, M0 model selection pin by pull-up resistor R6, R7, R8; TMS, the TCK of main serial connection mouthful P_JTAG and TMS, TCK and the TDO pin that the TDO pin inserts FPGA respectively; The TMS of jtag interface F_JTAG, TCK, TDO, TDI pin insert TMS, TCK, TDO and the TDI pin of FPGA respectively by current-limiting resistance RS4, RS5, RS6 and RS7; 1.8V power end inserts decoupling capacitor C1, C2 and C3, the 3.3V power end inserts decoupling capacitor C4, C5, C6 and C7.

System powers on or PROGRAM B signal resets can cause that all FPGA reconfigures, if core voltage, reference voltage and I/O voltage are correct, then enters configuration mode.Data are at first passed through the TDI pin of JTAG connector with the speed of TCK, enter the TDI pin of fpga chip.And then from the TDO pin of FPGA configuration data is sent into the TDI pin of PROM chip with same speed, this moment, PROM to the TDO of JTAG connector looping back data, constituted complete JTAG chain by its TDO; Again since the DONE signal of fpga chip be low, INIT_B output level for high, PROM gives FPGA with the speed of CCLK with configuration data by D0.The 3rd, FPGA begins to accept configuration data, and finishes CRC check, if CRC check is passed through DONE signal pin output high level; If the CRC check failure, the DONE signal is low, the layoutprocedure failure, but this moment, FPGA did not provide any prompting, at this moment need add LED with the output cue on the DONE pin.At last, PROM closes the data output pin because the CE pin is input as height, empties address counter, enters dormant state, and configuration finishes.

2. the power circuit of hardware platform

The design requirement of the power circuit of hardware platform is by the decision of the power requirement of fpga chip Virtex-4, PROM chip and components and parts such as storage element device, data acquisition and communication interface circuit.Virtex-4FPGA adopts the power supply of three power supplys, is respectively core power supply VCCINT, auxiliary electric power supply VCCAUX, interface power supply VCCO.Wherein, VCCINT is mainly in the Virtex-4 sheet power supplies such as resource such as stone processor P owerPC405, logical block, XtremeDSP, here select the TPS75701 power supply chip of TI company for use, be aided with the little magnetic bead L4 of a small amount of resistance capacitance and filtering, L7, produce the needed 1.2V voltage of VCCINT; VCCAUX is mainly FPGA configuration mechanism, DCM (digital dock administrative unit) power supply, requires voltage stable, and ripple is less, and the present invention selects for use TPS75725 to be aided with capacitance resistance and little magnetic bead L3, the L8 of a small amount of necessity, forms the 2.5V configuration voltages; VCCO mainly drives the IO interface of FPGA, for the distinct interface level provides for stream and discharge capacity, its electric current demand is relevant with signal upset speed with the interface standard of FPGA pin, therefore selects for use the TPS75733 of TI company to add capacitance resistance and little magnetic bead L2, L9, generates interface voltage 3.3V; Select for use TPS75718 to be aided with a small amount of resistance capacitance and little magnetic bead L5, L6, produce the needed 1.8V operating voltage of PROM chip.The annexation of the power supply circuit of hardware platform is seen Fig. 3.

3. data acquisition module

The original signal of laser gyro strapdown system is from the output of gyroscope and accelerometer, and quantity to be measured is the electric current of laser gyro and accelerometer output in the system, through the A/D conversion, adopts electric current/frequency inverted mode, and current conversion is become the positive negative pulse stuffing sequence.The certain angular velocity or the increment of linear acceleration have just been represented in each pulse like this, and the algebraic sum of positive negative pulse stuffing sequence has been represented the integrated value of measured angle speed or linear acceleration in its unit interval, only need pulse sequence to count and get final product.

Data acquisition controller of the present invention form with IP kernel in FPGA exists, and it comprises interface logic, steering logic, counter module, wave digital lowpass filter etc.Processor core PPC405 begins to carry out data acquisition by OPB bus notification controller, call the collection counting that the counter module that edits carries out data, collection result is fetched by interface logic, and data enter the FIR low-pass filter thereafter, is saved in internal memory by the OPB bus after the filtering high frequency interference.This data acquisition controller utonomous working ability is strong, behind the acquisition of accepting PPC405 and drainage pattern, will independently control with corresponding acquisition rate and passage order, collection and digital filtering.The method that the reversible counting module enables by clock produces the reset signal of counter, then the output pulse of gyro is counted; Carrying out digital filtering at FPGA indoor design FIR IP kernel then gets final product.

4. navigation calculation module

Among the present invention, the navigation calculation module is utilized embedded DSP module of FPGA and PowerPC405 stone, by the APU coprocessor, on the basis of floating-point IP kernel, encapsulate accordingly and cutting, the seamless link of the floating-point operation processor of realization and APU, make up the floating-point arithmetic IP kernel, the data after the sampling enter carries out a series of navigation operations in the floating-point arithmetic IP kernel;

Utilize its inner DSP module and PowerPC405 stone in the present invention,, make up the floating-point arithmetic IP kernel by the APU coprocessor.Provide the floating-point operation device in the IP storehouse of Xilinx, this process will be finished under XPS, but this only is a simple algorithm, does not possess the interface logic that is connected with bus on chip, can not directly link to each other with the APU controller of Vietex4.Therefore, the present invention encapsulates and cutting on the basis of floating-point IP kernel accordingly, realizes and being connected of the floating-point operation processor of APU.The navigation calculation flow process as shown in Figure 4, τ is the instant iteration cycle of revising of the plain Q of quaternary, and m τ is the iteration cycle that earth rate and location matrix calculate, and k τ is the plain normalized iteration cycle of quaternary, n is given navigation calculation number of times, I is the number of times of current navigation calculation, and Vp navigation coordinate system is the speed of carrier down, and T is an attitude matrix, be used to ask for attitude of carrier and realize the conversion of carrier coordinate system to navigation coordinate system, C is a location matrix, is used to obtain the position of carrier, g acceleration of gravity;

The specific implementation step is as follows: the FPGA that initialization is finished gathers the signal of gyro and accelerometer, initialization quaternary element, carry out the instant correction (every iteration k τ just need carry out a normalization to the plain Q of quaternary) of the plain Q of quaternary behind speed and the position (iteration just can obtain these parameters from the value that calculates later for the second time), just can calculate attitude matrix T (can ask for the attitude of carrier by attitude matrix in real time) then, the conversion by attitude matrix T of the value of the acceleration that collects on the carrier coordinate system can be obtained acceleration under the navigation coordinate system, in the period m τ of earth rate and location matrix calculating, the integration of acceleration can obtain speed, after compensation is fallen to be harmful to acceleration, can calculate position and speed, can resolve then and obtain location matrix C, earth rate and height and gravity acceleration g so just can be asked for the position and the speed of carrier in real time.

5. interface communication module

Interface communication of the present invention relates to two kinds of communication modes: serial communication and usb communication:

(1) serial communication modular

Input of navigation sensor information and the navigation results output forms that adopt serial ports so should dispose the serial ports of right quantity more on navigational computer.Native system communicates with three peripherals at least, be respectively PC, GPS and DVL, because the programmable features flexibly of FPGA and the support of design software EDK, the present invention adopt the IP reuse technology to realize enough a plurality of serial ports in the FPGA (Field Programmable Gate Array) in the FPGA sheet.Serial ports IP kernel and processor P owerPC405 coexist in the fpga chip, are connected by bus on chip, provide to extend out the incomparable data bandwidth of serial port chip.With adopt special chip different, realize among the FPGA that the IP kernel of serial port function is designed by hardware description language, so the data layout of each serial ports, whether need the byte degree of depth of FIFO buffering, FIFO to customize according to actual needs.

In the design tool XPS of Xilinx, design standards UART IP kernel (opb_uartlite 1.00.b) disposes a plurality of RS-232 serial ports according to the needs of navigational system, and opb_uartllite is the IP kernel title, and 1.00.b is a version number.This IP kernel is through area and optimization in Properties, taking the interior resource quantity of FPGA sheet only is 88 LUT (look-up table), 44 FF (trigger), baud rate, data bits and parity checking can be set flexibly, finish the data logical protocol of RS-232, with OPB bus compatible, can directly be articulated on the OPB bus based on the Virtex-4 SOC (system on a chip).

(2) usb communication module

In the present invention owing to consider that data quantity transmitted is bigger, and the requirement of speed is arranged,, on the basis of serial communication, designed usb communication again in order better to improve the design of native system.

USB2.0 interface chip of the present invention is selected the EZ-USB FX2 (CY7C6801356 pin SOPP) of CYPRESS company for use.FPGA inside comprises programmed logical module CLB, input/output module IOB able to programme and interconnector able to programme, and abundant trigger resources helps designing complicated sequential logic.FX2 is operated in the Slave fifo mode in the present invention, and peripheral control unit can be read and write the multilayer buffering FIFO of FX2 as common FIFO under this mode, and FX2 can need not the participation of 8051 firmwares with the FPGA direct communication.Data transmission between FX2 chip and the FPGA is mainly by 2 address wire FIFOADR[0:1], 16 data lines USB_FD0-FD15 read that control line USB_SLRD and state index line USB_FLAGA-FLAGD finish; The FX2 pin is connected with the signal of FPGA sees Fig. 5, and SLOE is the output enable signal in the circuit, and when it was low level, data can be exported.FIFOADR[0:1] be address wire, choose the FIFO that inserts data bus.FD0～FD15 is a data line.FLAGC# is a fifo status sign, when its FIFO that inserts data bus during for low level be a sky, and the FIFO non-NULL of access data bus during for high level.SLRD# is a read control signal, and is effective during low level.

6.SD card interface module

For convenience of the separate, stored of guidance system data, the present invention inserts the SD card again on the pin of FPGA, under its work SPI pattern.That the interface circuit in the native system adopts is Virtex-4FX20 FPGA, does not have the SPI pattern, but can realize the data transmission of SPI pattern by software programming: comprise the input and output of serial clock, data, its hardware connects as shown in Figure 6.Under the SPI pattern, realize the data transmission of the SPI pattern of SD card by software programming, FPGA with mainly contain clock line SD_CLK, three single data transmission line SD_DATAIN, SD_DATAOUT, SD_DATAOUT1 and a heel piece route selection SD_CS being connected of SD card, in whole spi bus mode process, the SD_CS chip select line must keep low level

The data of spi bus pattern are that unit transmits with the byte, and every byte is 8.Each order or data block all are byte-aligned (integral multiples of 8 clocks).Main frame is communicated by letter all by host computer control with the various of SD card, main frame all must will drag down the chip selection signal CS of SD card earlier before SD being sticked into any operation of row, send order by main frame to the SD card then, the SD card all will respond any order that main frame sends, and different orders has different response format (1 byte or 2 byte response).The SD card when carrying out write operation, also will respond (sending a special data response sign to main frame) to each data block that main frame sends except to the command response.

The present invention uses fpga chip as physical support, carries out technology on the programmable chip of chip design, i.e. SoPC utilizes the FPGA and the reusable IP kernel of embedded microprocessor stone, makes up the hardware platform of laser gyro strapdown system.A series of functions such as the data acquisition of system, navigation calculation and communication interface all realize at the reusable IP kernel of single fpga chip inner utilization, not only improved the dirigibility of system, shortened the construction cycle, and reduced core number, this invention integrated level height, volume, power consumption and cost significantly reduce, for the miniaturization, the single chip that realize navigational system are laid a good foundation.

Claims (6)

1, a kind of navigational computer of laser gyro strapdown system is by the data acquisition module in the FPGA master chip, navigation calculation module, the interface communication module that comprises serial ports and USB and SD card data memory module, is aided with that power circuit, configuration circuit form; It is characterized in that: power module provides working power, the output signal of laser gyro is gathered through the data acquisition module of FPGA inside, deliver to the navigation calculation module of FPGA inside, operation navigation calculation program in the navigation calculation module, navigation information after resolving is uploaded to PC and other peripheral hardwares by the interface communication module, and navigation information sticks into capable real-time storage by SD.

2, the navigational computer of a kind of laser gyro strapdown system according to claim 1, it is characterized in that: described power circuit comprises: the input end connection of TPS75733 constitutes input end LC filtering by the second little magnetic bead (L2) and the 79 electric capacity (C79), the 80 electric capacity (C80), the output terminal of TPS75733 is connected with the LC filtering of the output terminal that is made of the 9th little magnetic bead (L9) and the 83 electric capacity (C83), the 84 electric capacity (C84), produces the needed 3.3V interface voltage of FPGA; The input end of TPS75725 is connected with by the 3rd little magnetic bead (L3) and the 85 electric capacity (C85), the input end LC filtering that the 86 electric capacity (C86) constitutes, the output terminal of TPS75725 is connected with by the 8th little magnetic bead (L8) and the 88 electric capacity (C88), the output terminal LC filtering that the 89 electric capacity (C89) constitutes, be aided with TPS75718, produce configuration circuit needed 2.5V of chip XCF08P and 1.8V voltage, the input end of TPS75718 is connected with by the 5th little magnetic bead (L5) and the 95 electric capacity (C95), the input end LC filtering that the 96 electric capacity (C96) constitutes, the output terminal of TPS75718 is connected with by the 6th little magnetic bead (L6) and the 98 electric capacity (C98), the output terminal LC filtering that the 99 electric capacity (C99) constitutes; The input end of TPS75701 is connected with by the 4th little magnetic bead (L4) and the 90 electric capacity (C90), the 91 electric capacity (C91) and constitutes input end LC filtering, the output terminal of TPS75701 is connected with the LC filtering that is made of output terminal the 7th little magnetic bead (L7) and the 93 electric capacity (C93), the 94 electric capacity (C94), produces the needed 1.2V voltage of FPGA kernel.

3, the navigational computer of a kind of laser gyro strapdown system according to claim 2 is characterized in that: described configuration circuit is: the connection of configuration circuit is that the form by the pin network label connects, and HSWAP is drop-down by the 4th resistance (R4); DIN links to each other with the D0 pin of PROM; The OE/RESET pin of INIT_B and PROM links to each other; DONE is connected to the CE pin of PROM; PROG_B is connected to the CF pin of PROM; CCLK is by drawing on the 5th resistance (R5), and toggle switch (S1) inserts M2, M1, M0 model selection pin by pull-up resistor the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8); TMS, the TCK of main serial connection mouthful P_JTAG and TMS, TCK and the TDO pin that the TDO pin inserts FPGA respectively; The TMS of jtag interface F_JTAG, TCK, TDO, TDI pin insert TMS, TCK, TDO and the TDI pin of FPGA respectively by the 4th current-limiting resistance (RS4), the 5th current-limiting resistance (RS5), the 6th current-limiting resistance (RS6) and the 7th current-limiting resistance (RS7); 1.8V power end inserts first decoupling capacitor (C1), second decoupling capacitor (C2) and the 3rd decoupling capacitor (C3), the 3.3V power end inserts the 4th decoupling capacitor (C4), the 5th decoupling capacitor (C5), the 6th decoupling capacitor (C6) and the 7th decoupling capacitor (C7).

4, the navigational computer of a kind of laser gyro strapdown system according to claim 3, it is characterized in that: described data acquisition module is: the output signal of laser gyro is a pulse signal, after treating that signal enters the reversible counting module of FPGA inside, the method that enables by clock produces the reset signal of counter, then the output pulse of gyro is counted, enter FIR digital filtering IP kernel subsequently and carry out digital filtering, with specific frequency filtered signal is sampled at last, the data after will sampling are again delivered to the navigation calculation module and are handled;

5, the navigational computer of a kind of laser gyro strapdown system according to claim 4, it is characterized in that: described navigation calculation module is: utilize embedded DSP module of FPGA and PowerPC405 stone, by the APU coprocessor, on the basis of floating-point IP kernel, encapsulate accordingly and cutting, the seamless link of the floating-point operation processor of realization and APU, make up the floating-point arithmetic IP kernel, the data after the sampling enter the module of carrying out a series of navigation operations in the floating-point arithmetic IP kernel; The performing step of concrete navigation operations is: the FPGA that initialization is finished gathers the signal of gyro and accelerometer, initialization quaternary element, carry out the instant correction of the plain Q of quaternary behind speed and the position, just calculate attitude matrix T then, with the value of the acceleration that collects on the carrier coordinate system the acceleration under the navigation coordinate system of being converted to by attitude matrix T, in the period m τ of earth rate and location matrix calculating, integrated acceleration is obtained speed, after compensation is fallen to be harmful to acceleration, calculate position and speed, can resolve then and obtain location matrix C, earth rate and height and gravity acceleration g are asked for the position and the speed of carrier in real time.

6, the navigational computer of a kind of laser gyro strapdown system according to claim 5, it is characterized in that: being characterized as of described SD card data memory module: SD card of the present invention is operated under the SPI pattern, FPGA with mainly contain clock line SD_CLK, three single data transmission line SD_DATAIN, SD_DATAOUT, SD_DATAOUT1 and a heel piece route selection SD_CS being connected of SD card, these pins insert the general pin of FPGA respectively, and all pins all are connected to pull-up resistor.

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