CN116279208A - Data processing subsystem, domain controller and vehicle - Google Patents
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Abstract
The application provides a data processing subsystem, a domain controller and a vehicle, wherein a first processor module comprises a first processor sub-module, and an expansion interface module comprises an expansion interface sub-module, a serializer sub-module and a deserializer sub-module. The expansion interface sub-module is used for receiving the first data sent by the first processor sub-module and sending the first data to the serializer sub-module, and the serializer sub-module is used for driving the corresponding device according to the first data. The expansion interface sub-module is further configured to receive second data sent by the deserializer sub-module, and send the second data to the first processor sub-module, where the first processor sub-module generates a control instruction according to the second data, and the control instruction is used to control a corresponding device. The expansion of the first processor submodule is realized through the expansion interface submodule, so that the problem of insufficient resources of the first processor submodule is solved, more functions are integrated, and various demands of users are met.
Description
Technical Field
The present application relates to the field of vehicles, and more particularly, to a data processing subsystem, a domain controller, and a vehicle.
Background
Along with the evolution of the whole vehicle electronic and electric architecture from the distributed electronic and electric architecture to the domain control central integrated electronic and electric architecture, independent ECUs (Electronic Control Unit, electronic control units) in the cabin are integrated into a cabin domain controller, so that functions and processed data which are required to be realized by the intelligent cabin are more and more complex.
The existing cabin adopts an integrated System On Chip (SOC), and as the CPU (central processing unit ) has limited computing power and the GPU (Graphics Processing Unit, graphics processor) has limited computing power, the integrated functions are less, and the requirements of various man-machine interaction, entertainment experience, living offices and the like are difficult to meet.
Disclosure of Invention
The application provides a data processing subsystem, a domain controller and a vehicle, which are used for integrating more functions and meeting the demands of users.
In a first aspect, the present application provides a data processing subsystem comprising:
the device comprises a first processor module and an expansion interface module, wherein the first processor module comprises a first processor sub-module, and the expansion interface module comprises an expansion interface sub-module, a serializer sub-module and a deserializer sub-module;
the expansion interface sub-module is used for receiving first data sent by the first processor sub-module and sending the first data to the serializer sub-module, and the serializer sub-module is used for driving a corresponding device according to the first data;
the expansion interface sub-module is further configured to receive second data sent by the deserializer sub-module, and send the second data to the first processor sub-module, where the first processor sub-module is configured to generate a control instruction according to the second data, and the control instruction is configured to control a corresponding device.
Optionally, the expansion interface sub-module is configured to receive the video data sent by the first processor sub-module, and send the video data to the serializer sub-module, where the serializer sub-module is configured to drive a target screen according to the video data.
Optionally, the expansion interface submodule is configured to receive camera data sent by the deserializer submodule, and send the camera data to the first processor submodule, where the first processor submodule is configured to generate a control instruction according to the camera data, and the control instruction is configured to control a corresponding device;
the camera data comprises at least one of DMS camera data, OMS camera data, ADCU camera data and side camera data.
Optionally, the expansion interface sub-module sends the video data to the serializer sub-module through a DSI interface, and the expansion interface sub-module receives the camera data sent by the deserializer sub-module through a CSI-2 interface;
the expansion interface module comprises a clock buffer submodule, wherein the clock buffer submodule is used for dividing a received clock signal into multiple paths of clock signals and providing clock signals for the DSI interface and the CSI-2 interface.
Optionally, the first processor module includes:
the system comprises a memory sub-module, a solid hard disk sub-module, a basic input/output sub-module, an IO expansion sub-module and a first temperature sensor sub-module;
the basic input/output submodule is used for storing a bootstrap program, and the solid state disk submodule is used for storing an operating system;
the first processor submodule is used for reading a bootstrap program from the basic input/output submodule, storing the bootstrap program in the memory submodule, reading an operating system from the solid hard disk submodule and storing the operating system in the memory submodule; the first processor sub-module is further used for controlling the serializer sub-module and the deserializer sub-module by controlling the IO expansion sub-module;
the first temperature sensor submodule is used for monitoring the temperature of the memory submodule.
Optionally, the data processing subsystem includes:
the second processor module comprises a second processor sub-module, a video memory sub-module and a second temperature sensor sub-module;
the second processor submodule is used for carrying out 3D rendering of images, image stitching and running target applications;
the video memory submodule is used for storing data corresponding to the second processor submodule;
the second temperature sensor submodule is used for monitoring the temperatures of the second processor submodule and the video memory submodule.
In a second aspect, the present application provides a domain controller comprising the data processing subsystem of the first aspect and any one of the possible designs of the first aspect.
Optionally, the domain controller includes:
the micro control subsystem comprises a first micro control module, a second micro control module, a controller area network module, a local area interconnection network module, a Flexray module, an Ethernet module and a watchdog module;
the first micro control module is used for running an automobile open system; the second micro control module is used for performing enabling control on each module in the domain controller and monitoring the power output state; the controller area network module, the local area internet module, the Flexray module and the Ethernet module are respectively used for communicating with a corresponding electronic control unit; the watchdog module is used for monitoring the running states of the first micro-control module and the second micro-control module.
Optionally, the domain controller includes:
the digital signal processing subsystem comprises a digital signal processing module, an analog-to-digital converter module, an automobile audio bus module, a digital power amplifier module, a radio module and a Bluetooth module;
the digital signal processing module is used for performing first processing on first audio data sent by the analog-to-digital converter module and the automobile audio bus module, sending the first audio data to the first processor submodule, and sending the second processed first audio data to at least one of the automobile audio bus module, the digital power amplifier module, the radio module and the Bluetooth module after receiving the first audio data subjected to second processing by the first processor submodule so as to output the second processed first audio data;
the digital signal processing module is further configured to perform a first process on the second audio data sent by the radio module and the bluetooth module, and send the processed second audio data to at least one of the car audio bus module, the digital power amplifier module, the radio module and the bluetooth module, so as to output the first processed second audio data.
Optionally, the domain controller includes:
the peripheral subsystem comprises a serial deserializer module, a Bluetooth Wifi module, a universal serial bus module and an inertial measurement module, wherein the serial deserializer module comprises a second serializer sub-module and a second deserializer sub-module;
the second serializer submodule is used for receiving video data sent by the first processor submodule and the second processor submodule so as to drive a corresponding screen; the second deserializer submodule is used for receiving camera data and sending the camera data to the expansion interface module submodule; the Bluetooth Wifi module is used for realizing Bluetooth function and WiFi function; the universal serial bus module is used for providing a communication interface; the inertial measurement module is used for inertial navigation.
In a third aspect, the present application provides a vehicle comprising the second aspect and the domain controller in any one of the possible designs of the second aspect.
The data processing subsystem comprises a first processor module and an expansion interface module, wherein the first processor module comprises a first processor sub-module, and the expansion interface module comprises an expansion interface module sub-module, a serializer sub-module and a deserializer sub-module. The expansion interface submodule is used for receiving first data sent by the first processor submodule and sending the first data to the serializer submodule, and the serializer submodule is used for driving a corresponding device according to the first data so as to realize more functions. The expansion interface sub-module is further configured to receive second data sent by the deserializer sub-module, send the second data to the first processor sub-module, and generate a control instruction according to the second data by the first processor sub-module, where the control instruction is used to control a corresponding device. The expansion of the first processor submodule is realized through the expansion interface submodule, so that the problem of insufficient resources of the first processor submodule is solved, more functions are integrated, and various demands of users are met.
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For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a data processing subsystem according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a domain controller according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
As described in the background art, the existing cabin adopts an integrated SOC, and because the CPU computing power and the GPU computing power are limited, the integrated functions are less, and the requirements of various man-machine interactions, entertainment experiences, living offices and the like are difficult to meet. In order to make up the problem of insufficient resources of the APU submodule, the FPGA submodule is adopted to realize CRC calculation of the functional safety icons and expansion of interfaces of the APU submodule, the data processing subsystem comprises an APU module and an FPGA module, the APU module comprises an APU submodule, and the FPFA module comprises an FPGA submodule, a sequencer submodule and a Deserializer submodule. The FPGA submodule is used for receiving the first data sent by the APU submodule and sending the first data to the sequencer submodule, and the sequencer submodule is used for driving a corresponding device according to the first data. The FPGA sub-module is also used for receiving second data sent by the Deserializer sub-module and sending the second data to the APU sub-module, the APU sub-module is used for generating a control instruction according to the second data, and the control instruction is used for controlling a corresponding device.
The technical scheme of the present application is described in detail below with specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
FIG. 1 is a schematic diagram of a data processing subsystem according to an embodiment of the present application. The data processing subsystem provided by the embodiment of the application comprises:
a first processor (Accelerated Processing Unit, APU) module and an expansion interface (Field Programmable Gate Array, FPGA) module;
the first processor module comprises a first processor sub-module, and the expansion interface module comprises an expansion interface sub-module, a Serializer (Serializer) sub-module and a Deserializer (Deserializer) sub-module;
the expansion interface submodule is used for receiving the first data sent by the first processor submodule and sending the first data to the serializer submodule, and the serializer submodule is used for driving a corresponding device according to the first data;
the expansion interface sub-module is further configured to receive second data sent by the deserializer sub-module, and send the second data to the first processor sub-module, where the first processor sub-module is configured to generate a control instruction according to the second data, where the control instruction is configured to control a corresponding device.
For ease of description, the first processor module is referred to as an APU module, the expansion interface module is referred to as an FPGA module, the first processor sub-module is referred to as an APU sub-module, the expansion interface sub-module is referred to as an FPGA sub-module, the Serializer sub-module is referred to as a Serializer sub-module, and the Deserializer sub-module is referred to as a Deserializer sub-module.
The APU submodule has strong calculation power and rich high-speed buses and low-speed interfaces, is a brain of the whole digital processing subsystem, is internally provided with a CPU and a GPU, the calculation power of the CPU can reach 384KDMIPS (Dhrystone Million Instructions executed Per Second), and the calculation power of the GPU can reach 1.4T flow (flowing-point operations per second). The APU sub-module may further include high-speed interfaces such as a 4-way DP1.4 interface, an 18-way PCIE Gen3 interface, a 2-way SGMII interface, a 4-way USB3.2 Gen2 interface, a 4-way USB2.0 interface, a 4-way LPDDR4X, and low-speed interface resources such as a 2-way TDM interface, a 5-way I2C interface, a 1-way SPI interface, a 2-way UART interface, and GPIOs.
In some embodiments, the APU sub-module is a SOC chip, within which the CPU and GPU are integrated.
In some embodiments, the GPU built into the APU sub-module is a vehicle-mounted chip.
In some embodiments, the GPU built in the APU sub-module is iGPU (integrated GPU), which enables image processing in low-computational-force scenarios.
In some embodiments, in order to implement the rear seat screen RSD and head up display screen HUD functions, the APU sub-module may send video data to the FPGA sub-module, which receives the video data sent by the APU sub-module and sends the video data to the sequencer sub-module, which drives the target screen according to the video data. For example, the APU submodule may send video data to the FPGA submodule through the 4lane pcie3.0 bus, and the FPGA submodule may send video data to the sequencer submodule through the 2-way DSI interface, where after the sequencer submodule receives the data, one way drives the rear seat screen through the FPD LINK4 interface, and one way drives the head-up display screen through the FPD LINK3 interface.
In some embodiments, the FPGA sub-module is an FPGA chip.
In some embodiments, the deseriaizer sub-module can receive at least one of the following camera data: DMS data transmitted by a DMS camera, OMS camera data transmitted by an OMS camera, ADCU camera data transmitted by an ADCU camera, and side camera data transmitted by a side camera. After receiving the camera data, the Deserializer sub-module sends the camera data to the APU sub-module, and the APU sub-module generates a control instruction according to the camera data, wherein the control instruction is used for controlling a corresponding device.
For example, in order to implement the in-cabin sensing function of DMS (Drive Monitoring System, driver monitoring system)/OMS (Occupancy Monitoring System, passenger monitoring system), the deperiaizer submodule receives camera data transmitted from a DMS camera, an OMS camera, etc., the FPGA submodule receives the camera data transmitted by the deperiaizer submodule, generates a control instruction according to the camera data, and the control instruction is used for controlling a corresponding device. For example, the deseriaizer sub-module receives camera data transmitted from the DMS camera, the OMS camera and the like through the GMSL2 interface and transmits the camera data to the FPGA sub-module through the 1-path CIS-2 interface, and the FPGA sub-module transmits the camera data to the APU sub-module through the PCIE3.0 bus for analysis and processing, for example, the camera data includes feature data (drowsiness feature, yawning feature and the like) corresponding to fatigue driving, and the APU sub-module can control the alarm device to send an alarm according to a control instruction generated by the camera data.
For example, in order to realize the functions of automatic driving and automatic parking, the deperiarizer submodule receives ADCU camera data sent by an ADCU (Automated Driving Control Unit, automatic driving domain controller) camera and side camera data sent by a side camera, and the FPGA submodule receives the camera data sent by the deperiarizer submodule, generates a control instruction according to the camera data, and the control instruction is used for controlling a corresponding device. For example, the deseriaizer sub-module receives, through a GMSL3 interface, ADCU camera data sent by an ADCU camera, and side camera data sent by a side camera, and then sends the received ADCU camera data and the side camera data to the FPGA sub-module through a 1-path CSI-2 interface, and the FPGA sub-module sends the received ADCU camera data and the side camera data to the APU sub-module through a PCIE3.0 bus to analyze and process, for example, when the camera data includes vehicle or pedestrian information in a target range, a control instruction generated by the APU sub-module is used for controlling vehicle deceleration or braking and the like.
Optionally, the FPGA sub-module further has a multi-path I2C, SPI, UART bus interface, where the I2C bus is mainly used to configure registers of the sequencer sub-module and the deserializing sub-module so as to implement corresponding control and status reading thereof; the SPI bus is mainly used for communicating with the MCU 1; UART flow control of the Bluetooth module is realized through a UART bus of the FPGA sub-module.
For example, the FPGA module may include a clock buffer sub-module for dividing a one-way clock signal into multiple-way clock signals. For example, the FPGA submodule sends video data to the serialiser submodule through a 2-way DSI interface, the FPGA submodule receives DMS camera data/OMS camera data sent by the Deserializer submodule through a 1-way CIS-2 interface, the FPGA submodule receives ADCU camera data/side camera data sent by the Deserializer submodule through a 1-way CIS-2 interface, and the clock buffer submodule mainly divides one 200MHz clock into 4 ways and is used for providing local clocks for the DSI interface and the CSI-2 interface so as to ensure normal communication.
In some embodiments, the APU module may include an APU sub-module, a memory sub-module, an SSD (Solid State Disk) sub-module, a BIOS (Basic Input/Output System) sub-module, an IO expansion sub-module, and a first temperature sensor sub-module. The BIOS sub-module is used for storing a BOOT program, the SSD sub-module is used for storing an operating system, the APU sub-module is used for reading the BOOT program from the BIOS sub-module, storing the BOOT program in the memory sub-module, and reading the operating system from the SSD sub-module, and storing the operating system in the memory sub-module, so that the CPU can execute the BOOT program in the memory sub-module to complete initialization of each memory and start the operating system in the memory sub-module. The APU sub-module is further used for controlling the sequencer sub-module and the deseriaizer sub-module through controlling the IO expansion sub-module, so that the sequencer sub-module can control a corresponding device, and the deseriaizer sub-module can receive corresponding camera data. The first temperature sensor submodule is used for monitoring the temperature of the memory submodule and preventing the occurrence of system halt or blue screen phenomenon.
Specifically, the APU sub-module reads the BOOT program from the BIOS sub-module through the SPI bus, and stores the BOOT program in the memory sub-module, so that the CPU can execute the BOOT program in the memory sub-module, to complete initialization of each memory. And then the APU submodule carries the operating system from the SSD submodule to the memory submodule through the PCIE bus, so that the CPU can execute initialization of other peripheral devices (interfaces, keyboards and the like) and start the operating system to finish starting operation. The IO expansion self-interface is used as the expansion of an APU submodule GPIO (General-purpose input/output), the APU submodule controls the IO expansion submodule to be used as the expansion of the APU submodule GPIO through an I2C bus, and controls the IO expansion submodule through the I2C bus so as to realize the control of the seriizer and the Deserializer module.
In some embodiments, the data processing subsystem further comprises: and the second processor (GPU) module comprises a second processor sub-module, a video memory sub-module and a second temperature sensor sub-module. For ease of description, the second processor module is referred to as a GPU module and the second processor sub-module is referred to as a GPU sub-module. The CPU submodule is used for carrying out 3D rendering of graphics, image splicing and running target application, neural network learning, artificial intelligence providing calculation force and the like, the video memory submodule is used for storing data corresponding to the GPU submodule, the second temperature sensor is used for monitoring the temperatures of the CPU submodule and the video memory submodule, and the situation that performance is reduced due to overheat of the GPU submodule and the video memory submodule is prevented.
In some embodiments, the GPU sub-module is an image processing chip.
In some embodiments, the GPU sub-module is a dGPU (discrete/dedicated GPU) that enables image processing alone or in combination with an APU in a high computational force scene.
In some embodiments, the GPU submodule is a consumer image processing chip with a computational effort of 8.7 tflips.
In some embodiments, the GPU submodule integrates 28 computing units, the computing power is up to 8.7T maps, and the GPU submodule can be used for performing 3D rendering of images, splicing images, running large-scale 3D games and other applications, and interacts with the APU submodule through an 8-way PCIE3.0 bus to achieve high-speed communication. The display memory submodule adopts 4 GDDR6 display memories with 32bit width, each pin rate reaches 14Gbps, the total bandwidth reaches 224GB/s, and the total capacity reaches 8GB, so as to store the rendering data processed or to be extracted by the GPU submodule.
According to the data processing subsystem, the expansion of the APU sub-module is realized through the FPGA sub-module, the problem of insufficient resources of the APU sub-module is solved, more functions are integrated, and various requirements of users are met.
Fig. 2 shows a schematic structural diagram of a domain controller according to an embodiment of the present application. The domain controller system provided by the embodiment of the application comprises the data processing subsystem.
In some embodiments, the domain controller includes a micro control (Multi Control Unit, MCU) subsystem including a first micro control module, a second micro control module, a controller area network (Controller Area Network, CAN) module, a local interconnect network (Local Interconnect Network, LIN) module, a Flexray module, an ethernet module, and a watchdog module.
For convenience of description, the micro control subsystem is referred to as an MCU subsystem, the first micro control module is referred to as an MCU1 module, the second micro control module is referred to as an MCU2 module, the controller area network module is referred to as a CAN module, and the local interconnect network module is referred to as a LIN module.
The MCU1 module is used for running an automobile development system (AUTOSAR) to communicate with other ECUs of the whole automobile through buses such as CAN, LIN, flexray and Ethernet and realize system power management; in addition, the MCU1 module is also respectively communicated with the MCU2 module, the Ethernet module, the DSP module and the FPGA sub-module through SPI interfaces; the communication is carried out with an APU submodule through a switch in the Ethernet module through an RGMII interface; the control and the reading of the states of the radio module, the digital power amplifier module, the analog MIC module, the digital MIC module and the RTC module are realized through the I2C interface.
The MCU2 module is used for performing enabling control on each module in the domain controller so as to control the working state of each module to realize normal starting of the system and sleep policy management, for example, to control each module to be in a working state or a disconnection state. The MCU2 module is also used for monitoring the power output state so as to control the power supply of the whole system.
The CAN module, the LIN module, the Flexray module and the Ethernet module are respectively used for communicating with the corresponding ECU. For example, the CAN module mainly realizes communication with other ECUs of the whole vehicle and is used as a wake-up source of the system. The LIN module is mainly used for realizing communication with other ECUs of the whole vehicle. The Flexray module mainly realizes communication with other ECUs of the whole vehicle and is used as a wake-up source of the system. The Ethernet module internally comprises 2 PHY sub-modules and an Ethernet SWITCH sub-module. The PHY submodule is mainly used for realizing the communication with other ECUs of the whole vehicle and the bus upgrading function; the Ethernet SWITCH submodule is mainly used for realizing data distribution, specifically, the Ethernet SWITCH submodule is communicated with the PHY submodule through a 2-path RGMII interface, is communicated with the MCU1 submodule through a 1-path RMII interface, is communicated with the APU through a 1-path SGMII interface, and specific data exchange rules are set by the MCU1 through an SPI bus.
The watchdog module is used for monitoring the running states of the MCU1 module and the MCU2 module, and resetting the MCU1 and the MCU2 after monitoring that the MCU1 module and the MCU2 module are abnormal, for example, resetting the MCU1 module after monitoring that the MCU1 module is abnormal, and resetting the MCU2 module after monitoring that the MCU2 module is abnormal.
In some embodiments, the domain controller further comprises a digital signal processing (Digital Signal Processing, DSP) subsystem comprising a digital signal processing module, an Analog-to-Digital Converter (ADC) module, an automotive audio bus (A2B) module, a digital power amplifier module, a radio module, and a bluetooth module.
For the purposes of this description, the digital signal processing subsystem is referred to as the DSP subsystem, the analog-to-digital converter module is referred to as the ADC module, and the car audio bus module is referred to as the A2B module.
The DSP module is used as an audio processor of the domain controller and is used for carrying out first processing on first audio data sent by the ADC module and the A2B module and then sending the first audio data to the APU sub-module, the APU sub-module carries out second processing on the first video data and sends the second processed first audio data to the DSP module, and after receiving the first audio data which is subjected to the second processing by the APU sub-module, the DSP module sends the second processed first audio data to at least one of the A2B module, the digital power amplifier module, the radio module and the Bluetooth module, so that the first audio data which is processed by the DSP module and the APU sub-module is output through the A2B module, the digital power amplifier module, the radio module and/or the Bluetooth module. For example, the first audio data input by the ADC module and the A2B module are processed by the DSP module and then sent to the APU sub-module through the TDM interface, and the APU sub-module further processes the first audio data to fuse the multimedia data, and then sends the first audio data to the DSP module through the TMD interface, and then sends the first audio data to the digital power amplifier module, the A2B module, the bluetooth module, and so on.
The second audio data transmitted from the radio module and the Bluetooth module are processed by the DSP module and then directly output to the A2B module, the digital power amplifier module and the like, so that the DSP module is also used for performing first processing on the second audio data transmitted from the radio module and the Bluetooth module and then transmitting the second audio data to at least one of the A2B module, the digital power amplifier module, the radio module and the Bluetooth module so as to output the first processed second audio data.
The ADC module is used for collecting 4 paths of analog MIC signals and sending the signals to the DSP module through the TDM interface so that the DSP module processes the analog MIC signals collected by the ADC module. The A2B module is used for collecting audio data transmitted from the remote slave node through the A2B bus and transmitting the audio data to the DSP module for processing through the TDM interface or outputting the audio data processed by the DSP module to the remote slave node. The digital power amplifier module is used for receiving the digital audio data processed by the DSP module through the I2S interface, converting the digital audio data into analog signals, amplifying the analog signals and outputting the analog signals through the loudspeaker. The radio module is used for receiving audio data through AM and FM antennas and sending the audio data to the DSP module for processing through the I2S interface.
In some embodiments, the domain controller includes a peripheral subsystem including a serial Deserializer (Serdes) module, a bluetooth Wifi module, a universal serial bus (Universal Serial Bus, USB) module, and an inertial measurement module (Inertial Measurement Unit), the serial Deserializer module including a second Serializer sub-module and a second Deserializer sub-module.
For ease of description, the serial Deserializer module is referred to as the Serdes module, the universal serial bus module is referred to as the USB module, the inertial measurement module is referred to as the IMU module, the second Serializer sub-module is referred to as the Serializer2 sub-module, and the second Deserializer sub-module is referred to as the Deseriizer 2 sub-module.
The sequencer 2 submodule is used for receiving video data sent by the APU submodule and the GPU submodule so as to drive a corresponding screen. For example, the serializer submodule mainly receives video data transmitted from the APU submodule and the GPU submodule through the DP1.4 interface, and drives the CSD screen, the PSD screen, the DIS screen and the RSD1 screen through the FPD LINK4 interface, and the APU submodule and the GPU submodule have strong calculation power, so that the four screens can be linked simultaneously.
The Deserializer2 submodule is used for receiving camera data and sending the camera data to the FPGA submodule. For example, the video data transmitted by the camera is received and then transmitted to the FPGA submodule through the CSI-2 interface, and then transmitted to the APU submodule for processing.
The Bluetooth Wifi module is used for realizing the Bluetooth function and the WiFi function, and the Bluetooth WIFI module is integrated on the same module, so that the Bluetooth and the WIFI function can be realized simultaneously. The USB module is used for providing a communication interface, for example, the USB module comprises a path of USB3.2 Gen2 interface and a path of USB2.0 interface, and the APU submodule is used for communicating with an external USB3.2 BOX through the USB3.2 Gen2 interface to realize a USB3.2 HUB function; the APU submodule is communicated with an external USB2.0 BOX through one USB2.0 interface to realize a USB2.0 HUB function, and the APU submodule is communicated with the other USB2.0 interface to realize a digital audio broadcasting DAB function. The IMU module is used for inertial navigation, and the APU submodule can realize control and state reading of the IMU module through the I2C interface.
The domain controller provided by the application comprises a data processing subsystem, wherein the data processing subsystem comprises an FPGA (field programmable gate array) sub-module, and the expansion of the APU sub-module is realized through the FPGA sub-module, so that the problem of insufficient resources of the APU sub-module is solved, more functions are integrated, and various demands of users are met.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. Such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (11)
1. A data processing subsystem, comprising:
the device comprises a first processor module and an expansion interface module, wherein the first processor module comprises a first processor sub-module, and the expansion interface module comprises an expansion interface sub-module, a serializer sub-module and a deserializer sub-module;
the expansion interface sub-module is used for receiving first data sent by the first processor sub-module and sending the first data to the serializer sub-module, and the serializer sub-module is used for driving a corresponding device according to the first data;
the expansion interface sub-module is further configured to receive second data sent by the deserializer sub-module, and send the second data to the first processor sub-module, where the first processor sub-module is configured to generate a control instruction according to the second data, and the control instruction is configured to control a corresponding device.
2. The system of claim 1, wherein the expansion interface sub-module is configured to receive video data sent by the first processor sub-module and send the video data to the serializer sub-module, and wherein the serializer sub-module is configured to drive a target screen according to the video data.
3. The system of claim 2, wherein the expansion interface sub-module is configured to receive camera data sent by the deserializer sub-module and send the camera data to the first processor sub-module, and the first processor sub-module is configured to generate a control instruction according to the camera data, where the control instruction is configured to control a corresponding device;
the camera data comprises at least one of DMS camera data, OMS camera data, ADCU camera data and side camera data.
4. The system of claim 3, wherein the expansion interface sub-module sends video data to the serializer sub-module via a DSI interface, and wherein the expansion interface sub-module receives camera data sent by the deserializer sub-module via a CSI-2 interface;
the expansion interface module comprises a clock buffer submodule, wherein the clock buffer submodule is used for dividing a received clock signal into multiple paths of clock signals and providing clock signals for the DSI interface and the CSI-2 interface.
5. The system of claim 1, wherein the first processor module comprises:
the system comprises a memory sub-module, a solid hard disk sub-module, a basic input/output sub-module, an IO expansion sub-module and a first temperature sensor sub-module;
the basic input/output submodule is used for storing a bootstrap program, and the solid state disk submodule is used for storing an operating system;
the first processor submodule is used for reading a bootstrap program from the basic input/output submodule, storing the bootstrap program in the memory submodule, reading an operating system from the solid hard disk submodule and storing the operating system in the memory submodule; the first processor sub-module is further used for controlling the serializer sub-module and the deserializer sub-module by controlling the IO expansion sub-module;
the first temperature sensor submodule is used for monitoring the temperature of the memory submodule.
6. The system of any one of claims 1-5, wherein the data processing subsystem comprises:
the second processor module comprises a second processor sub-module, a video memory sub-module and a second temperature sensor sub-module;
the second processor submodule is used for carrying out 3D rendering of images, image stitching and running target applications;
the video memory submodule is used for storing data corresponding to the second processor submodule;
the second temperature sensor submodule is used for monitoring the temperatures of the second processor submodule and the video memory submodule.
7. A domain controller comprising the data processing subsystem of any of claims 1-6.
8. The domain controller of claim 7, wherein the domain controller comprises:
the micro control subsystem comprises a first micro control module, a second micro control module, a controller area network module, a local area interconnection network module, a Flexray module, an Ethernet module and a watchdog module;
the first micro control module is used for running an automobile open system; the second micro control module is used for performing enabling control on each module in the domain controller and monitoring the power output state; the controller area network module, the local area internet module, the Flexray module and the Ethernet module are respectively used for communicating with a corresponding electronic control unit; the watchdog module is used for monitoring the running states of the first micro-control module and the second micro-control module.
9. The domain controller of claim 8, wherein the domain controller comprises:
the digital signal processing subsystem comprises a digital signal processing module, an analog-to-digital converter module, an automobile audio bus module, a digital power amplifier module, a radio module and a Bluetooth module;
the digital signal processing module is used for performing first processing on first audio data sent by the analog-to-digital converter module and the automobile audio bus module, sending the first audio data to the first processor submodule, and sending the second processed first audio data to at least one of the automobile audio bus module, the digital power amplifier module, the radio module and the Bluetooth module after receiving the first audio data subjected to second processing by the first processor submodule so as to output the second processed first audio data;
the digital signal processing module is further configured to perform a first process on the second audio data sent by the radio module and the bluetooth module, and send the processed second audio data to at least one of the car audio bus module, the digital power amplifier module, the radio module and the bluetooth module, so as to output the first processed second audio data.
10. The domain controller of claim 9, wherein the domain controller comprises:
the peripheral subsystem comprises a serial deserializer module, a Bluetooth Wifi module, a universal serial bus module and an inertial measurement module, wherein the serial deserializer module comprises a second serializer sub-module and a second deserializer sub-module;
the second serializer submodule is used for receiving video data sent by the first processor submodule and the second processor submodule so as to drive a corresponding screen; the second deserializer submodule is used for receiving the camera data and sending the camera data to the expansion interface submodule; the Bluetooth Wifi module is used for realizing Bluetooth function and WiFi function; the universal serial bus module is used for providing a communication interface; the inertial measurement module is used for inertial navigation.
11. A vehicle comprising a domain controller according to any one of claims 7-10.
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