CN109931932A - A kind of high-precise synchronization integrated navigation computer - Google Patents
A kind of high-precise synchronization integrated navigation computer Download PDFInfo
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Abstract
A kind of high-precise synchronization integrated navigation computer, including FPGA board, dsp processor drive crystal oscillator, and the driving crystal oscillator provides unified clock for dsp processor and FPGA board, to guarantee the synchronization of each chip.It realizes to resolve navigation data in such a way that two CSTR processor is combined with FPGA board and separates independent operating with on-line correction filtering, improve the frequency of navigation calculation, reliability is greatly improved with precision；Unified sampling clock is provided to gyro, accelerometer using FPGA board, completes the synchronous acquisition of gyro data and acceleration information, can guarantee the real-time of navigation；Using unified external data interface, need to only change interface board can be realized to the acquisition of distinct interface data, avoided the circuit interface of change navigational computer, increased the versatility of integrated navigation computer and reduce design cost.
Description
Technical field
The present invention relates to integrated navigation computer field, especially a kind of high-precise synchronization integrated navigation computer.
Background technique
Integrated navigation technology be will include that Strapdown Inertial Navigation System (SINS), GPS, celestial navigation system (CNS) etc. are a variety of leads
Boat technology is integrated, and realizes and has complementary advantages, improves navigation accuracy to a greater extent.Integrated navigation technology is in space flight and aviation, force
The fields such as device guidance, vehicle mounted guidance, ship navigation are widely used.
For integrated navigation technology compared with single airmanship, performance advantage is obvious, but data volume to be treated is significantly
Increase, each navigation subsystem it is synchronous require it is also higher and higher, thus to acquiring, handle and control for navigation data
The structure of integrated navigation computer and performance requirement are higher.Navigational computer basic function is each sensing data of acquisition, is completed
Compensation data and navigation calculation, and navigation results are exported, it is completed at the same time the interaction with external control command.Traditional navigation meter
Calculation machine is designed in the form of single dsp processor+FPGA circuitry type structure, data of the dsp processor as whole system
Processing and resolve part, major function includes the output filtering and temperature-compensating of gyro signal, add table signal output filter and
Temperature-compensating, navigational parameter resolve, on-line correction filters and navigation data exports etc.；Pair of the FPGA board as whole system
Outer data input and output interfaces, major function includes gyro data acquisition, accelerometer data acquires, external sensor data is adopted
The synchronization of collection and each sensing data, while receiving external control command.But since the calculation amount of on-line correction filtering is larger, flower
The time taken is more, the frequency decline for causing navigational parameter to resolve, so the navigation operations rate of this structure is slower, navigation accuracy
It is poor.Currently, integrated navigation system mostly uses greatly two CSTR processor structure, document " lead by embedded based on two CSTR processor
Navigate computer distributed system design, Chinese inertial technology journal, the 1st phase of volume 2008,16 " propose will navigation calculate with it is online
Filter task is completed in different dsp processors, effectively raises system accuracy, but is not considered gyro data and accelerated
It spends the synchronization counted and does not consider the data phase mutual feedback between dsp processor, eventually precision is had an impact；Document
" two CSTR processor communication research in the integrated navigation system based on optical fibre gyro, Modern Scientific Instruments, the 2011, the 6th phase " mentions
The communication between two dsp processors is realized using McASP bus out, but is the absence of a master controller and two DSP are handled
Effective management of device and resource allocation.
Summary of the invention
The purpose of the invention is to overcome the above-mentioned shortcoming of the prior art, and provide a kind of with high navigation calculation
Frequency is able to carry out the high-precise synchronization integrated navigation calculating that real-time synchronization data acquire and have external universal data interface
Machine.
For achieving the above object, the technical scheme is that
A kind of high-precise synchronization integrated navigation computer, including FPGA board, dsp processor drive crystal oscillator, the driving
Crystal oscillator provides unified clock for dsp processor and FPGA board, to guarantee the synchronization of each chip；
The dsp processor, including two panels dsp processor, a piece of navigation acquired for analyzing processing by FPGA board
Parameter calculation, another filters for on-line correction, and respectively exports the result of operation to FPGA board；
The FPGA board is used to provide clock pulses for external gyro and accelerometer, and completes gyro data and add
The synchronous acquisition that speed counts, and realize the acquisition to navigation data, then by packed data with parallel bus
Mode is transferred to specified dsp processor, and by the fructufy of dsp processor operation when feeds back to another dsp processor, into
Row data correction is realized that navigation is calculated and is completed in different dsp processors from on-line correction filter task, mentions most possibly
High navigation accuracy.
Further embodiment is: the FPGA board is used uniformly the bus interface of parallel transmission to external interface,
It include the second pulse signal line of data line, control line, address wire, p-wire, differential clock line and GPS system, and also
Equipped with interface conversion plate, the bus interface on interface conversion plate is corresponding with FPGA board external interface also using same total
Line definition, the bus transfer rate is adjustable, is controlled by FPGA board.
Further embodiment is: further including that gyroscope, accelerometer, GPS system equipment connect on the interface conversion plate
Mouthful.
Further embodiment is: further including RS422, RS232, ARINC429 expansion interface on the interface conversion plate.
Further embodiment is: the differential clock line connects for FPGA board and gyroscope and accelerometer
It connects, with clock between unification, guarantees the synchronization of acquisition data.
Further embodiment is: the DPS processor respectively connects flash storage, for extending DPS processor
Internal reservoir prevents data degradation to realize the storage and transfer of mass data, improves the navigation stability and navigation of computer
Precision.
The present invention is since using the above structure, advantage is compared with prior art:
(1) present invention realizes in such a way that two CSTR processor is combined with FPGA board resolves and online school navigation data
Positive filter separates independent operating, improves the frequency of navigation calculation, reliability is greatly improved with precision；
(2) present invention provides unified sampling clock to gyro, accelerometer using FPGA board, complete gyro data with
The synchronous acquisition of acceleration information can guarantee the real-time of navigation；
(3) present invention employs unified external data interfaces, and only need to change interface board can realize to distinct interface data
Acquisition avoids the circuit interface of change navigational computer, increases the versatility of integrated navigation computer and reduce design
Cost.
Detailed description of the invention
Fig. 1 is overall logic structural schematic diagram of the invention；
Fig. 2 is electrical block diagram of the invention；
Fig. 3 is that specific line and function division are illustrated between dsp processor and FPGA board in Fig. 2；
Fig. 4 is FPGA board external interface schematic diagram in Fig. 2.
Specific embodiment
The present invention is described in further details below with reference to Figure of description:
As shown in Figure 1, a kind of high-precise synchronization integrated navigation computer, is mainly deposited by FPGA board, dsp processor, Flash
Reservoir, driving crystal oscillator and relevant interface composition, two dsp processors pass through internal bus interface and FPGA board phase respectively
Even, and possess respective storage flash storage, external sensing data is written by external interface, by FPGA board
Management after distribute to the processing operation that corresponding dsp processor carries out data, a piece of dsp processor is responsible for navigational parameter solution
It calculates, another dsp processor is then responsible for on-line correction filtering, and dsp processor exports the result of operation to FPGA board,
FPGA board can according to operation result carry out Navigation Control and by respective operation result feed back to another dsp processor into
The amendment of row navigational parameter can be in an on-line correction filtering since to resolve the time spent shorter for navigational parameter
Navigation calculation is repeatedly completed, since the frequency of navigation calculation is faster, result precision is higher, and navigational computer entire in this way is led
Boat precision just correspondinglys increase.
Fig. 2 gives integrated navigation computer and external sense circuit is illustrated, and is divided into three major parts: including combination
Navigational computer circuit, interface conversion plate and external sense circuit, integrated navigation computer include two TI company models
For TMS320C6727B-350 dsp processor and its extension storage model SST39VF3202 flash storage, one
The FPGA board and driving crystal oscillator that SPARTAN serial model No. is XC6SLX16-3FTG256I, dsp processor and FPGA electricity
It is connected between the plate of road by control line, data line and address wire, respective function is as follows:
1 function of dsp processor: gyro and accelerometer data, temperature-compensating, calibrating parameters compensation, navigation calculation are read；
2 function of dsp processor: GPS and external sensor data are read, reads 1 calculation result of dsp processor, combined filter；
FPGA board function: navigational parameter data are packaged and is allocated, is read external sensor data, external interface is provided
With clock, output Navigation Control parameter.
Due to FPGA board external interface be used uniformly parallel transmission bus interface (including 16 be data line, 6 ground
Location line, 6 control lines, read-write clock line), advantage is no matter carry how many external sensor are without change navigational computer
Circuit can increase the versatility of navigational computer and reduce the I/O port use to FPGA board in navigational computer.
Design needs special interface conversion plate to realize the compatibility to external different sensors interface, therefore interface in this way
It include that one group of FPGA board parallel transmission bus interface, three groups of gyro interfaces, three groups of accelerometers connect in conversion plate interface
Mouth, one group of GPS sensor interface and other expansion interfaces etc..
Interface conversion plate provides various navigational parameters for integrated navigation computer, wraps in currently used integrated navigation system
Containing gyro, accelerometer and GPS system, be also possible to that star sensor can be added as needed, thus be additionally provided with RS422,
RS232, ARINC429 bus expansion interface, these sensing datas can enter the FPGA of interface conversion plate by respective interface
Circuit board, and in FPGA board complete data packing, then by parallel transmission bus be written navigational computer.
In addition navigational computer unified read-write clock can be provided to external sensor come guarantee data due to no matter outer
How many sensing data of portion is all by between the FPGA board in the FPGA board and navigational computer in conversion circuit
Bus come complete data transmission, so the read or write speed of the bus be generally located on 100Mbps can meet data transmission
Requirement.
In the present invention between dsp processor and FPGA board specific line and function division as shown in figure 3, being divided into 6
A part: the configuration of FPGA board and dsp processor is respectively byPart and theIt is partially completed, mainly matches including program
It sets and is configured with clock；TheMainly FPGA board provided to dsp processor and flash storage data, control with
Address interface, for carrying out the transmission and control of data；TheAs long as being transmitted between part dsp processor and FPGA board
The design of bus interface；ThePart is dsp processor internal data processing unit；ThePart is then flash storage
Data file interface design.
The input of external all sensing datas, the output for reading and writing clock, the output of Navigation Control are all parallel by one group
Output bus interface is completed, and the design of specific external interface is as shown in figure 4, be divided into FPGA board configuration module and outer
Portion's interface two parts.FPGA board configuration is similar with the configuration in Fig. 3, and mainly completion program and clock configures；It is external
Interface defines one group of parallel bus interface connecting with interface conversion plate, comprising:
6 bit address lines (DH_A (5:0)): address input is provided for external interface；
6 control lines (DH_C (5:0)): being mainly responsible for Read-write Catrol and state controls；
16 position datawires (DH_D (15:0)): for external sense data provide parallel input provide with navigation control data it is defeated parallel
Out；
4 bit test lines (DH_T (3:0)): for the test of FPGA board function, can also be used to carry out control and clock line
Extension；
One group of gyro differential clock line (FOG_CLK+, FOG_CLK-): work clock is provided for gyro data；
One group of accelerometer differential clock line (ACC_CLK+, ACC_CLK-): work clock is provided for accelerometer, when with gyro
Clock is synchronous；
A piece GPS second pulse signal (GPS_PPS): predominantly GPS system provides a synchronization pulse.
When carrying out Interface Controller, the FPGA board in integrated navigation computer belongs to master controller, main FPGA circuitry
Plate can initiate reading instruction and clock control according to the service requirement of navigational computer, at this time when there is data needs in interface conversion plate
When transmission, the read signal state value in control line can be updated immediately, and main FPGA board just will do it read operation at this time, same main
FPGA board will enable the write signal in control line when needing to write data, and complete in the ready situation of translation interface
The write operation of data.
The above is only the preferred embodiment of the present invention, protection scope of the present invention is not limited merely to above-described embodiment,
All technical solutions belonged under thinking of the present invention all belong to the scope of protection of the present invention.It should be pointed out that for the art
For those of ordinary skill, several improvements and modifications without departing from the principles of the present invention should be regarded as protection of the invention
Range.
Claims (9)
1. a kind of high-precise synchronization integrated navigation computer, it is characterized in that including FPGA board, dsp processor drives crystal oscillator,
The dsp processor, including two panels dsp processor, a piece of navigational parameter acquired for analyzing processing by FPGA board
It resolves, another filters for on-line correction, and respectively export the result of operation to FPGA board；The driving crystal oscillator
Unified clock is provided for dsp processor and FPGA board, to guarantee the synchronization of each chip；The FPGA board
Clock pulses is provided for external gyro and accelerometer, and completes the synchronous acquisition of gyro data and accelerometer data, with
And acquisition of the realization to navigation data, then packed data are transferred to specified DSP in a manner of parallel bus and handled
Device, and by the fructufy of dsp processor operation when feeds back to another dsp processor, carries out data correction.
2. a kind of high-precise synchronization integrated navigation computer as described in claim 1, it is characterized in that the FPGA board
The bus interface of parallel transmission is used uniformly to external interface, when including data line, control line, address wire, p-wire, difference
The second pulse signal line of clock line and GPS system, and it is additionally provided with interface conversion circuit board, the bus on interface conversion circuit board
Interface is corresponding with FPGA board external interface also to use same bus definition, and the bus transfer rate is adjustable, by FPGA
Circuit board control.
3. a kind of high-precise synchronization integrated navigation computer as claimed in claim 2, it is characterized in that the interface conversion electricity
It further include gyroscope, accelerometer, GPS system equipment interface on the plate of road.
4. a kind of high-precise synchronization integrated navigation computer as claimed in claim 2 or claim 3, it is characterized in that the interface conversion
It further include RS422, RS232, ARINC429 expansion interface on circuit board.
5. a kind of high-precise synchronization integrated navigation computer as claimed in claim 2 or claim 3, it is characterized in that the differential clocks
Line is connect for FPGA board with gyroscope and accelerometer, with clock between unification, guarantees the synchronization of acquisition data.
6. a kind of high-precise synchronization integrated navigation computer as claimed in claim 4, it is characterized in that the differential clock line
It is connect for FPGA board with gyroscope and accelerometer, with clock between unification, guarantees the synchronization of acquisition data.
7. a kind of high-precise synchronization integrated navigation computer as described in 1,2,3,6 any one of claim, it is characterized in that institute
The DPS processor stated respectively connects flash storage, for extending the internal reservoir of DPS processor.
8. a kind of high-precise synchronization integrated navigation computer as claimed in claim 4, it is characterized in that the DPS processor is each
From connection flash storage, for extending the internal reservoir of DPS processor.
9. a kind of high-precise synchronization integrated navigation computer as claimed in claim 5, it is characterized in that the DPS processor is each
From connection flash storage, for extending the internal reservoir of DPS processor.
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Cited By (9)
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| CN110532689A (en) * | 2019-08-29 | 2019-12-03 | 贵州航天控制技术有限公司 | A kind of miniature Φ 36mm howitzer central processing circuit system |
| CN110849361A (en) * | 2019-11-28 | 2020-02-28 | 湖南率为控制科技有限公司 | Light and small integrated optical fiber inertial navigation system for unmanned driving |
| CN111865125A (en) * | 2020-07-29 | 2020-10-30 | 中车青岛四方车辆研究所有限公司 | Traction inverter control system and PWM modulation method |
| CN112925393A (en) * | 2021-03-11 | 2021-06-08 | 深圳市天辰防务通信技术有限公司 | Positioning and orienting controller |
| CN113253639A (en) * | 2021-04-22 | 2021-08-13 | 深圳市天辰防务通信技术有限公司 | Navigation processor |
| CN113483756A (en) * | 2021-07-13 | 2021-10-08 | 北京信息科技大学 | Data processing method and system, storage medium and electronic equipment |
| CN114485726A (en) * | 2021-12-23 | 2022-05-13 | 北京无线电测量研究所 | Inertial navigation pulse output sampler manufacturing method and system |
| CN115373925A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Comprehensive test method, system and storage medium for heterogeneous integrated microsystem |
| CN117553786A (en) * | 2024-01-04 | 2024-02-13 | 深圳市天辰防务通信技术有限公司 | Navigation device |
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| CN110532689A (en) * | 2019-08-29 | 2019-12-03 | 贵州航天控制技术有限公司 | A kind of miniature Φ 36mm howitzer central processing circuit system |
| CN110849361A (en) * | 2019-11-28 | 2020-02-28 | 湖南率为控制科技有限公司 | Light and small integrated optical fiber inertial navigation system for unmanned driving |
| CN110849361B (en) * | 2019-11-28 | 2022-02-15 | 湖南率为控制科技有限公司 | Light and small integrated optical fiber inertial navigation system for unmanned driving |
| CN111865125A (en) * | 2020-07-29 | 2020-10-30 | 中车青岛四方车辆研究所有限公司 | Traction inverter control system and PWM modulation method |
| CN111865125B (en) * | 2020-07-29 | 2021-07-20 | 中车青岛四方车辆研究所有限公司 | Traction inverter control system and PWM modulation method |
| CN112925393A (en) * | 2021-03-11 | 2021-06-08 | 深圳市天辰防务通信技术有限公司 | Positioning and orienting controller |
| CN113253639A (en) * | 2021-04-22 | 2021-08-13 | 深圳市天辰防务通信技术有限公司 | Navigation processor |
| CN113483756A (en) * | 2021-07-13 | 2021-10-08 | 北京信息科技大学 | Data processing method and system, storage medium and electronic equipment |
| CN114485726A (en) * | 2021-12-23 | 2022-05-13 | 北京无线电测量研究所 | Inertial navigation pulse output sampler manufacturing method and system |
| CN115373925A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Comprehensive test method, system and storage medium for heterogeneous integrated microsystem |
| CN117553786A (en) * | 2024-01-04 | 2024-02-13 | 深圳市天辰防务通信技术有限公司 | Navigation device |
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Application publication date: 20190625 |