CN115373925A - Comprehensive test method, system and storage medium for heterogeneous integrated microsystem - Google Patents
Comprehensive test method, system and storage medium for heterogeneous integrated microsystem Download PDFInfo
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Abstract
The invention discloses a comprehensive test method, a system and a storage medium of a heterogeneous integrated micro-system, wherein a minimum system external interface USB or PXI is used for developing high-level application layer software, the unified scheduling of the high-level application layer software is used for realizing the comprehensive test flow of the micro-system, the method can cover the channel test, the short circuit test, the high-speed synchronization, the self-test and the like among TSV multi-chips in the micro-system, the unified final test result can be stored in a storage chip of a double FPGA, the test data of the internal chip of the micro-system can be conveniently checked and analyzed through the visual presentation of the high-level application layer software, and the problems of interconnection of pins among heterogeneous interconnection chips and the test bottleneck of read-write time sequence at present are effectively solved.
Description
Technical Field
The invention belongs to the technical field of chip testing, relates to a heterogeneous integrated multi-chip interconnection and intercommunication testing method and a multi-chip interconnection read-write time index testing method, and particularly relates to a heterogeneous integrated micro-system comprehensive testing method, a heterogeneous integrated micro-system comprehensive testing system and a storage medium.
Background
The conventional two-dimensional chip adopts an on-chip DFT method which is commonly adopted at present, and the on-chip DFT method comprises the following steps: boundary scan, built-in self test BIST, and scan test.
For a multi-chip microsystem (such as a TSV) with heterogeneous integration, new open-circuit and short-circuit faults are caused due to failure modes such as metal fracture or insulation layer holes of the TSV and related vias. In addition, the micro system chip has no test access port for interconnection and no port for communication with the outside, so that the test of interconnection and intercommunication between chips is difficult. At present, for a multi-chip interconnection micro-system, a traditional ATE test can only be performed through an external interface of the micro-system after bonding, and the test coverage rate of interconnection among chips cannot be ensured. However, the current common JTAG programmer performs chip test through JTAG, so that other interface pins cannot be directly controlled and observed.
Due to the connection between the interconnected chips, the black box is invisible to the outside, so that the comprehensive test between the chips of the product becomes useless, and the yield of the product in the fault mode cannot be determined.
Disclosure of Invention
In order to solve the technical problems that the traditional ATE test cannot ensure the test coverage rate of interconnection among chips, and other interface pins cannot be directly controlled and directly observed through JTAG test, the invention provides a comprehensive test method, a system and a storage medium of a heterogeneous integrated micro-system, which can effectively solve the problems of interconnection and intercommunication of pins among heterogeneous interconnected chips and the test bottleneck of pin read-write time sequence. The system-level high-speed synchronization of the microsystem product can be further realized, a uniform scheduling algorithm is provided for the test of the microsystem product, the test and debugging modes in the interconnected chips can be started through the JTAG, the system-level uniform test strategy of the microsystem product is realized, and the comprehensive test of the multi-chip interconnection facing the heterogeneous integration process becomes very simple.
In order to achieve the above purpose, the invention adopts the following technical contents:
a comprehensive test method for a heterogeneous integrated microsystem comprises the following steps:
s1, building a minimum test system based on double FPGAs and developing application layer software according to the minimum test system;
s2, unifying a test algorithm and a test strategy of the minimum test system through the mutual matching of the application layer software and the FPGA embedded software of the S1;
s3, testing the heterogeneous integrated micro system to be tested to obtain a comprehensive test result;
s4, storing the data of the comprehensive test result obtained in the S3, transmitting the data back to application layer software for data analysis, and outputting an analysis result;
and S5, observing the internal fault of the heterogeneous integrated micro-system to be tested according to the analysis result of the S4.
Preferably, a USB or PXI interface is reserved when the minimum test system is built in S1.
Preferably, the FPGA of S1 is loaded with a memory chip and reserves a JTAG interface.
Preferably, the testing of the heterogeneous integrated microsystem under test in S3 is based on the JTAG1149 protocol or the JTAG1500 protocol.
Preferably, the heterogeneous integrated micro-system to be tested in S3 is composed of dual SoC chips.
Preferably, the heterogeneous integrated microsystem to be tested in S3 is implemented based on a TSV process.
Preferably, the test process of the heterogeneous integrated micro system to be tested includes a method for synchronizing the interconnection chips in the heterogeneous integrated micro system to be tested at a high speed, and the method specifically includes the following steps:
s301, configuring an FPGA homologous clock;
s302, controlling an input/output mode of an interconnection chip in the heterogeneous integrated micro-system through the FPGA and respectively collecting an input clock and an output clock;
s303, comparing the input clock and the output clock acquired in the S302 with the homologous clock of the S301 to obtain the clock difference between the input mode and the output mode of the interconnection chip in the heterogeneous integrated micro system;
and S304, according to the clock difference of the S303, carrying out high-speed synchronization on the interconnected chips in the heterogeneous integrated micro-system.
Preferably, the format of the parsing result in S4 is an image or text.
An integrated test system for heterogeneous integrated microsystems, comprising:
a development module: the system is used for developing application layer software according to a minimum test system;
a debugging module: the test algorithm and the test strategy for unifying the minimum test system are adopted;
the test module is used for testing the heterogeneous integrated micro system to be tested and outputting a comprehensive test result;
the storage module is used for storing the comprehensive test result;
and the analysis module is used for analyzing the comprehensive test result in the storage module and observing the internal design fault of the heterogeneous integrated micro-system product through the analysis result.
A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method of integrated testing of heterogeneous integrated microsystems.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a comprehensive test method of a heterogeneous integrated micro-system, which is characterized in that a minimum test system is built through double FPGAs, and a test and debugging mode in a chip is started based on the minimum test system.
In addition, the invention provides a unified test strategy and a test algorithm by developing application layer software; realizing high-speed synchronization of the interconnected chips by means of a homologous clock; the comprehensive test method of the interconnection chips with more than two layers and stacked multilayer chips, and the comprehensive test method of the multi-chip interconnection of the heterogeneous integration process, namely the comprehensive test method of the heterogeneous integration microsystem provide a basis for the deep research of the technology in the field, develop a portable test tool capable of replacing an ATE test tool, and provide a novel portable, economic and universal method for the chip test.
Furthermore, when the minimum test system is built, an external interface, namely a USB or PXI interface is reserved, so that the development of high-level application layer software is facilitated.
Furthermore, when the minimum test system is built, the FPGA is provided with a storage chip and a JTAG interface is reserved, the test result can be stored in the storage chip carried by the FPGA, and the JTAG can be used for controlling the double chips in the micro-system, so that the multi-mode switching can be realized, the switching can be switched into a test mode and a debugging mode, and the integrated tests such as independent test of each chip, interconnection and intercommunication test among the chips and the like can be realized.
Furthermore, the invention utilizes the JTAG of the FPGA to control the double chips of the microsystem to be tested, respectively carries out read-write operation, establishes time sequence contrast analysis according to the respective read-write of the input clock and the double chips, obtains the difference value of the read-write time sequence between the interconnected chips and can realize the high-speed time synchronization of the interconnected chips.
Furthermore, the invention displays the analysis result in the form of image or text, which can more clearly help the tester and user identify the fault of heterogeneous integrated micro system.
The invention also provides a comprehensive test system of the heterogeneous integrated micro-system, which can complete the comprehensive test flow of the system-level heterogeneous integrated micro-system through the cooperative cooperation of the development module, the debugging module, the test module, the storage module and the analysis module, and can realize various tests such as path test, short circuit test, high-speed synchronization, self-test and the like among the multiple chips in the heterogeneous integrated micro-system.
The invention also provides a computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the steps of the comprehensive test method of the heterogeneous integrated microsystem, so as to complete the test of interconnection and intercommunication among the multiple chips.
Drawings
FIG. 1 is a schematic structural diagram of a minimum test system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of interconnection testing and control of interconnection chips according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a unified scheduling algorithm and scheduling policy control of a microsystem according to an embodiment of the present invention;
FIG. 4 is a high-speed synchronous control diagram of the interconnect chip according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of a comprehensive test flow provided by an embodiment of the present invention;
FIG. 6 is a schematic block diagram of a minimal test system provided by an embodiment of the present invention;
FIG. 7 is a timing diagram of the source clock according to an embodiment of the present invention;
FIG. 8 is a write timing diagram provided by an embodiment of the present invention;
fig. 9 is a read timing diagram provided in an embodiment of the invention;
FIG. 10 is a timing diagram according to an embodiment of the present invention;
FIG. 11 is a flowchart illustrating a comprehensive test of a heterogeneous integrated microsystem according to the present invention;
FIG. 12 is a schematic diagram of a heterogeneous integrated microsystem according to the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects of the present invention more apparent, the following embodiments further describe the present invention in detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 11, the present invention provides a comprehensive testing method for heterogeneous integrated micro-systems, which comprises the following steps:
s1, building a minimum test system based on double FPGAs and developing application layer software according to the minimum test system;
when a minimum test system is built, a USB or PXI interface is reserved, and the FPGA carries a storage chip and reserves a JTAG interface.
And S2, unifying the test algorithm and the test strategy of the minimum test system through the mutual matching of the application layer software and the FPGA embedded software of the S1.
S3, testing the heterogeneous integrated micro system to be tested to obtain a comprehensive test result; the heterogeneous integrated micro system to be tested is realized based on a TSV (through silicon via) process and consists of double SoC (system on chip) chips.
The method comprises a high-speed synchronization method of interconnected chips in the heterogeneous integrated micro-system to be tested, and comprises the following specific steps:
s301, configuring an FPGA homologous clock;
s302, controlling an input/output mode of the interconnection chip through the FPGA;
s303, comparing with the homologous clock of S301 to obtain the clock difference between the input and the output of the interconnected chip;
and S304, completing the high-speed synchronization of the interconnected chips according to the clock difference of the S303.
And S4, storing the comprehensive test result obtained in the S3, transmitting the comprehensive test result back to application layer software for data analysis, outputting an analysis result, and displaying the analysis result in an image or text format.
And S5, observing the internal fault of the heterogeneous integrated micro-system to be tested through the analysis result of the S4.
The comprehensive test method of the heterogeneous integrated microsystem is based on the JTAG1149 protocol or the 1500 protocol. As shown in fig. 12, the present invention further provides a comprehensive test system for heterogeneous integrated micro-systems, comprising: the development module is used for developing application layer software according to the minimum test system; the debugging module is used for unifying a test algorithm and a test strategy of the minimum test system; the test module is used for testing the heterogeneous integrated micro system to be tested and outputting a comprehensive test result; the storage module is used for storing the comprehensive test result; and the analysis module is used for analyzing the test result in the storage module and observing the internal design fault of the heterogeneous integrated microsystem product through the analysis result.
The comprehensive test method and the system of the heterogeneous integrated micro-system provided by the invention can be used for developing application layer software (high-level application layer software) through a minimum system external interface USB or PXI, can realize the comprehensive test flow of the system-level micro-system through the unified scheduling of the high-level application layer software, can cover the channel test, short-circuit test, high-speed synchronization, self-test and the like among TSV multiple chips in the micro-system, can store the unified final test result in a storage chip of a double FPGA (field programmable gate array), can be used for conveniently checking and analyzing the test data of chips in the micro-system through the visual presentation of the high-level application layer software, and effectively solves the problems of interconnection and intercommunication of pins among heterogeneous interconnected chips and the test bottleneck of pin read-write time sequence at present.
The invention also provides a computer readable storage medium, the computer readable storage medium stores a computer program, and the steps of the comprehensive test method of the heterogeneous integrated microsystem can be realized by executing the computer program through the processor, so that the test of interconnection and intercommunication among the multiple chips is completed.
The computer-readable storage medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, etc.
It should be noted that the computer readable storage medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable storage media that does not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
Examples
Detailed description of the drawings:
as shown in fig. 1, the minimum test system architecture is specifically configured to: and a USB or PXI interface is adopted, and a minimum test system is built by using double FPGAs. The FPGA can be respectively carried with a storage chip to store a test result, and can also be externally connected with a computer readable storage medium to realize the storage and backup of the test result, a JTAG interface is reserved when a minimum test system is built, and the JTAG can be used for controlling double chips in the heterogeneous integrated micro-system, thereby realizing the multi-mode switching and carrying out the comprehensive test.
Based on the minimum test system, a test and debugging mode in the chip is started, a unified test strategy and scheduling algorithm are realized, the double chips of the heterogeneous integrated microsystem are independently controlled through the JTAG generator of the double FPGAs and can be switched into the test mode and the debugging mode, independent test of each chip and interconnection and intercommunication test among the chips are realized, and a test result can be stored in a storage chip carried by the FPGA.
The test mode and the debugging mode are switching modes of JTAG to the boundary scan self-test of the chip. Generally, the independent test of chips is performed in a test mode, i.e. a conventional boundary scan test, and the interconnection test between chips is performed based on the test mode of the chips. In addition, when the test is not performed, the function test of the heterogeneous integrated system can be performed in a debugging mode.
As shown in fig. 2, the inter-chip interconnection and intercommunication test specifically includes: the JTAG of the FPGA is used for controlling the SoC, so that the pin connectivity of a single SoC can be tested respectively, and two FPGAs can be used for controlling the respective SoC to test the interconnection interoperability between two interconnected SoCs. By the method, whether open circuit or short circuit faults exist in the connection of the TSV heterogeneous integrated microsystem structure among the interconnected chips can be tested, and specific fault pins can be located. Furthermore, the redundant design of the fault can be carried out according to the fault location, and the yield of the product is improved.
As shown in fig. 3, the scheduling algorithm and scheduling policy of the heterogeneous integrated microsystem of the unified interconnect chip are as follows: and respectively controlling each SoC by using two FPGAs, entering a test mode, setting one SoC pin as input and the other SoC pin as output, developing and designing a unified scheduling algorithm and scheduling strategy through the read-write test of the input and the output, uniformly scheduling by using FPGA embedded software, and carrying out interconnection and intercommunication test between two interconnected SoC chips. By the method, the uniform scheduling algorithm and scheduling strategy can be carried out on the microsystem product by means of FPGA embedded software, and interconnection and intercommunication tests among the system-level heterogeneous integrated microsystem interconnection chips are completed.
As shown in fig. 4, the specific operations of high-speed synchronization of the interconnected chips are: inputting the same homologous clocks to the two FPGAs, performing read-write test on the two SoCs by using JTAG, setting one SoC as input and the other SoC as output, comparing the read-write time sequence difference with the input homologous clock time sequence to obtain the read-write delay of the two SoCs, and performing high-speed synchronous design between the interconnected chips according to the delay time to ensure the high-speed synchronization of the interconnected chips.
As shown in fig. 5, the system level integrated test flow is as follows: according to the interface design of the minimum test system, application layer software can be developed, a unified test algorithm and a test strategy designed by FPGA are called and controlled through an external interface of the minimum system and a JTAG protocol, and the comprehensive test result of the microsystem interconnection chip can be subjected to data return and data analysis through the application layer software under the application environment of the whole product and the comprehensive test result of the inner chip of the heterogeneous integrated product, and the internal design fault of the microsystem product can be visually observed through the data analysis result.
The invention provides a heterogeneous integration-oriented multi-chip interconnection comprehensive test method by taking double SoC chips and a microsystem product realized based on a TSV (through silicon via) process as an example (hereinafter referred to as microsystem) of a heterogeneous integration to be tested, and the method comprises the following steps:
step 1: and building and realizing a minimum test system design.
1-1: as shown in fig. 6, the design builds a minimal test system. The external interface can be selected from various interfaces, such as a USB interface or a PXI interface, and can be inserted into a PC (personal computer), so that a minimum test system can be realized.
1-2: and (3) products to be tested: and the double-layer SoC chip adopts TSV process design to form a microsystem test product.
Step 2: and starting a test mode and a debugging mode in the chip based on the minimum test system to realize a unified test strategy and scheduling algorithm.
2-1: and chip multi-mode selection control.
Controlling the SoC chip through the JTAG of the FPGA, using a JTAG protocol and controlling an instruction register to enable the chip to enter a test mode or other functional modes; when testing the chip, the chip is controlled to enter a test mode, and the connectivity of the chip pins can be tested.
2-2: and testing interconnection and intercommunication among the interconnected chips.
Through the JTAG interface of the FPGA which is interconnected with the chips, chip pins are configured to be in an input/output mode, test data and test instructions are input, test data 0/1 are input to one chip pin, the other chip pin is output, and the input and output data are compared to finish the test of interconnection and intercommunication among the chips.
2-3: and the interconnected chips have unified scheduling algorithm and scheduling strategy.
The method is characterized in that a uniform scheduling algorithm and a scheduling strategy are developed on the FPGA to control the interconnected chips of the microsystem product to be tested, uniform test strategy scheduling is carried out through FPGA software, and interconnection and intercommunication test among the interconnected chips of the microsystem product and self test of the storage equipment integrated on the SoC chip can be completed.
And step 3: based on the minimum test system, high-speed synchronization of the interconnected chips is realized.
3-1: and (5) configuring an FPGA homologous clock.
The same clock source is input to the two FPGAs through the crystal oscillator, as shown in fig. 7.
3-2: and the FPGA controls the input and the output of the chip.
The FPGA configures one SoC into an input mode and the other into an output mode. The input clock and the output clock are collected separately as shown in fig. 8 and 9.
3-3: and determining the difference value of the read-write time sequence of the interconnected chips.
As shown in fig. 10, the clock difference of the two SoC input/output chips is obtained by comparing with the same source clock.
3-4: high speed synchronization is performed using timing interpolation.
And according to the clock difference, designing high-speed synchronization.
And 4, step 4: and based on a minimum test system, a system-level comprehensive test flow is realized.
4-1: and (5) application layer software development.
The development of the application layer software can be based on the high-level language, and the development of the application layer software of the object-oriented high-level language can be completed under an operating system (Windows/Linux). And finishing the dispatching control of the FPGA test strategy and the test algorithm through a minimum test system external interface (USB/PXI) to carry out the comprehensive test of the microsystem interconnection chip.
4-2: and the application layer software controls the JTAG and starts the test flow.
The application layer software can start the test flow through the JTAG interface of the FPGA. According to the 1149 protocol or 1500 protocol of the JTAG, performing instruction control on the chip in the heterogeneous integrated microsystem to complete the comprehensive test of the chip.
4-3: and storing the test result.
The storage device carried by the FPGA can store the test data of the comprehensive test of the heterogeneous integrated microsystem interconnection chip.
4-4: and returning the test result, and storing and analyzing the data.
The application layer software can read the stored test data, store the data on a hard disk or other computer readable storage media, automatically analyze the stored data, display the analysis result in an image or text format, and more clearly help testers and users to identify the faults of products.
The invention can develop high-level application layer software through a minimum system external interface USB or PXI, can realize the comprehensive test flow of the system-level heterogeneous integrated micro system through the unified scheduling of the high-level application layer software, and can cover the channel test, short circuit test, high-speed synchronization, self-test and the like among TSV multi-chips in the micro system. And the unified final test result can be stored in the storage chip of the double FPGA, and the test data of the chip in the microsystem can be conveniently checked and analyzed through the visual presentation of the high-level application layer software.
The method used by the invention simplifies and clarifies the comprehensive test of the multi-chip interconnection facing the heterogeneous integration process.
To the test of single-chip product, practiced thrift a large amount of human costs and carried out artifical test to the chip, avoided artifical test to use the physical damage of detecting to the chip, also replaced the most function of ATE testing tool simultaneously, practiced thrift certain testing tool use cost.
For the test of the dual-chip interconnection microsystem product, a simple and clear test method is provided for the test between the interconnection chips, not only can the interconnection and intercommunication faults between the chips be tested, but also a uniform test strategy and a test algorithm can be provided by further developing the application layer software; realizing high-speed synchronization of the interconnected chips by means of a homologous clock; the comprehensive test method of the interconnection chip with more than two layers and stacked multilayer chips is derived.
On the basis of a comprehensive test method for multi-chip interconnection of heterogeneous integration technology, further in-depth research can be carried out, a portable test tool capable of replacing an ATE test tool is developed, and a novel portable, economical and universal method is provided for chip testing.
The above-described embodiment is only one of the embodiments that can implement the technical solution of the present invention, and the scope of the present invention is not limited by the embodiment, but includes any variations, substitutions and other embodiments that can be easily conceived by those skilled in the art within the technical scope of the present invention disclosed.
Claims (10)
1. A comprehensive test method of a heterogeneous integrated microsystem is characterized by comprising the following steps:
s1, building a minimum test system based on double FPGAs and developing application layer software according to the minimum test system;
s2, unifying a test algorithm and a test strategy of the minimum test system through the mutual matching of the application layer software and the FPGA embedded software of the S1;
s3, testing the heterogeneous integrated micro system to be tested to obtain a comprehensive test result;
s4, storing the data of the comprehensive test result obtained in the S3, transmitting the data back to application layer software for data analysis, and outputting an analysis result;
and S5, observing the internal fault of the heterogeneous integrated micro-system to be tested according to the analysis result of the S4.
2. The comprehensive test method of the heterogeneous integrated micro-system according to claim 1, wherein a USB or PXI interface is reserved when a minimum test system is built in S1.
3. The integrated test method for the heterogeneous integrated micro-system according to claim 1, wherein the FPGA of S1 is provided with a memory chip and a JTAG interface is reserved.
4. The integrated testing method of the heterogeneous integrated micro-system according to claim 3, wherein the testing of the heterogeneous integrated micro-system to be tested in S3 is based on JTAG1149 protocol or JTAG1500 protocol.
5. The integrated test method for the heterogeneous integrated micro-system according to claim 1, wherein the heterogeneous integrated micro-system to be tested in S3 is composed of dual SoC chips.
6. The integrated test method for the heterogeneous integrated micro-system according to claim 1, wherein the heterogeneous integrated micro-system to be tested in S3 is implemented based on a TSV process.
7. The integrated test method of the heterogeneous integrated micro-system according to claim 1, wherein the test process of the heterogeneous integrated micro-system to be tested comprises a high-speed synchronization method of interconnected chips in the heterogeneous integrated micro-system to be tested, and the specific steps are as follows:
s301, configuring an FPGA homologous clock;
s302, controlling an input/output mode of an interconnection chip in the heterogeneous integrated micro-system through the FPGA and respectively collecting an input clock and an output clock;
s303, comparing the input clock and the output clock acquired in the S302 with the homologous clock of the S301 to obtain the clock difference between the input mode and the output mode of the interconnection chip in the heterogeneous integrated micro system;
and S304, according to the clock difference of the S303, carrying out high-speed synchronization on the interconnected chips in the heterogeneous integrated micro-system.
8. The integrated testing method for heterogeneous integrated micro-systems according to claim 1, wherein the format of the parsing result of S4 is an image or a text.
9. An integrated test system for heterogeneous integrated microsystems, comprising:
a development module: for developing application layer software according to a minimal test system;
a debugging module: the test algorithm and the test strategy for unifying the minimum test system;
the test module is used for testing the heterogeneous integrated micro system to be tested and outputting a comprehensive test result;
the storage module is used for storing the comprehensive test result;
and the analysis module is used for analyzing the comprehensive test result in the storage module and observing the internal design fault of the heterogeneous integrated microsystem product through the analysis result.
10. A computer-readable storage medium, in which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for integrated testing of a heterogeneous integrated microsystem according to one of claims 1 to 8.
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