CN210721071U

CN210721071U - Timing controller based on FPGA

Info

Publication number: CN210721071U
Application number: CN201921584443.4U
Authority: CN
Inventors: 罗怀林; 康会彬; 周凯; 望坤
Original assignee: Hubei Chuangxin Electric Ltd By Share Ltd
Current assignee: Hubei Chuangxin Electric Ltd By Share Ltd
Priority date: 2019-09-23
Filing date: 2019-09-23
Publication date: 2020-06-09
Anticipated expiration: 2029-09-23

Abstract

The utility model provides a timing controller based on FPGA, relates to electric timing control field, and it includes main control unit and power module, and main control unit is connected with the power module electricity, and main control unit is equipped with FPGA module, interface module, output module, real-time clock module, clock taming module and DRAM memory. The GPS/BD2 time service module and the FPGA module are calibrated to provide accurate standard time and written into the real-time clock module, the set time of the upper computer and the stored real-time are compared to determine the power-on and power-off time, errors can be eliminated through comparison and adjustment with the standard time, and then power control is performed through the control relay.

Description

Timing controller based on FPGA

Technical Field

The utility model relates to an electric timing control field, especially a timing controller based on FPGA.

Background

With the continuous development of domestic industrial foundation and power construction, the scale of a factory is continuously increased, large-scale and ultra-large-scale equipment is more and more invested, the power consumption of the factory is increased rapidly, and national 'thirteen-five' planning clearly proposes that industrial enterprises are encouraged to reduce energy consumption and improve energy efficiency. In the industrial power utilization field, for encouraging the enterprise peak shifting power consumption, divide into the peak section with the power consumption time interval, flat section and millet section, millet section price of electricity is less than the peak section greatly, consequently, some industrial equipment that power consumption is big such as resistance furnace, quenching chance takes use millet section and flat section time power consumption, some normal atmospheric temperature workshop air conditioners also can open at millet section time as far as possible and reduce use cost, for convenient management, can be with these high-energy consumption equipment power linked timer, through timer controlgear power supply time interval, these timers are because self frequency is not stable enough, difference between with the lapse of time and the standard time can constantly increase, deviate more and more far with the millet section live time of settlement, it can let equipment use cost increase to get off for a long time. Therefore, a precise timing control device is needed.

In the prior art, there is also a device for precisely controlling timing, and chinese patent document CN 108471303 a describes a programmable nanosecond timing precision pulse generator based on an FPGA, and proposes a multi-channel pulse signal generator to implement a 1ns high-precision pulse timing control method. The method has no reference object, the timing object is the time set by the reference and upper computer, the internal operation is complex, and the method has higher requirements on the response of the FPGA chip.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a timing controller based on FPGA is provided, can provide accurate standard time and write in the real-time clock module through the calibration of GPS BD2 time service module and FPGA module, carry out the comparison to the time of host computer settlement time and storage and confirm the time of going up and down to compare with standard time when the electricity is constantly gone up and down in the determination, in order to ensure the accuracy of time.

In order to solve the technical problem, the utility model discloses the technical scheme who adopts is:

a timing controller based on FPGA comprises a main controller and a power supply module, wherein the main controller is electrically connected with the power supply module and is provided with an FPGA module, an interface module, an output module, a real-time clock module, a clock taming module and a clock taming module;

the peripheral circuit of the main controller comprises a GPS/BD2 time service module, a crystal oscillator module and a control relay;

the interface module is electrically connected with the GPS/BD2 time service module and the upper computer respectively; the clock taming module is respectively connected with the crystal oscillator module and the frequency divider; the real-time clock module is respectively connected with the crystal oscillator module and the FPGA module; the output module is positioned between the FPGA module and a control relay on the periphery of the main controller.

The interface module is used for receiving satellite signals from GPS and BD2, processing the satellite signals, generating second pulses and transmitting the second pulses to the main controller 1.

The upper computer is used for transmitting the set control time and corresponding operation to the main controller through the interface module.

The clock taming module is used for performing voltage control tuning on the crystal oscillator module and generating a 1Hz clock signal synchronous with the standard clock.

The real-time clock module is used for receiving the standard clock calibrated by the FPGA and providing a time comparison value for the FPGA module.

The output module is used for receiving the control pulse output by the FPGA and controlling a peripheral relay.

The main controller is also provided with a DRAM memory for storing the current time, the calibration record, the state of the control relay and the like.

The upper computer can be an HMI (human machine interface), a PC (personal computer), and the like.

The control relay is connected with the control mechanism and controls the power-on and power-off of the equipment or the electrical appliance through power-on and power-off.

The crystal oscillator module is connected with a real-time clock module, a frequency divider and a clock taming module on the main controller, satellite signals of a GPS system and a BD2 system are sent to the FPGA module after second pulses GPS _1PPS and BD2_1PPS which are output after baseband processing are optimized, meanwhile, 1Hz clock signals after the crystal oscillator frequency division are sent to the FPGA module, the FPGA module carries out voltage control tuning on the crystal oscillator through comparing the phase difference between the two, the 1Hz clock signals and the optimized U1PPS which are output by the crystal oscillator are enabled to be synchronous through the continuous closed-loop adjustment of the clock taming module, standard time is obtained, and the time is set to the real-time clock module.

The GPS/BD2 time service module is internally provided with a GPS signal processing module and a BD2 signal processing module which are both connected with the GPS/BD2 dual-mode antenna.

The power supply module comprises 3 AMS1117 voltage conversion chips and a configuration circuit thereof, converts +5.0V voltage into +3.3V, +2.5V and +1.2V voltage, and provides power for the modules in the main controller 1.

The chip of the FPGA module adopts an EP3C40F14I7 chip of Altera corporation.

The real-time clock module adopts a DS1302 chip of MAXIM company.

The interface module adopts an RS-232 interface.

The GPS/BD2 time service module is a commercially available product, such as the BD-125B time service module manufactured by Shenzhen North Tian communications Limited.

The GPS/BD2 dual-mode antenna is a commercially available product, such as a BD-142AJ antenna manufactured by Shenzhen North antenna communication Limited.

The utility model provides a pair of timing controller based on FPGA, the calibration through GPS BD2 time service module and FPGA module provides accurate standard time and writes in the real-time clock module, carries out the comparison to the real-time of host computer setting time and storage and confirms the live time, can eliminate the error through the adjustment of comparing with standard time, later operates power control through control relay.

Drawings

The invention will be further explained with reference to the following figures and examples:

fig. 1 is a schematic view of the overall structure of the present invention;

FIG. 2 is a circuit diagram of the real time clock module of the present invention;

FIG. 3 is a circuit diagram of a crystal oscillator module;

FIG. 4 is a 3.3V circuit diagram of the power supply module;

FIG. 5 is a 2.5V circuit diagram of the power supply module;

fig. 6 is a 1.2V circuit diagram of the power supply module.

In the figure: the device comprises a main controller 1, a power supply module 2, an FPGA module 3, an interface module 4, an output module 5, a real-time clock module 6, a clock taming module 7, a DRAM memory 8, a GPS/BD2 time service module 9, an upper computer 10, a crystal oscillator module 11, a frequency divider 12, a control relay 13, a control mechanism 14 and a GPS/BD2 dual-mode antenna 15.

Detailed Description

As shown in fig. 1, a timing controller based on FPGA comprises a main controller 1 and a power supply module 2, wherein the main controller 1 is electrically connected with the power supply module 2, and the main controller 1 is provided with an FPGA module 3, an interface module 4, an output module 5, a real-time clock module 6, a clock taming module 7 and a clock taming module 2;

the peripheral circuit of the main controller 1 comprises a GPS/BD2 time service module 9, a crystal oscillator module 11 and a control relay 13;

the interface module 4 is respectively electrically connected with the GPS/BD2 time service module 9 and the upper computer 10; the clock taming module 7 is respectively connected with the crystal oscillator module 11 and the frequency divider 12; the real-time clock module 6 is respectively connected with the crystal oscillator module 11 and the FPGA module 3; the output module 5 is positioned between the FPGA module 3 and a control relay 13 on the periphery of the main controller 1.

The upper computer is used for transmitting the set control time and corresponding operation to the main controller 1 through the interface module.

The clock taming module 7 is used for performing voltage control tuning on the crystal oscillator module 11 and generating a 1Hz clock signal synchronous with the standard clock.

The real-time clock module 6 is configured to receive the standard clock calibrated by the FPGA and provide a time comparison value for the FPGA module 3.

The main controller is also provided with a DRAM memory 8 for storing the current time, the calibration record, the state of the control relay and the like.

As shown in fig. 1, the control relay 13 is connected to a control mechanism 14, and the control relay 13 controls the power supply and the power failure of the device or the electrical appliance.

As shown in fig. 1, the crystal oscillator module 11 is connected to the real-time clock module 6, the frequency divider 12 and the clock taming module 7 on the main controller 1, satellite signals of the GPS system and the BD2 system, the clocks GPS _ DATE and BD2_ DATE output after baseband processing are preferably sent to the FPGA module, meanwhile, the 1Hz clock signal after crystal oscillator frequency division is compared by the FPGA module with pulse phase difference between the two, the crystal oscillator is voltage-controlled tuned by a control signal, the clock taming module continuously performs closed-loop adjustment to synchronize the 1Hz output by the crystal oscillator with the preferred clock rising edge, so as to obtain standard time, and the time is set to the real-time clock module.

As shown in fig. 1, the GPS/BD2 timing module 9 is provided with a GPS signal processing module and a BD2 signal processing module, both of which are connected to the GPS/BD2 dual-mode antenna 15.

As shown in fig. 4, 5 and 6, the power supply module 2 includes 3 AMS1117 voltage conversion chips and their configuration circuits, which convert +5.0V into +3.3V and +2.5V or +1.2V, and provide power for the modules in the main controller 1.

As shown in fig. 2, the pins X1 and X2 of the real-time clock module are connected to the crystal oscillator module, and the reference pulse provided by the crystal oscillator is used as the reference, and the connected source crystal oscillator is connected to X1 only, and the pin X2 is suspended; VCC2 provides power supply for the chip, and SCLK, I/O, CE stitch are connected with FPGA module, CE is the input pin, control read-write operation, and SCLK is the input pin, and as the clock signal of communication, I/O is the two-way communication signal, is used for reading and writing data.

As shown in fig. 3, the pin 4 of the crystal oscillator module is connected to the forward power VCC 3.3V, and the pin 2 is grounded, so that the oscillation output can be output through the pin 3.

In a preferred embodiment, the chip of the FPGA module 3 is EP3C40F14I7 chip of Altera corporation.

In a preferred embodiment, the real-time clock module 6 is a DS1302 chip of MAXIM corporation.

In a preferred embodiment, the interface module 4 employs an RS-232 interface.

In a preferred embodiment, the GPS/BD2 time service module is a commercially available product, such as the BD-125B time service module manufactured by Shenzhen North Tian communications Limited.

In a preferred embodiment, the GPS/BD2 dual-mode antenna is a commercially available product, such as a BD-142AJ antenna manufactured by shenzhen north antenna communication limited.

When the device is used, when the device is electrified for the first time, the clock taming module adjusts the rising edge of the controlled 1Hz pulse to be synchronous with the rising edge of a preferred clock signal transmitted by a GPS/BD2 dual-mode antenna, the signal is placed into the real-time clock module, the real-time clock module taking the crystal oscillator module as the reference starts to time, the FPGA module continuously reads the clock signal and compares the clock signal with the control time transmitted by an upper computer, if the time is the same, the time of the real-time clock module is compared with the clock transmitted by the GPS/BD2 timing module, if the current clocks are consistent, the operation required to be executed by the upper computer is judged, a response high level or a response low level is output to the output module, the output module controls the final mechanism to act, if the clocks are inconsistent, the clock calibration work is carried out again, then the clocks are reset, and the clocks at the moment of the mechanism act are always kept synchronous with the standard clock, and the clock calibration and reset recording, the execution action of the output module and the like are stored into the DRAM memory while working.

Claims

1. A timing controller based on FPGA is characterized in that: the intelligent power supply system comprises a main controller (1) and a power supply module (2), wherein the main controller (1) is electrically connected with the power supply module (2), and the main controller (1) is provided with an FPGA module (3), an interface module (4), an output module (5), a real-time clock module (6) and a clock taming module (7);

the peripheral circuit of the main controller (1) comprises a GPS/BD2 time service module (9), a crystal oscillator module (11) and a control relay (13);

the interface module (4) is respectively and electrically connected with the GPS/BD2 time service module (9) and the upper computer (10); the clock taming module (7) is respectively connected with the crystal oscillator module (11) and the frequency divider (12); the real-time clock module (6) is respectively connected with the crystal oscillator module (11) and the FPGA module (3); the output module (5) is positioned between the FPGA module (3) and a control relay (13) on the periphery of the main controller (1).

2. The FPGA-based timing controller of claim 1, wherein: the control relay (13) is connected with the control mechanism (14), and the control relay (13) controls the equipment or the electric appliance to be powered on or powered off through power-on and power-off.

3. The FPGA-based timing controller of claim 1, wherein: the crystal oscillator module (11) is connected with the real-time clock module (6), the frequency divider (12) and the clock taming module (7) on the main controller (1).

4. The FPGA-based timing controller of claim 1, wherein: the GPS/BD2 time service module (9) is internally provided with a GPS signal processing module and a BD2 signal processing module which are both connected with a GPS/BD2 dual-mode antenna (15).

5. The FPGA-based timing controller of claim 1, wherein: the power supply module (2) comprises 3 voltage conversion chips and a configuration circuit thereof, converts +5.0V voltage into +3.3V, +2.5V and +1.2V voltage, and provides power for the modules in the main controller (1).

6. The FPGA-based timing controller of claim 1, wherein: and the main controller is also provided with a DRAM (8).

7. The FPGA-based timing controller of claim 1, wherein: the GPS/BD2 time service module (9) receives satellite signals from a GPS and a BD2, generates second pulses and sends the second pulses to the main controller (1), and the upper computer (10) transmits set control time to the main controller (1).