CN103869687A - Clock controller and clock - Google Patents

Clock controller and clock Download PDF

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Publication number
CN103869687A
CN103869687A CN201210551619.2A CN201210551619A CN103869687A CN 103869687 A CN103869687 A CN 103869687A CN 201210551619 A CN201210551619 A CN 201210551619A CN 103869687 A CN103869687 A CN 103869687A
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China
Prior art keywords
clock
time
module
cpld
microcontroller
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CN201210551619.2A
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CN103869687B (en
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巫玲坚
鲍贤勇
曾庆宇
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Feiyada Precision Technology Co., Ltd
SHENZHEN FLYTA TECHNOLOGY DEVELOPMENT Co.,Ltd.
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Fiyta Group Co Ltd
Shenzhen Fiyta Science and Technology Development Co Ltd
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Abstract

The invention discloses a clock controller and a clock. The clock comprises a clock controller, a transmission gear train and a pointer; the clock controller comprises a control unit and an interface unit; the control unit comprises an MCU, a master-clock clock circuit and a time calibration signal receiving module; the interface unit comprises a travelling time pulse generation circuit, a motor drive circuit, a stepping motor, an LCD drive circuit, an LCD display unit, an input device, and a CPLD connected with the MCU through an address and data bus. The CPLD extends an MCU interface, so that available resources of the clock controller and the clock are more abundant; processing tasks of the MCU are shared by the CPLD, so that the complexity of software design is simplified, and the response speed is improved; and a large number of separated IC devices are replaced with the CPLD, so that devices of the clock controller and the clock are facilitated to be reduced, and thus fault points are reduced, faults and hidden troubles are reduced, the power consumption is reduced, and the stability and the reliability are improved.

Description

A kind of clock controller and clock
Technical field
The present invention relates to timing control field, more particularly, relate to a kind of clock controller and clock.
Background technology
Existing extraordinary clock and watch are generally made up of two parts: controller and movement.Controller is also referred to as master clock, the clock control cell take microcontroller (MCU) as core, while being responsible for power management, master clock timing, master clock school, master clock time showing, outside input control, Electric Machine Control and drive generation, the secondary clock of signal to synchronize with master clock and give the correct time to manage etc.Movement, also referred to as secondary clock, is made up of motor, train, pointer, is used to indicate the current master clock time.This clock controller system architecture as shown in Figure 1, it is the star-like control structure take MCU as unique key control unit, MCU has born a large amount of data processing tasks, as master clock timing, the processing of outside input and generation of motor drive signal etc., system need to be by interrupting processing each task frequently, makes that Software for Design complexity, potential faults are large, response speed is also had a greatly reduced quality, stability is relative with reliability poor.Maintenance work has brought very large puzzlement also to the user of clock and watch frequently, therefore designs a good stability, and reliability is high, and the clock controller that is easy to maintenance is just necessary.
Summary of the invention
The present invention is directed in prior art take MCU as unique key control unit, MCU bears a large amount of data processing tasks, make Software for Design complexity, potential faults is large, response speed is also had a greatly reduced quality, stability poor defect relative to reliability, a kind of clock controller and clock are provided, the double-core framework that adopts microcontroller (MCU) and CPLD (CPLD) to form, utilize the interface of CPLD expansion MCU and shared the Processing tasks of MCU, make available resource abundanter, simplify Software for Design, reduce potential faults, improve response speed, stability and reliability.
The technical scheme that the present invention solves its technical matters employing is: a kind of clock controller is provided, comprise control module and interface unit, described control module comprises microcontroller and the master clock clock circuit and the correcting delay signal receiver module that are connected with described microcontroller respectively, pulse generating circuit, motor-drive circuit, stepper motor, LCD driving circuit, LCD display device, input block and CPLD when described interface unit comprises walking; Described CPLD is connected with described microcontroller with data bus by address bus, pulse signal when the walking of pulse generating circuit output when walking described in receiving, production burst sequence is exported described motor-drive circuit, so that described motor-drive circuit drives described stepper motor to rotate; Described CPLD is also for receiving the instruction of described microcontroller and exporting to described LCD driving circuit, so that described LCD driving circuit drives described LCD display device to show corresponding content; Described CPLD is received signalization and control command and is exported to described microcontroller by described input block.
Preferably, described input block comprises Keysheet module.
Preferably, described input block also comprises wireless remote control load module.
Preferably, described signalization comprises the master clock time and gives the correct time the period.
Preferably, described control module also comprises give the correct time module and active audio amplifier; In the time that the master clock time arrives the time of giving the correct time arranging, module output audio signal playing by described active audio amplifier gives the correct time described in described microprocessor controls.
Preferably, described control module also comprises: alternating current power failure detection module, and it obtains current alternating current state, exports high level to described microcontroller in the time that alternating current has electricity, and in the time of alternating current power failure, output low level is to described microcontroller.
Preferably, described control module also comprises: power-down data protection module, when receive the low level of described alternating current power failure detection module output at described microcontroller, preserve master clock time, power down zone bit and critical data now.
Preferably, described control module also comprises: position feedback module, it is connected with described microcontroller, for judge the secondary clock time whether with master clock time synchronized, in the time that both are asynchronous, described microcontroller will be adjusted secondary clock time and master clock time synchronized.
A kind of clock is provided, and described clock comprises the clock controller of above-mentioned any one, by described stepper motor driven train, and the pointer being connected with described train.
Clock controller of the present invention and clock have following beneficial effect: the Dual Core Processing Architecture that adopts MCU and CPLD to form, and utilize CPLD to expand the interface of MCU, make the available resource of clock controller and clock abundanter; Utilize CPLD to share the Processing tasks of MCU, simplified the complexity of Software for Design, improved response speed; On the other hand, replace a large amount of IC devices that separate by CPLD, be conducive to reduce the device of clock controller and clock, thereby reduced trouble spot, lowered potential faults, reduced power consumption, improved stability and reliability.
Accompanying drawing explanation
Fig. 1 is the star-like control structure figure of existing clock controller system;
Fig. 2 is the functional block diagram of clock controller the first embodiment of the present invention;
Fig. 3 is the functional block diagram of clock controller the second embodiment of the present invention;
Fig. 4 is the network control structural drawing of clock controller of the present invention;
Fig. 5 is the functional block diagram of clock one embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further explained.
Fig. 2 is the functional block diagram of clock controller the first embodiment of the present invention, as shown in Figure 2, in the present embodiment, clock controller of the present invention comprises control module 1 and interface unit 2, wherein, control module 1 comprises microcontroller (MCU) 10, master clock clock circuit 11 and correcting delay signal receiver module 12.Pulse generating circuit 20, motor-drive circuit 21, stepper motor 22, LCD driving circuit 23, LCD display device 24, input block 25 and CPLD 26 when interface unit 2 comprises walking.
In the present embodiment, MCU 10 is as the core of control module 1, for all peripheral functional modules of management and supervision.
Master clock clock circuit 11 is made up of the read-write real-time timepiece chip and the peripheral circuit that comprise inner crystal oscillator, communicates by letter, for clock controller provides the master clock time by I2C universal serial bus with MCU10.
Correcting delay signal receiver module 12 receives by the time reference signal of wired or wireless transmission, and MCU10, by being written to master clock clock circuit 11 after the time reference signal decoding receiving, completes the calibration to the master clock time.
CPLD 26 is cores of interface unit 2, interconnects by address and data bus and MCU 10, has not only expanded the quantity of MCU10 peripheral interface, and has shared the task of Driving Stepping Motor 22.While walking, pulse generating circuit 20 comprises high frequency crystal oscillator, pulse export CPLD26, pulse production burst sequence output motor driving circuit 21 when CPLD26 will walk by its inner frequency dividing circuit and sequential logical circuit when walking.Motor-drive circuit 21 pulse sequence are amplified and are processed rear output stepper motor 22, rotate with Driving Stepping Motor 22.
The frequency dividing circuit that CPLD 26 includes and sequential logical circuit can pulse generating circuit 20 be exported when walking walk time pulse produce the pulse train of different frequency, when its middle-low frequency pulse is used for walking, secondary clock drives, when high-frequency impulse is used for chasing after, secondary clock drives.CPLD 26 inside also comprise address decoder and latch, coordinate address bus to distribute an address to connected each functional module: LCD FPDP, LCD command port, step motor control port, input block port.In the time that MCU 10 needs these functional module formulas of visitor, read and write data to corresponding address.
LCD driving circuit 23 and LCD display device 24 complete the demonstration of master clock time, master clock state and user's current operation jointly.Wherein, user's operation is inputted by input block 25.MCU10 sends to instruction the address of LCD command port, data is sent to the address of LCD FPDP, realizes the displaying contents of controlling LCD display device 20.For example, MCU10 sends to the instruction that shows the master clock time address of LCD command port, is sent to the address of LCD FPDP the master clock time, realizes the master clock time of controlling LCD display device 20.
Input block 25 is for receiving signalization and control command, and signalization comprises master clock time and the period of giving the correct time are set, and control command comprises step motor control order, control command when school.Referring to Fig. 3, input block 25 can be realized by Keysheet module 251, and user arranges master clock time and input of control commands by Keysheet module 251.Input block 25 also can be realized by wireless remote control load module 252, and wireless remote control load module 252 can be made up of infrared defeated transmitting-receiving module, realizes the remote input of control command, so that Installation and Debugging.In addition, input block 25 can be realized by Keysheet module 251 and wireless remote control load module 252.In the time that input block 25 comprises wireless remote control load module 252, control command can also comprise wireless switching control command.
In the present embodiment, MCU 10 and CPLD 26 are by address bus and data bus interconnection, MCU10 accesses CPLD 26 in the mode of access external memory, receive external input signal by the mode of reading a certain address date, the mode by writing data to external address to the periphery device is sent control command; When CPLD 26 utilizes, the high frequency crystal oscillator of pulse generating circuit 20 produces pulse train Driving Stepping Motor 22 by inner frequency dividing circuit and sequential logical circuit, the generation of pulse train does not rely on MCU 10 completely, guarantee the accuracy in recurrent interval, greatly alleviate the load of MCU 10, made clock controller have more resources to process other tasks.
Fig. 3 is the functional block diagram of clock controller the second embodiment of the present invention; as shown in Figure 3; in the present embodiment, the control module 1 of clock controller also comprises alternating current power failure detection module 13, power-down data protection module 14, the module of giving the correct time 15, active audio amplifier 16 and position feedback module 17.
Alternating current power failure detection module 13 comprises voltage comparator circuit, and it obtains current alternating current state by voltage comparator circuit, exports high level to microcontroller 10 in the time that alternating current has electricity, and in the time of alternating current power failure, output low level is to microcontroller 10.
Microcontroller 10, in the time receiving the low level that alternating current power failure detection module 13 exports, is controlled master clock time, power down zone bit and critical data that power-down data protection module 14 is preserved now.Power-down data protection module 14 comprises nonvolatile memory; master clock time, power down zone bit and the critical data of alternating current power failure are stored in nonvolatile memory; in the time that next alternating current powers on, MCU 10 takes out critical data from nonvolatile memory, while chasing after for secondary clock.
The module of giving the correct time 15 comprises audio chip, audio output interface and active audio amplifier power switch, arrive when the master clock time giving the correct time the time of setting, MCU 10 controls audio chip from audio output interface output audio signal, open active audio amplifier power switch simultaneously, play chime by active audio amplifier 16.Now, the signalization of inputting by input block 25 also comprises the time signal of giving the correct time.
Position feedback module 17 comprises optical coupled switch, and in the time of a certain ad-hoc location of pointer process, position feedback module output low level is exported all the time high level in the time of other positions.Position feedback module 17 is connected with microcontroller 10, for judge the secondary clock time whether with master clock time synchronized.When group clock time and master clock asynchronism(-nization) step, flow process when microcontroller 10 synchronously chases after enable position feedback, output control signal is to CPLD 26, and CPLD26 utilizes the high-frequency impulse Driving Stepping Motor 22 in the pulse train of different frequency of its generation to rotate, while chasing after to realize secondary clock.When after secondary clock and master clock time synchronized, microcontroller 10, sending control command to CPLD 26, makes it switch back low-frequency pulse Driving Stepping Motor 22 and rotates, and secondary clock is got back to state while normally walking.
The existing mode of industry is take single-chip microcomputer as key control unit, all peripheral functional modules of Single-chip Controlling, and single-chip microcomputer hardware resource distributes nervous, and system design flexibility is poor; Software flow is long and task is various, and Software for Design risk strengthens, entire system poor reliability.Clock controller of the present invention changes the star-like control structure (referring to Fig. 1) take single-chip microcomputer as key control unit into the parallel control structure (referring to Fig. 4) of double-core control module, reduce the operation burden of key control unit, software flow is also simpler, has improved reliability control system; Utilize CPLD to expand the interface quantity of clock controller simultaneously, can utilize hardware resource abundanter, optimized control structure, dirigibility and the expansibility of clock controller design are strengthened.
In clock controller of the present invention, MCU10 and CPLD26 are interconnected by address and data bus, the peripheral functional modules being connected with CPLD 26 is all counted as memory address one by one, when MCU 10 need to control certain peripheral functional modules or obtain the duty of this functional module, can be by writing data to this address or reading the mode complete operation of this storage address, whole operation engineering is simple.
Fig. 5 is the functional block diagram of clock one embodiment of the present invention, and as shown in Figure 5, clock of the present invention comprises clock controller of the present invention, the train 3 being driven by the stepper motor 22 of clock controller and the pointer 4 being connected with train 3.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in claim scope of the present invention.In addition, the technical characterictic in various embodiments of the present invention may be used alone, can also be used in combination.

Claims (9)

1. a clock controller, comprise control module (1) and interface unit (2), described control module (1) comprises microcontroller (10) and the master clock clock circuit (11) and the correcting delay signal receiver module (12) that are connected with described microcontroller (10) respectively, it is characterized in that pulse generating circuit (20), motor-drive circuit (21), stepper motor (22), LCD driving circuit (23), LCD display device (24), input block (25) and CPLD (26) when described interface unit (2) comprises walking; Described CPLD (26) is connected with described microcontroller (10) with data bus by address bus, clock signal while being used for the walking of pulse generating circuit (20) output while walking described in receiving, production burst sequence is exported to described motor-drive circuit (21), so that described motor-drive circuit (21) drives described stepper motor (22) to rotate; Described CPLD (26) is also for receiving the instruction of described microcontroller (10) and exporting to described LCD driving circuit (23), so that described LCD driving circuit (23) drives described LCD display device (24) to show corresponding content; Described CPLD (26) is received signalization and control command and is exported to described microcontroller (10) by described input block (25).
2. clock controller according to claim 1, is characterized in that, described input block (25) comprises Keysheet module (251).
3. clock controller according to claim 2, is characterized in that, described input block (25) also comprises wireless remote control load module (252).
4. clock controller according to claim 1, it is characterized in that, described control module (1) also comprises: alternating current power failure detection module (13), it obtains current alternating current state, in the time that alternating current has electricity, export high level to described microcontroller (10), in the time of alternating current power failure, output low level is to described microcontroller (10).
5. clock controller according to claim 4; it is characterized in that; described control module (1) also comprises: power-down data protection module (14); be used for, in the time that described microcontroller (10) receives the low level of described alternating current power failure detection module (13) output, preserving master clock time, power down zone bit and critical data now.
6. clock controller according to claim 1, is characterized in that, described signalization comprises the master clock time and gives the correct time the period.
7. clock controller according to claim 6, is characterized in that, described control module (1) also comprises the module of giving the correct time (15) and active audio amplifier (16); When the master clock time arrive arrange the time of giving the correct time time, described microcontroller (10) control described in give the correct time module (15) output audio signal and by described active audio amplifier (16) play.
8. clock controller according to claim 1, is characterized in that, described control module (1) also comprises: position feedback module (17), it is connected with described microcontroller (10), for judge the secondary clock time whether with master clock time synchronized; In the time that both are asynchronous, described microcontroller (10) is adjusted into the secondary clock time and master clock time synchronized.
9. a clock, is characterized in that, described clock comprises the clock controller described in any one in claim 1-9, the train (3) being driven by described stepper motor (22), and the pointer (4) being connected with described train (3).
CN201210551619.2A 2012-12-18 2012-12-18 Clock controller and clock Active CN103869687B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104281050A (en) * 2014-09-24 2015-01-14 得利时钟表（深圳）有限公司 Timing device of electronic watch
CN104503222A (en) * 2014-12-30 2015-04-08 飞亚达（集团）股份有限公司 Watch and method for synchronizing time thereof
CN105429724A (en) * 2015-10-20 2016-03-23 北京小鸟听听科技有限公司 Clock correction method, clock correcting device, and sound box
CN106940522A (en) * 2016-01-05 2017-07-11 精工电子有限公司 The control method of pointer driving electric motor units and pointer driving electric motor units
CN107966896A (en) * 2016-10-19 2018-04-27 精工电子有限公司 The control method of clock and watch and clock and watch

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CN101995817A (en) * 2010-11-19 2011-03-30 烟台持久钟表集团有限公司 Marine secondary clock
CN202421767U (en) * 2011-12-23 2012-09-05 中国船舶重工集团公司七五○试验场 Time unification equipment
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CN101145777A (en) * 2007-10-11 2008-03-19 中国科学院长春光学精密机械与物理研究所 GPS time synchronization terminal system
CN201749316U (en) * 2010-07-22 2011-02-16 海盐新跃电器有限公司 Intelligent electric energy meter clock multi-function quick tester
CN101995817A (en) * 2010-11-19 2011-03-30 烟台持久钟表集团有限公司 Marine secondary clock
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104281050A (en) * 2014-09-24 2015-01-14 得利时钟表（深圳）有限公司 Timing device of electronic watch
CN104503222A (en) * 2014-12-30 2015-04-08 飞亚达（集团）股份有限公司 Watch and method for synchronizing time thereof
CN104503222B (en) * 2014-12-30 2017-07-07 飞亚达（集团）股份有限公司 A kind of wrist-watch and its method for synchronizing time
CN105429724A (en) * 2015-10-20 2016-03-23 北京小鸟听听科技有限公司 Clock correction method, clock correcting device, and sound box
CN105429724B (en) * 2015-10-20 2018-03-23 北京小鸟听听科技有限公司 Clock correction method, clock correction device and audio amplifier
CN106940522A (en) * 2016-01-05 2017-07-11 精工电子有限公司 The control method of pointer driving electric motor units and pointer driving electric motor units
CN106940522B (en) * 2016-01-05 2020-08-18 精工电子有限公司 Pointer driving motor unit and pointer driving motor unit control method
CN107966896A (en) * 2016-10-19 2018-04-27 精工电子有限公司 The control method of clock and watch and clock and watch

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