CN207301706U

CN207301706U - High speed input/output control circuit based on CPLD devices

Info

Publication number: CN207301706U
Application number: CN201721066327.4U
Authority: CN
Inventors: 周秀明; 曹明; 韦奇
Original assignee: Nanjing Able Automation Equipment Co Ltd
Current assignee: Nanjing Able Automation Equipment Co Ltd
Priority date: 2017-08-23
Filing date: 2017-08-23
Publication date: 2018-05-01
Anticipated expiration: 2027-08-23

Abstract

The utility model provides a kind of high speed input/output control circuit based on CPLD devices, including clock, CPLD, CPU, memory and A/D convertor circuit, and clock connects the input end of clock of CPU and the input terminal of CPLD by buffer；CPLD connects CPU and A/D convertor circuit respectively, and CPLD receives the signal of CPU, controls A/D convertor circuit and the AD conversion data of A/D convertor circuit acquisition are transmitted to CPU；Memory is connected with CPU, for storing and exporting the data of CPU.The utility model is made CPU to directly control AD conversion, open into signal input, output signal output, has been saved resource and the time of CPU, improved the work efficiency of CPU and whole input/output control circuit by the use of CPLD.

Description

High speed input/output control circuit based on CPLD devices

Technical field

The utility model belongs to electronic technology field, and in particular to a kind of high speed input and output control based on CPLD devices Circuit.

Background technology

In existing input/output control system, directly control AD conversion usually using processor such as CPU, open into the defeated of signal Enter and output signal output.This can waste substantial amounts of cpu resource and time, cause the work efficiency of CPU not high, and then tie down The reaction speed of whole control system.

Patent a kind of the comprehensive monitoring management terminal grid-connected suitable for distributed generation resource (day for announcing 2015.04.22, bulletin Number CN204290496U) disclose a kind of grid-connected comprehensive monitoring management terminal of distributed generation resource, including power module, host CPU System, MMI modules, I/O modules, AD sampling modules, electric quantity acquisition module and current and voltage signals front end processing block, wherein main The receiving terminal of cpu system connects AD sampling modules, electric quantity acquisition module, the control terminal of main CPU system by data/address bus respectively I/O modules are connected through I/O buses.In the utility model, AD samplings, I/O input/output modules are directly controlled by CPU, needed Substantial amounts of cpu resource is consumed, the work efficiency of CPU is relatively low.

Therefore being badly in need of one kind makes CPU to control AD conversion, open into signal input, output signal output, improves CPU works Make the high speed input/output control circuit of efficiency.

Utility model content

In order to solve the above-mentioned technical problem, the utility model provides a kind of high speed input and output control based on CPLD devices Circuit, the high speed input/output control circuit by the use of CPLD, make CPU need not directly control AD conversion, open it is defeated into signal Enter, output signal output, saved resource and the time of CPU, improve the work effect of CPU and whole input/output control circuit Rate.

The utility model provides following technical solution：

A kind of high speed input/output control circuit based on CPLD devices, including clock, CPLD, CPU, memory and AD turn Circuit is changed, clock connects the input end of clock of CPU and the input terminal of CPLD by buffer, for ensuring that CPU is synchronous with CPLD And clocked flip interrupts；CPLD connects CPU and A/D convertor circuit respectively, and CPLD receives the signal of CPU, and control A/D convertor circuit is simultaneously The AD conversion data that A/D convertor circuit obtains are transmitted to CPU；Memory is connected with CPU, for storing and exporting the data of CPU.

Preferably, CPLD is connected respectively opens into signal input module and outputs signal output module；CPLD, which includes piece choosing, to be made Can unit, buffering area, AD control modules and AD read modules；Open and opened into signal input module for input into signal；Output letter Number output module outputs signal for output；Piece selects enabling unit input terminal to be connected with the output terminal of CPU, and piece selects enabling unit Output terminal connects respectively to be opened into signal input module, outputs signal output module and AD control modules；Piece select enabling unit according to CPU output reading open into, write output with AD conversion require signal control open into signal input module, output signal output module, The opening and closing of AD control modules；Buffering area includes opening into buffering area and outputs buffering area, opens into buffering area storage CPU outputs Read to open the input data into signal input module when opening into requirement signal, input data can be read by CPU；Output buffering area storage CPU outputs write writing of outputing that CPU when requiring signal exports and output data；Write to output data and be output to and output signal output module； AD control modules are connected with A/D convertor circuit input terminal, for controlling the opening and closing of A/D convertor circuit；AD read modules with A/D convertor circuit output terminal is connected, for reading the data of A/D convertor circuit and the data of A/D convertor circuit being transmitted to buffering area.

Preferably, CPLD is also connected with liquid crystal man-machine interface.

Preferably, CPU passes through RS485 interface connecting communication equipment.

Preferably, outputing signal output module includes 74273 data latches.

Preferably, 16 bit parallel data buses are further included, CPLD is by 16 bit parallel data buses and opens into signal input Module is connected with signal output module is outputed.

Preferably, memory is 2 SDRAM memories.

The beneficial effects of the utility model are：

1st, the utility model circuit design is simple, and cost is relatively low.

2nd, the utility model is by the use of CPLD, replaces CPU to perform AD conversion with CPLD, opens and input, output into signal Signal output, has saved resource and the time of CPU, improves the work efficiency of CPU.

3rd, the response speed and precision of the utility model whole input/output control circuit equipment under the conditions of equal CPU Significantly improve, improve the user experience of product.

4th, the utility model is opened into signal input module using the connection of 16 bit parallel data buses and is outputed signal output mould Block, improves the speed opened and input and output signal output into signal.

Brief description of the drawings

Attached drawing is used to provide a further understanding of the present invention, and a part for constitution instruction, with this practicality New embodiment is used to explain the utility model together, does not form the limitation to the utility model.In the accompanying drawings：

Fig. 1 is the block diagram of the utility model；

Fig. 2 is that the utility model piece selects enabling unit structure chart；

Fig. 3 is the utility model AD control module structure charts；

Fig. 4 is the utility model AD read module structure charts；

Fig. 5 is that the utility model is opened into signal input module structure chart；

Fig. 6 is that the utility model outputs signal output module structure chart.

In figure mark for：1st, clock；2、CPLD；3、CPU；4th, memory；5th, A/D convertor circuit；6th, buffer；7th, open into Signal input module；8th, signal output module is outputed；9th, piece selects enabling unit；10th, buffering area；11st, AD control modules；12、AD Read module；13rd, liquid crystal man-machine interface；14th, communication apparatus.

Embodiment

The preferred embodiment of the utility model is described below in conjunction with the accompanying drawings.

As shown in Figure 1, a kind of high speed input/output control circuit based on CPLD devices, including clock 1, CPLD2, CPU3, memory 4 and A/D convertor circuit 5, clock 1 connect the input of the input end of clock and CPLD2 of CPU3 by buffer 6 End, for ensuring that CPU3 is synchronous with CPLD2 and clocked flip interrupts.

Specifically, clock 1 uses the high-precision clock chip with temperature compensation, buffer 6 is multichannel buffer.Memory 4 be 2 SDRAM memories.Clock 1 exports the input end of clock that CPU and CPLD are respectively connected to after multichannel buffer, protects Two chip clock deviations of card are consistent and same-phase, the time in AD sampling intervals are realized by the clock timer inside CPU3.Root Reach the setting value of timer according to exterior 1 input clock cycle number of clock, trigger the interruption of highest level, which is defined as Sampling interrupt, whole circuit handle the reading and CPLD controls of AD data in this interruption.

CPLD2 connects CPU3 and A/D convertor circuit 5 respectively, and CPLD2 receives the signal of CPU3, and control A/D convertor circuit 5 is simultaneously The AD conversion data that A/D convertor circuit 5 obtains are transmitted to CPU3；Memory 4 is connected with CPU3, for storing and exporting CPU3's Data.

CPLD2 is by 16 bit parallel data buses with opening into signal input module 7 and outputing signal output module 8 and be connected. CPLD2 selects enabling unit 9, buffering area 10, AD control modules 11 and AD read modules 12 including piece；Open into signal input module 7 Opened for inputting into signal；Output signal output module 8 and output signal for output；Piece selects 9 input terminal of enabling unit and CPU3 Output terminal be connected, piece selects the output terminal of enabling unit 9 to connect respectively and opens into signal input module 7, outputs signal output module 8 With AD control modules 11；Piece select enabling unit 9 according to the CPU3 readings exported open into, write output with AD conversion require signal control open Enter signal input module 7, output the opening and closing of signal output module 8, AD control modules 11；Buffering area 10 includes opening into slow Rush area and output buffering area, open and opened when reading and open into requirement signal into buffering area storage CPU3 outputs into the defeated of signal input module 7 Enter data, input data can be read by CPU3；Output buffering area storage CPU3 outputs and write and output what CPU3 when requiring signal was exported Write and output data；Write to output data and be output to and output signal output module 8；AD control modules 11 and 5 input terminal of A/D convertor circuit It is connected, for controlling the opening and closing of A/D convertor circuit 5；AD read modules 12 are connected with 5 output terminal of A/D convertor circuit, are used for Read the data of A/D convertor circuit 5 and the data of A/D convertor circuit are transmitted to buffering area 10.

Specifically, CPLD2 is also connected with liquid crystal man-machine interface 13.

Specifically, CPU3 passes through RS485 interface connecting communications equipment 14.

Specifically, outputing signal output module 8 employs 74273 data latches.

Specific work process is as follows：As shown in Fig. 2, CPLD2 internal logic circuits are inputted into signal by opening for CPU3, outputed Signal output, three pieces of A/D chip control are selected to control the Enable Pin i.e. piece of data to select enabling unit 9, when three piece choosings require When having one by there is the request of reading or write-in, open data channel.

As shown in figure 3, AD controls process：In the address that CPU3 is specified into CPLD2 first, write-in one is customized solid Fixed value, represents the purpose of CPU next step.Piece is selected and write effective signal and gives CPLD2 by CPU3, CPLD2 receive this two Triggering starts A/D convertor circuit 5 during a signal (logic function block for starting AD conversion is realized by the logic circuit inside CPLD). According to the requirement of the chip of A/D convertor circuit 5, first make the CS feet of A/D chip effective, the input for being kept for certain time postposition AD start Pin is significant level.After AD automatic conversions, A/D chip exports the interrupt signal converted, this interrupt signal is directly sent To CPLD2, notice CPLD2 reads the position that effective AD data are specified to the buffering area 10 in CPLD2.When CPU3 is to CPLD2 When reading data, data buffering passage is opened in the piece choosing of read-write AD devices, reads the Enable Pin ad_rd signals control buffering of control The opening in area, CPU3 can read the AD buffered datas in CPLD2.

As shown in figure 4, the state output that each read-write enables is to be selected by piece with the state of the crucial position of Write post through decoding Form, so same choosing can control different read-write states.

As shown in figure 5, opened outside CPLD2 readings as follows into logic chart：CPU3 to slice select and read open into signal when, Buffering area 10 opens, and then can read to walk 16 data directly from bus, that is, 16 open into.Delay opening to be sent into signal Before rushing area 10, open into 15 and open into 16 could be provided as low and high level triggering or pulse-triggered, realize external pulse count.Each The stabilization time (open stabilization time can reduce intake wrong report) of intake can be set, such software work(in CPLD2 Energy hardware realization, it is possible to reduce the burden of CPU3 and the reliability for increasing equipment.

As shown in fig. 6, CPLD2 writes outside when outputing state, out_cs chip selection signals and out_wr are sent out by CPU3 first Signal, opens buffering area 10 and its state is set to output state, outputs data and writes after buffering area 10 by a clock Delay by 74273 data latches latch export.The bus of parallel data can realize 16 outlet and meanwhile send out so that Improve the reaction speed of device outlet.

The above descriptions are merely preferred embodiments of the present invention, is not intended to limit the present invention, although ginseng The utility model is described in detail according to previous embodiment, for those skilled in the art, it still can be with Modify to the technical solution described in foregoing embodiments, or equivalent substitution is carried out to which part technical characteristic.It is all Within the spirit and principles of the present invention, any modification, equivalent replacement, improvement and so on, should be included in this practicality Within new protection domain.

Claims

A kind of 1. high speed input/output control circuit based on CPLD devices, it is characterised in that

Including clock, CPLD, CPU, memory and A/D convertor circuit,

The clock connects the input end of clock of the CPU and the input terminal of the CPLD by buffer, described for ensuring CPU is synchronous with the CPLD and clocked flip interrupts；

The CPLD connects the CPU and the A/D convertor circuit respectively, and the CPLD receives the signal of the CPU, controls institute State A/D convertor circuit and the AD conversion data that the A/D convertor circuit obtains are transmitted to CPU；

The memory is connected with the CPU, for storing and exporting the data of CPU.
2. the high speed input/output control circuit according to claim 1 based on CPLD devices, it is characterised in that

The CPLD is connected respectively to be opened into signal input module and outputs signal output module；

The CPLD selects enabling unit, buffering area, AD control modules and AD read modules including piece；

Described open is opened into signal into signal input module for input；

The signal output module of outputing outputs signal for output；

Described is selected enabling unit input terminal and the output terminal of the CPU to be connected, and described is selected the output terminal of enabling unit to distinguish Opened described in connection into signal input module, described output signal output module and the AD control modules；Described choosing is enabled single Member opens according to the CPU readings exported, writes to output and requires to open into signal input module, described described in signal control with AD conversion Output the opening and closing of signal output module, the AD control modules；

The buffering area includes opening into buffering area and outputs buffering area, it is described open into buffering area store the CPU outputs reading open into It is required that opening the input data into signal input module described in during signal, the input data can be read by CPU；It is described to output buffering Storage CPU outputs in area's, which are write, to be outputed writing for CPU output when requiring signal and outputs data；It is described write output data be output to it is described Output signal output module；

The AD control modules are connected with the A/D convertor circuit input terminal, for controlling unlatching and the pass of the A/D convertor circuit Close；

The AD read modules are connected with the A/D convertor circuit output terminal, for reading the data of A/D convertor circuit and turning AD The data for changing circuit are transmitted to the buffering area.
3. the high speed input/output control circuit according to claim 2 based on CPLD devices, it is characterised in that described CPLD is also connected with liquid crystal man-machine interface.
4. the high speed input/output control circuit based on CPLD devices according to claim 3, it is characterised in that the CPU Pass through RS485 interface connecting communication equipment.
5. the high speed input/output control circuit according to claim 4 based on CPLD devices, it is characterised in that described to open Going out signal output module includes 74273 data latches.
6. the high speed input/output control circuit according to claim 5 based on CPLD devices, it is characterised in that further include 16 bit parallel data buses, the CPLD are opened into signal input module and described by the 16 bit parallel data bus with described Signal output module is outputed to be connected.
7. the high speed input/output control circuit according to claim 6 based on CPLD devices, it is characterised in that described to deposit Reservoir is 2 SDRAM memories.