CN103869687B - Clock controller and clock - Google Patents
Clock controller and clock Download PDFInfo
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- CN103869687B CN103869687B CN201210551619.2A CN201210551619A CN103869687B CN 103869687 B CN103869687 B CN 103869687B CN 201210551619 A CN201210551619 A CN 201210551619A CN 103869687 B CN103869687 B CN 103869687B
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Abstract
The invention discloses a clock controller and a clock. The clock comprises a clock controller, a transmission gear train and a pointer; the clock controller comprises a control unit and an interface unit; the control unit comprises an MCU, a master-clock clock circuit and a time calibration signal receiving module; the interface unit comprises a travelling time pulse generation circuit, a motor drive circuit, a stepping motor, an LCD drive circuit, an LCD display unit, an input device, and a CPLD connected with the MCU through an address and data bus. The CPLD extends an MCU interface, so that available resources of the clock controller and the clock are more abundant; processing tasks of the MCU are shared by the CPLD, so that the complexity of software design is simplified, and the response speed is improved; and a large number of separated IC devices are replaced with the CPLD, so that devices of the clock controller and the clock are facilitated to be reduced, and thus fault points are reduced, faults and hidden troubles are reduced, the power consumption is reduced, and the stability and the reliability are improved.
Description
Technical field
The present invention relates to timing control field, more particularly, it relates to a kind of clock controller and clock.
Background technology
Existing special type clock and watch are typically made up of two parts：Controller and movement.Controller is also referred to as master clock, is with micro-control
Device (MCU) processed is the clock control cell of core, when responsible power management, master clock timing, master clock school, master clock time showing, outer
The generation of portion's input control, motor control and drive signal, secondary clock and master clock synchronization and management etc. of giving the correct time.Movement is also referred to as
Make secondary clock, be made up of motor, train, pointer, for indicating the current master clock time.This clock controller system architecture
As shown in figure 1, be unique key control unit with MCU star-like control structure, MCU assume responsibility for substantial amounts of data processing and appoints
Business, such as generation of master clock timing, the process of outside input and motor drive signal etc., system needs by frequently interrupting
To process each task so that Software for Design is complicated, potential faults big, response speed is also had a greatly reduced quality, stability and reliability
Relatively poor.Frequently maintenance work brings very big puzzlement also to the user of clock and watch, therefore designs a good stability, can
By property height it is easy to the clock controller safeguarded is just necessary.
Content of the invention
The present invention is directed in prior art with MCU for unique key control unit, and MCU undertakes substantial amounts of data processing and appoints
Business is so that Software for Design is complicated, potential faults big, response speed is also had a greatly reduced quality, stability and relatively poor scarce of reliability
Fall into, a kind of clock controller and clock are provided, are constituted using microcontroller (MCU) and CPLD (CPLD)
Double-core framework, extends the interface of MCU using CPLD and has shared the process task of MCU so that available resource is richer
Richness, simplifies Software for Design, reduces potential faults, improves response speed, stability and reliability.
The present invention solves its technical problem and employed technical scheme comprise that：There is provided a kind of clock controller, including control unit
And interface unit, described control unit include microcontroller and the master clock clock circuit being connected with described microcontroller respectively and
Correcting delay signal receiver module, when described interface unit includes walking, pulse generating circuit, motor-drive circuit, stepper motor, LCD drive
Dynamic circuit, LCD display device, input block and CPLD；Described CPLD passes through
Address bus data bus is connected with described microcontroller, for when walking described in receiving pulse generation circuit output walk clock pulse
Rush signal, generate pulse train and export described motor-drive circuit, so that described motor-drive circuit drives described stepper motor
Rotate；Described CPLD is additionally operable to receive instructing and exporting to described LCD driving electricity of described microcontroller
Road, so that described LCD drive circuit drives described LCD display device to show corresponding content；Described complicated programmable logic device
Part receives setting signal and control command by described input block and exports to described microcontroller.
Preferably, described input block includes Keysheet module.
Preferably, described input block also includes wireless remote control input module.
Preferably, described setting signal includes the master clock time and gives the correct time the period.
Preferably, described control unit also includes give the correct time module and active audio amplifier；Reach giving the correct time of setting when the master clock time
During the time, module of giving the correct time described in described microprocessor control exports audio signal is simultaneously play by described active audio amplifier.
Preferably, described control unit also includes：Alternating current power failure detection module, it obtains current alternate current states, when
Alternating current has output high level during electricity, and, to described microcontroller, when alternating current power failure, output low level is to described microcontroller.
Preferably, described control unit also includes：Power-down data protection module, for receiving institute in described microcontroller
State the output of alternating current power failure detection module low level when, preserve master clock time now, power loss indicator position and critical data.
Preferably, described control unit also includes：Position feedback module, it is connected with described microcontroller, for judging
The secondary clock time whether with master clock time synchronized, when both are asynchronous, described microcontroller will adjust the secondary clock time with master clock when
Between synchronous.
There is provided a kind of clock, described clock includes the clock controller of any of the above-described, by described stepper motor driven
Train, and the pointer being connected with described train.
The clock controller of the present invention and clock have the advantages that：At the double-core being constituted using MCU and CPLD
Reason framework, extends the interface of MCU so that clock controller and the available resource of clock are abundanter using CPLD；Using
CPLD shares the process task of MCU, simplifies the complexity of Software for Design, improves response speed；On the other hand, pass through
CPLD replaces detached IC device in a large number, advantageously reducing the device of clock controller and clock, thus decreasing trouble point, subtracting
Low potential faults, decrease power consumption, improve stability and reliability.
Brief description
Fig. 1 is the star-like control structure figure of existing clock controller system；
Fig. 2 is the functional block diagram of the clock controller first embodiment of the present invention；
Fig. 3 is the functional block diagram of the clock controller second embodiment of the present invention；
Fig. 4 is the network controlling structure figure of the clock controller of the present invention；
Fig. 5 is the functional block diagram of clock one embodiment of the present invention.
Specific embodiment
Below in conjunction with drawings and Examples, the present invention is further explained.
Fig. 2 is the functional block diagram of the clock controller first embodiment of the present invention, as shown in Fig. 2 in the present embodiment, this
The clock controller of invention includes control unit 1 and interface unit 2, and wherein, control unit 1 includes microcontroller (MCU) 10, mother
Clock clock circuit 11 and correcting delay signal receiver module 12.Pulse generating circuit 20, Motor drive electricity when interface unit 2 includes walking
Road 21, stepper motor 22, LCD drive circuit 23, LCD display device 24, input block 25 and CPLD
26.
In the present embodiment, MCU 10 is as the core of control unit 1, for managing and monitoring all of peripheral function mould
Block.
Master clock clock circuit 11 is made up of the read-write real-time timepiece chip comprising internal crystal oscillator and peripheral circuit, passes through
I2C universal serial bus is communicated with MCU10, provides the master clock time for clock controller.
Correcting delay signal receiver module 12 receives the time reference signal by wired or wireless transmission, and MCU10 will receive
Time reference signal decoding after be written to master clock clock circuit 11, complete the calibration to the master clock time.
CPLD 26 is the core of interface unit 2, is interconnected with MCU 10 by address data bus, not only expands
The quantity of MCU10 peripheral interface, and shared the task of Driving Stepping Motor 22.When walking, pulse generating circuit 20 includes high frequency
Crystal oscillator, for pulse export CPLD26 when producing, CPLD26 passes through its internal frequency dividing circuit and sequential logical circuit general
When walking, pulse generates pulse train output motor drive circuit 21.Motor-drive circuit 21 is amplified to pulse train and processes
Export stepper motor 22 afterwards, rotated with Driving Stepping Motor 22.
The frequency dividing circuit that CPLD 26 includes and sequential logical circuit can walking according to pulse generating circuit when walking 20 output
When pulses generation different frequency pulse train, when its middle-low frequency pulse is used for walking secondary clock drive, when high-frequency impulse is used for chasing after son
Clock drives.Address decoder and latch is also comprised, cooperation address bus gives each function mould connected inside CPLD 26
Block distributes an address：LCD FPDP, LCD command port, step motor control port, input block port.As MCU 10
When needing these functional module formulas of visitor, read and write data to corresponding address.
LCD drive circuit 23 and LCD display device 24 complete master clock time, master clock state and user's current operation jointly
Display.Wherein, the operation of user is inputted by input block 25.MCU10 sends an instruction to the address of LCD command port,
Transmit data to the address of LCD FPDP, realize controlling the display content of LCD display device 24.For example, MCU10 will show
Show that the instruction of master clock time is sent to the address of LCD command port, be sent to the address of LCD FPDP the master clock time, real
Now control the master clock time of LCD display device 24.
Input block 25 is used for receiving setting signal and control command, and setting signal includes arranging master clock time and report
When the period, control command includes step motor control order, control command during school.Referring to Fig. 3, input block 25 can pass through key
Disk module 251 is realized, and user arranges master clock time and input control command by Keysheet module 251.Input block 25
Can be realized by wireless remote control input module 252, wireless remote control input module 252 can be by infrared defeated transmitting-receiving module group
Become, realize the remote input of control command, in order to installation and debugging.In addition, input block 25 can pass through Keysheet module 251 He
Wireless remote control input module 252 is realizing.When input block 25 includes wireless remote control input module 252, control command also may be used
To include wireless switching control command.
In the present embodiment, MCU 10 and CPLD 26 passes through address bus data bus interconnection, and MCU10 is outer to access
The mode of portion's memory accesses CPLD 26, receives external input signal, by outside by way of reading a certain address date
The outside peripheral device of mode that data is write in address sends control command；CPLD 26 is brilliant using the high frequency of pulse generating circuit when walking 20
Shake and pulse train Driving Stepping Motor 22 is produced by internal frequency dividing circuit and sequential logical circuit, the generation of pulse train is complete
It is independent of MCU 10 it is ensured that the accuracy in pulse spacing, significantly reduces the load of MCU 10, so that clock controller is had more
Resource processes other tasks.
Fig. 3 is the functional block diagram of the clock controller second embodiment of the present invention, as shown in figure 3, in the present embodiment, when
The control unit 1 of clock controller also include alternating current power failure detection module 13, power-down data protection module 14, module of giving the correct time 15,
Active audio amplifier 16 and position feedback module 17.
Alternating current power failure detection module 13 includes voltage comparator circuit, and it obtains current alternating current by voltage comparator circuit
State, when alternating current has electricity, to microcontroller 10, when alternating current power failure, output low level is to microcontroller for output high level
10.
Microcontroller 10, when receiving the low level of alternating current power failure detection module 13 output, controls power-down data protection
Module 14 preserves master clock time now, power loss indicator position and critical data.Power-down data protection module 14 includes non-volatile
Property memory, the master clock time of alternating current power failure, power loss indicator position and critical data are stored in nonvolatile memory, instantly
On secondary alternating current during electricity, critical data is taken out by MCU 10 from nonvolatile memory, uses when chasing after for secondary clock.
Module of giving the correct time 15 includes audio chip, audio output interface and active audio amplifier power switch, arrives when the master clock time
Reach giving the correct time the time of setting, MCU 10 controls audio chip from audio output interface exports audio signal, opens active sound simultaneously
Case power switch, plays chime by active audio amplifier 16.Now, the setting signal being inputted by input block 25 is also included
Give the correct time time signal.
Position feedback module 17 includes optical coupled switch, and when pointer is through a certain ad-hoc location, feedback module output in position is low
Level, exports high level all the time in other positions.Position feedback module 17 is connected with microcontroller 10, for judging the secondary clock time
Whether with master clock time synchronized.When group clock time and master clock time irreversibility, microcontroller 10 will start position feedback synchronization
Flow process when chasing after, output control signal utilizes the high frequency arteries and veins in the pulse train of different frequency that it produces to CPLD 26, CPLD26
Rush Driving Stepping Motor 22 to rotate, with when realizing secondary clock and chasing after.After secondary clock and master clock time synchronized, microcontroller 10 is sending control
System order rotates so as to switch back into low-frequency pulse Driving Stepping Motor 22 to CPLD 26, and secondary clock returns to state when normally walking.
The existing mode of industry is with single-chip microcomputer as key control unit, all peripheral functional modules of Single-chip Controlling, single
The distribution of piece machine hardware resource is nervous, and system design flexibility is poor；Software flow length and task is various, Software for Design increased risk,
System global reliability is poor.Star-like control structure with single-chip microcomputer as key control unit (is joined by the clock controller of the present invention
See Fig. 1) it is changed into the parallel control structure (referring to Fig. 4) of double-core control unit, reduce the operation burden of key control unit,
Software flow is also simpler, improves reliability control system；Expanded the number of ports of clock controller using CPLD simultaneously
Amount, available hardware resource is abundanter, optimizes control structure, and the flexibility of clock controller design and expansibility add
By force.
In the clock controller of the present invention, MCU10 and CPLD26 passes through address data bus bar, with CPLD 26 even
The peripheral functional modules connecing all are counted as storage address one by one, when MCU 10 need to control certain peripheral functional modules or
Obtain the working condition of this functional module, can be by writing data to this address or completing by way of reading this storage address to grasp
Make, whole operation engineering is simple.
Fig. 5 is the functional block diagram of clock one embodiment of the present invention, as shown in figure 5, the clock of the present invention includes the present invention
Clock controller, the train 3 being driven by the stepper motor 22 of clock controller and the finger being connected with train 3
Pin 4.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, made any repair
Change, equivalent, improvement etc., should be included within scope of the presently claimed invention.In addition, in various embodiments of the present invention
Technical characteristic may be used alone, can also be used in combination.
Claims (9)
1. a kind of clock controller, including control unit (1) and interface unit (2), described control unit (1) includes microcontroller
(10) the master clock clock circuit (11) being connected with described microcontroller (10) and respectively and correcting delay signal receiver module (12), its
It is characterised by, pulse generating circuit (20), motor-drive circuit (21), stepper motor when described interface unit (2) includes walking
(22), LCD drive circuit (23), LCD display device (24), input block (25) and CPLD (26)；
Described CPLD (26) is connected with described microcontroller (10) by address bus data bus, is used for connecing
Clock signal when walking that when walking described in receipts, pulse generating circuit (20) exports, generates pulse train and exports to described Motor drive electricity
Road (21), so that described motor-drive circuit (21) drives described stepper motor (22) to rotate；Described complicated programmable logic device
Part (26) is additionally operable to receive instructing and exporting to described LCD drive circuit (23) of described microcontroller (10), so that described LCD
Drive circuit (23) drives described LCD display device (24) to show corresponding content；Described CPLD (26)
Setting signal and control command are received by described input block (25) and exports to described microcontroller (10)；
Described CPLD (26) cooperation address bus distributes a ground to each functional module connected
Location, described microcontroller (10) is realized accessing corresponding functional module by reading and writing data to corresponding address.
2. clock controller according to claim 1 is it is characterised in that described input block (25) includes Keysheet module
(251).
3. clock controller according to claim 2 is it is characterised in that described input block (25) also includes wireless remote control
Input module (252).
4. clock controller according to claim 1 is it is characterised in that described control unit (1) also includes：Alternating current falls
Electro-detection module (13), it obtains current alternate current states, and when alternating current has electricity, output high level is to described microcontroller
(10), when alternating current power failure output low level to described microcontroller (10).
5. clock controller according to claim 4 is it is characterised in that described control unit (1) also includes：Power failure data
Protection module (14), for receiving, in described microcontroller (10), the low electricity that described alternating current power failure detection module (13) exports
At ordinary times, master clock time now, power loss indicator position and critical data are preserved.
6. clock controller according to claim 1 is it is characterised in that described setting signal includes the master clock time and gives the correct time
Period.
7. clock controller according to claim 6 is it is characterised in that described control unit (1) also includes module of giving the correct time
And active audio amplifier (16) (15)；When the master clock time reach setting give the correct time the time when, described microcontroller (10) controls described report
When module (15) exports audio signal and by described active audio amplifier (16) play.
8. clock controller according to claim 1 is it is characterised in that described control unit (1) also includes：Position is fed back
Module (17), it is connected with described microcontroller (10), for judge the secondary clock time whether with master clock time synchronized；At both not
When synchronous, described microcontroller (10) the secondary clock time is adjusted to and master clock time synchronized.
9. a kind of clock is it is characterised in that described clock includes the clock controller any one of claim 1-8, by
The train (3) that described stepper motor (22) drives, and the pointer (4) being connected with described train (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210551619.2A CN103869687B (en) | 2012-12-18 | 2012-12-18 | Clock controller and clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210551619.2A CN103869687B (en) | 2012-12-18 | 2012-12-18 | Clock controller and clock |
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| CN103869687A CN103869687A (en) | 2014-06-18 |
| CN103869687B true CN103869687B (en) | 2017-02-08 |
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| CN201210551619.2A Active CN103869687B (en) | 2012-12-18 | 2012-12-18 | Clock controller and clock |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104281050A (en) * | 2014-09-24 | 2015-01-14 | 得利时钟表（深圳）有限公司 | Timing device of electronic watch |
| CN104503222B (en) * | 2014-12-30 | 2017-07-07 | 飞亚达（集团）股份有限公司 | A kind of wrist-watch and its method for synchronizing time |
| CN105429724B (en) * | 2015-10-20 | 2018-03-23 | 北京小鸟听听科技有限公司 | Clock correction method, clock correction device and audio amplifier |
| JP6694270B2 (en) * | 2016-01-05 | 2020-05-13 | セイコーインスツル株式会社 | Pointer drive motor unit and control method for pointer drive motor unit |
| TWI746663B (en) * | 2016-10-19 | 2021-11-21 | 日商精工電子有限公司 | Timepiece and control method of timepiece |
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| CN101145777A (en) * | 2007-10-11 | 2008-03-19 | 中国科学院长春光学精密机械与物理研究所 | GPS time synchronization terminal system |
| CN101221410A (en) * | 2007-01-10 | 2008-07-16 | 精工爱普生株式会社 | Time adjustment device, timepiece with a time adjustment device, and time adjustment method |
| CN201749316U (en) * | 2010-07-22 | 2011-02-16 | 海盐新跃电器有限公司 | Intelligent electric energy meter clock multi-function quick tester |
| CN101995817A (en) * | 2010-11-19 | 2011-03-30 | 烟台持久钟表集团有限公司 | Marine secondary clock |
| CN202421767U (en) * | 2011-12-23 | 2012-09-05 | 中国船舶重工集团公司七五○试验场 | Time unification equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5747630B2 (en) * | 2011-04-21 | 2015-07-15 | セイコーエプソン株式会社 | Electronic clock and time correction method |
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| CN101221410A (en) * | 2007-01-10 | 2008-07-16 | 精工爱普生株式会社 | Time adjustment device, timepiece with a time adjustment device, and time adjustment method |
| CN101145777A (en) * | 2007-10-11 | 2008-03-19 | 中国科学院长春光学精密机械与物理研究所 | GPS time synchronization terminal system |
| CN201749316U (en) * | 2010-07-22 | 2011-02-16 | 海盐新跃电器有限公司 | Intelligent electric energy meter clock multi-function quick tester |
| CN101995817A (en) * | 2010-11-19 | 2011-03-30 | 烟台持久钟表集团有限公司 | Marine secondary clock |
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| CN103869687A (en) | 2014-06-18 |
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Address after: 518000 west side, first floor, second floor, third floor and fourth floor, building B, feiyada clock building, north side of South Ring Avenue, Gongming Street clock base, Guangming New District, Shenzhen City, Guangdong Province Co-patentee after: Feiyada Precision Technology Co., Ltd Patentee after: SHENZHEN FLYTA TECHNOLOGY DEVELOPMENT Co.,Ltd. Address before: 518034 Guangdong city of Shenzhen province Nanshan District Gao Xin Road Fiyta technology building 11 floor Co-patentee before: FIYTA (GROUP) Co.,Ltd. Patentee before: SHENZHEN FLYTA TECHNOLOGY DEVELOPMENT Co.,Ltd. |