CN115454751A - FPGA chip testing method and device and computer readable storage medium - Google Patents
FPGA chip testing method and device and computer readable storage medium Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
Abstract
The invention provides a method and a device for testing an FPGA chip, wherein the method comprises the following steps: carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal; the upper computer sends a test instruction to a test configuration tool; the test configuration tool converts the test instructions into the test stimulus and applies the test stimulus to the FPGA chip; the FPGA chip analyzes the test excitation to obtain a current test signal; and inputting the current test signal into an observation instrument, observing the current test signal by the observation instrument in real time, and verifying the current test signal and the expected test signal to obtain a current test result. The test method provided by the invention can observe the change of the test signal in real time and is beneficial to improving the test efficiency.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a method and a device for testing an FPGA chip and a computer readable storage medium.
Background
With the continuous development of integrated circuits, the functions of various application specific integrated circuits are more and more abundant, and a Field Programmable Gate Array (FPGA) is a semi-customized integrated circuit, can make up for some defects of the customized circuit, and is more flexible in product design. With the continuous expansion of FPGA scale and the continuous abundance of internal resources, testing and observing key signals in an integrated circuit become an indispensable means in the debugging process. In an integrated circuit with precious resources, the minimum area is required to be occupied, and meanwhile, as many key signals as possible can be output, which is beneficial to providing an effective solution when an internal logic circuit has problems.
In the manufacturing process of the FPGA chip, the influence of factors such as the photolithography deviation of the manufacturing process may cause the occurrence of a malfunctioning product. Therefore, before the product enters the market, strict tests are required to ensure the reliability of the related product.
However, the existing testing method has the problems of low data transmission speed, low testing efficiency, incapability of monitoring internal signals in real time and the like. Therefore, how to optimize the testing method of the FPGA chip is an urgent problem to be solved.
Disclosure of Invention
The invention provides a testing method of an FPGA chip for solving all or part of the problems in the prior art, which can observe the change of a test signal in real time and is beneficial to improving the testing efficiency.
The embodiment of the invention provides a method for testing an FPGA chip, which comprises the following steps: carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal; the upper computer issues a test instruction to a test configuration tool; the test configuration tool converts the test instructions into the test stimulus and applies the test stimulus to the FPGA chip; the FPGA chip analyzes the test excitation to obtain a current test signal; and inputting the current test signal into an observation instrument, observing the current test signal by the observation instrument in real time, and verifying the current test signal and the expected test signal to obtain a current test result. The test method provided by the invention can monitor and test the current test signal on the physical pin all the time only by carrying out test configuration loading once, so that the conditions of burst jump and the like of the internal signal can be detected in real time.
The upper computer sends the test instruction to the test configuration tool, and the test instruction can be transmitted to the test configuration tool through various interfaces, preferably the upper computer transmits the test instruction to the test configuration tool through a USB interface.
When the interface adopts a USB interface, specifically, the test configuration tool converts the test instruction corresponding to the USB interface into the test excitation corresponding to the SPI interface, and transmits the test excitation to the FPGA chip. By adopting SPI to transmit test excitation, the transmission speed can be greatly increased, and the test efficiency is improved. Here, the test signal does not need to be transmitted back to the upper computer through the SPI, and an observation instrument is directly adopted for real-time observation.
And the upper computer issues a test instruction to a test configuration tool, wherein the test instruction comprises an address and a chip area of the expected test signal. Multi-byte addresses may be used in order to increase the efficiency of processing data; similarly, to further improve the test efficiency, the test data may be divided into a plurality of sectors. In order to realize the test of multi-byte addresses and multi-chip areas, the test excitation needs to be configured to the address where the expected test signal is located and the position where the test signal is located, and the test excitation can be converted into the corresponding test excitation through the test instruction containing the address and the chip area, so that the test of the multi-byte addresses and the multi-chip areas is realized, and the efficiency is higher.
Analyzing the test excitation by the FPGA chip to obtain a current test signal, wherein the method comprises the following steps: the FPGA chip analyzes the test excitation through the test instruction analysis processing circuit to obtain the address and the chip area of the current test signal and the current test signal.
Inputting the current test signal into a scope, comprising: and outputting the current test signal to a chip FPGA physical pin based on the address and the area of the current test signal, and connecting the physical pin to an observation instrument.
Before the test configuration loading is performed on the FPGA chip, the method further comprises the following steps: carrying out application configuration loading on an FPGA chip to obtain response data, and determining the expected test signal, namely the test signal to be observed according to the response data; and switching the FPGA chip to a test mode, and connecting an external test circuit with an internal test circuit of the FPGA chip. Therefore, internal signals needing to be observed can be roughly positioned by analyzing the problems in the application configuration loading process of the FPGA chip, so that corresponding test configuration loading is carried out, and the test efficiency is improved.
After obtaining the current test result, the method further comprises: judging whether test signals of other addresses and chip areas need to be observed or not according to the current test result; if the observation is not needed, the test is finished; if observation is needed, the address and the chip area of the subsequent expected test signal are selected according to the address and the chip area of the test signal in the current test result, and the steps of the test method in the embodiment are repeatedly executed. Therefore, the test coverage rate of the internal resources of the FPGA chip is ensured through multiple test configuration loads.
The embodiment of the present invention further provides an FPGA chip testing apparatus, including: the system comprises a loading module, a sending module, a conversion module, an analysis module and an observation module; the loading module is used for carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal; the issuing module is used for issuing a test instruction to the test configuration tool by the upper computer; the conversion module is used for converting the test instruction into the test excitation by the test configuration tool and applying the test excitation to the FPGA chip; the analysis module is used for analyzing the test excitation by the FPGA chip to obtain a current test signal; and the observation module is used for inputting the current test signal into an observation instrument, observing the test signal in real time by the observation instrument, and verifying the test signal and the expected test signal to obtain a test result.
The issuing module transmits the test instruction to the test configuration tool, preferably through a USB interface.
The conversion module converts the test instruction into the test stimulus, specifically, the test configuration tool converts the test instruction corresponding to the USB interface into the test stimulus corresponding to the SPI interface, and finally transmits the test stimulus to the FPGA chip.
The test instruction may include an address and a chip area of the expected test signal.
The analysis module is configured to: the FPGA chip analyzes the test excitation through the test instruction analysis processing circuit to obtain the address and the chip area of the current test signal and the current test signal.
The observation module is configured to: and outputting the test signal to a chip FPGA physical pin based on the address and the chip area of the current test signal, and connecting the physical pin to an observation instrument.
The test device further comprises: the logic operation module is used for judging whether test signals of other addresses and areas need to be observed or not according to the test result; if the observation is not needed, the test is finished; if observation is needed, selecting the address and the chip area of the subsequent expected test signal according to the address and the chip area of the test signal in the current test result, and repeatedly executing the steps of the test method.
The invention also provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the testing method described in the above embodiments.
The invention also provides a test device, comprising: a processor and a memory for storing a computer program capable of running on the processor; wherein, the processor is configured to execute the steps of the test method according to the above embodiment when running the computer program.
Compared with the prior art, the invention has the main beneficial effects that:
according to the test method and device provided by the invention, the FPGA chip is loaded with test configuration, the upper computer issues the test instruction, the test configuration tool converts the test instruction into test excitation and then applies the test excitation to the FPGA chip, and the FPGA chip directly inputs the analyzed test signal to the observation instrument. Therefore, the test signal change can be observed in real time only by setting up a test environment once, and the test efficiency is improved. Meanwhile, as part of logic circuits in the reconfigurable system are multiplexed in the whole test flow, and the processes of loading test configuration and analyzing test excitation to obtain test signals are the same as the partial configuration mode in the practical application process of the FPGA, the repeated work of technicians and testers is reduced, and the design and the test are more convenient. And secondly, no additional logic test circuit is added in the FPGA chip, so that the FPGA chip can output as many test signals as possible while occupying less area of the chip.
Drawings
FIG. 1 is a diagram of the JTAG standard of the related art;
fig. 2 is a schematic flow chart of a testing method of an FPGA chip according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of parallel output in the testing method according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of serial output in the related art;
fig. 5 is a schematic structural diagram of a testing apparatus for an FPGA chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the specific embodiments of the present invention will be clearly and completely described below, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the related art, a typical JTAG (Joint Test Action Group) is generally used as a configuration and Test interface of a field programmable gate array, and as shown in fig. 1, an external interface only needs four signals, namely a Test clock input 11 (TCK), a Test mode select 12 (TMS), a Test data output 13 (TDO), and a Test data input 14 (TDI), but a logic circuit such as a state jump needs to be implemented according to the JTAG standard of the Institute of Electrical and Electronics Engineers (IEEE) in fpga to ensure normal operation of the JTAG. JTAG is the necessary tool to connect the user computer to the FPGA. The function of the FPGA chip is to convert USB (universal serial bus) input into JTAG input data and send the JTAG input data into the FPGA chip, so that the FPGA chip can identify instructions sent by an upper computer; and transmitting the JTAG output data to the USB conversion module and outputting the JTAG output data to the upper computer, so that the upper computer can identify the data returned by the FPGA. However, the typical JTAG test method is too slow to be able to monitor internal signals in real time due to single bit transmission. Meanwhile, the cross-clock sampling problem limits the relationship between the TCK and the internal clock, and the signal can be monitored only if the condition is satisfied, which leads to the problem that the non-integrated circuit is introduced in the debugging process, and increases the debugging difficulty.
Based on this, referring to fig. 2, an embodiment of the present invention provides a testing method for an FPGA chip, where the testing method includes:
step 201: carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal;
step 202: the upper computer issues a test instruction to a test configuration tool;
step 203: the test configuration tool converts the test instruction into test excitation and applies the test excitation to the FPGA chip;
step 204: analyzing the test excitation by the FPGA chip to obtain a current test signal;
step 205: and inputting the current test signal into an observation instrument, observing the current test signal by the observation instrument in real time, and verifying the current test signal and the expected test signal to obtain a test result.
According to the embodiment of the invention, the FPGA chip is loaded with the test configuration, the upper computer issues the test instruction, the test configuration tool converts the test instruction into the test excitation and then applies the test excitation to the FPGA chip, and the FPGA chip directly inputs the analyzed test signal to the observation instrument. Therefore, the current test signal change can be observed in real time only by setting up a test environment once, and the test efficiency is improved. Meanwhile, as part of logic circuits in the reconfigurable system are multiplexed in the whole test flow, the processes of loading test configuration and analyzing test excitation to obtain test signals are the same as the partial configuration mode in the practical application process of the FPGA, so that repeated work of technicians and testers is reduced, and design and test are more convenient. And secondly, no additional logic test circuit is added in the FPGA chip, so that the FPGA chip can output as many test signals as possible while occupying less area of the chip.
First, step 201 is executed to perform test configuration loading on the FPGA chip to obtain corresponding test stimulus and expected test signals.
Here, the test configuration data can be downloaded and programmed to connect the resources to be tested in the chip into a certain circuit structure, and after the test configuration of the FPGA chip is loaded, the FPGA chip to be tested includes the test stimulus and the expected test signal which are designed correspondingly. In actual operation, the FPGA chip can be tested, configured and loaded for multiple times, and corresponding test excitation is carried out, so that the test coverage rate of the FPGA internal resources is ensured.
In some embodiments, before the test configuration loading is performed on the FPGA chip, the method further includes: carrying out application configuration loading on the FPGA chip to obtain response data, and determining a test signal to be observed according to the response data; and switching the FPGA chip to a test mode, and connecting an external test circuit with an internal test circuit of the FPGA chip.
Before the function of the FPGA chip is applied, the FPGA chip must be specially configured, otherwise the FPGA chip does not have an internal circuit structure, and internal resources cannot be applied.
Specifically, firstly, the response data is obtained after the application configuration loading is performed on the FPGA chip. The response data here may be a problem or an abnormal situation during the application configuration loading process. And determining internal signals to be observed according to the problematic phenomenon index related design protocol, and monitoring abnormal conditions occurring in the configuration loading process of the FPGA chip. And determining a test signal to be observed according to a phenomenon index related design protocol with problems, and monitoring abnormal conditions in the configuration loading process of the FPGA chip. And then, switching the FPGA chip to a test mode, and connecting an external test circuit with an internal test circuit of the FPGA chip. In actual practice, for example, a test configuration tool or scope is connected to the FPGA chip.
Therefore, internal signals needing to be observed can be roughly positioned by analyzing the problems in the application configuration loading process of the FPGA chip, so that corresponding test configuration loading is carried out, and the test efficiency is improved.
Then, step 202 is executed, and the upper computer issues a test command to the test configuration tool.
Here, the upper computer may be an electronic device having a networking function, and the electronic device may be a configurator of an engineering device, a mobile phone, a tablet computer, a personal digital assistant, or the like. The test instruction may be a data stream issued from an upper computer. The test instructions include an address and a sector of the desired test signal. Illustratively, taking the data length of 32 bits as an address as an example, the data of 32 bits is 4 bytes, the first 16 bits are divided into a fragment area, and the data of the last 16 bits are divided into a fragment area. For example, the test command may select the corresponding address by 0, 1, 2, 3, etc., and the corresponding partition may be determined by 0 or 1, for example. In order to improve the efficiency of processing data, a multi-byte address can be adopted to improve the efficiency of processing data; similarly, to further improve the test efficiency, the test data may be divided into a plurality of areas to further improve the test efficiency. In order to realize the test of the multi-byte address and the multi-chip area, the test excitation needs to be configured to the address where the expected observation test signal is located and the position where the test observation signal is located, and the test instruction containing the address information and the chip area information can be converted into the corresponding test excitation, so that the test of the multi-byte and the multi-chip area is realized, and the efficiency is higher. The test configuration tool may be, for example, a slave burn-in tool. In actual operation, the upper computer can transmit the test instruction to the test configuration tool through the USB interface.
Next, step 203 is executed, the test configuration tool converts the test instructions into test stimulus and applies the test stimulus to the FPGA chip.
In some embodiments, the test configuration tool converts the test instruction corresponding to the USB interface into the test stimulus corresponding to the SPI interface, and transmits the test stimulus to the FPGA chip. In the related art, a JTAG test method is adopted, but the JTAG test method can only transmit single bit and has lower speed. By adopting SPI transmission test excitation, the transmission speed can be greatly increased, and the test efficiency is improved.
Then, step 204 is executed, the FPGA chip analyzes the test excitation to obtain the current test signal.
In some embodiments, the FPGA chip parses the test stimulus through the test instruction parsing processing circuit to obtain an address and a chip area of the current test signal and the current test signal. Specifically, the test instruction is transmitted to a test instruction analysis processing circuit designed in the reconfigurable system through the SPI interface, the address and the chip area where the test signal needs to be observed are analyzed according to the relevant protocol, and the analyzed result is sent to the test signal output circuit. The test instruction parsing processing circuit may be, for example, a slave processing module.
Finally, step 205 is executed to input the current test signal to the observation instrument, the observation instrument observes the current test signal in real time, and verifies the current test signal and the expected test signal to obtain a test result.
Here, the current test signal may be output to a chip FPGA physical pin based on the address and chip area of the current test signal, connecting the physical pin to the scope. Specifically, the address where the test signal to be observed is located is analyzed by the test instruction analysis processing circuit, the test signal to be observed is connected to the output circuit, and the test signal to be observed is finally output to the physical pin according to the chip area where the test signal to be observed is located, which is analyzed by the test instruction analysis processing circuit. And connecting the physical pin to an observation instrument, repeatedly configuring and loading the reconfigurable system, observing a test signal needing to be observed on the instrument in real time, and analyzing abnormal conditions.
The test method provided by the invention can monitor and test the current test signal on the physical pin all the time only by configuring the address and the chip area of the test signal once each time, thereby detecting the conditions of burst jump and the like of the internal signal in real time. In the related art, in the test method using the JTAG, after an upper computer issues a test instruction, an internal JTAG test circuit in a chip is used to analyze the test instruction, and then an analysis result still needs to be transmitted to the upper computer through a TDI signal, and the upper computer identifies data fed back by the internal JTAG through a related protocol to judge the test result. However, the data fed back by the internal JTAG is directed to the test instruction at this time, and the conditions such as burst jump of the internal signal cannot be monitored in real time. For example, poor welding of hardware inside an FPGA chip or defects in software design may occur. For monitoring a desired test signal, the test method using JTAG usually needs to issue multiple repeated test commands to ensure the accuracy of the test result. Thus, testing efficiency is wasted.
The test method provided by the invention can directly output the test signals from the physical pins, different test excitations test the test signals from the same physical pins, the test environment is set up and only needs to be configured by the upper computer without changing the test environment, and meanwhile, a plurality of groups of related test signals can be observed according to corresponding protocols, thereby greatly improving the test efficiency.
In some implementations, referring to fig. 3 and 4, each bit of data in the test signal is output in parallel. Taking the data length of 32 bits as an address as an example, the first 16 bits are divided into a fragment area, and the data of the second 16 bits are divided into a fragment area. For example, in 100 packets, the test command is address 3, and the chip area is the first 16 bits. Assume that the data of 16 bits is 1001000010100. The embodiment of the invention can output the 16-bit data in parallel through a physical pin connection observation instrument, while JTAG adopted in the related technology is single-bit output and needs a buffer to retain the data of the previous bit. The phenomenon that the jump of the test signal is abnormal and the like can be observed and judged more intuitively through the parallel data.
The test method provided by the invention can enable technicians to select sufficient signal addresses and chip areas for setting at the beginning of design according to related protocols, and the built-in test instruction analysis processing circuit can further map test instructions and further expand the test signal addresses and the chip areas, so that completely sufficient test signal addresses and chip areas can be provided.
In some embodiments, after inputting the current test signal to the observation instrument, the observation instrument observes the current test signal in real time, and verifies the current test signal and the expected test signal to obtain the test result, the method further includes: judging whether test signals of other addresses and areas need to be observed or not according to the test result; if the observation is not needed, the test is finished; if observation is needed, the address and the chip area of the subsequent expected test signal are selected according to the address and the chip area of the test signal in the current test result, and the steps of the test method of the embodiment are executed.
Specifically, when the test signal is observed in real time, whether other address and chip area signals need to be observed or not can be judged from the observed signals supplied by the designed test circuit, if the observation is not needed, the test is ended, and if the observation needs to be continued, the test signal in the test circuit is switched again. For example, if the test signal is consistent with the expected test signal, the test indicates that the FPGA chip has no fault; if the test signal is inconsistent with the expected test signal, the FPGA chip is indicated to have a fault based on the test.
The address and the chip area of the subsequent expected test signal are selected according to the address and the chip area of the test signal in the current test result, other addresses and chip areas can be selected through the result obtained by previous observation, all the addresses and the chip areas do not need to be traversed, the relation between each address and each chip area is designed in an internal circuit of the chip, and the address and the chip area of the subsequent expected test signal are selected according to the address and the chip area selected for the first time.
After the address and the chip area of the subsequent signal needing to be observed are selected, the steps of the test method of the embodiment are executed again: carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal; the upper computer issues a test instruction to a test configuration tool; the test configuration tool converts the test instruction into test excitation and applies the test excitation to the FPGA chip; analyzing the test excitation by the FPGA chip to obtain a current test signal; and inputting the current test signal into an observation instrument, observing the test signal by the observation instrument in real time, and verifying the current test signal and the expected test signal to obtain a test result.
Therefore, the test coverage rate of the internal resources of the FPGA chip is ensured through multiple times of test configuration loading. In actual operation, various configuration patterns can be designed for different resources to be tested, test configuration is loaded for multiple times, test excitation and observation test signals are repeatedly applied, and faults are diagnosed through analysis of the test signals.
The embodiment of the invention also provides an FPGA chip testing device, as shown in fig. 5, the device comprises: the system comprises a loading module 501, a sending module 502, a conversion module 503, an analysis module 504 and an observation module 505. The loading module 501 is configured to load a test configuration for the FPGA chip to obtain a corresponding test stimulus and an expected test signal; the issuing module 502 is used for issuing a test instruction to the test configuration tool by the upper computer; a conversion module 503, configured to convert the test instruction into a test stimulus by the test configuration tool, and apply the test stimulus to the FPGA chip; the analysis module 504 is used for analyzing the test excitation by the FPGA chip to obtain a current test signal; the observation module 505 is configured to input the current test signal to the observation instrument, and the observation instrument observes the current test signal in real time and verifies the current test signal and the expected test signal to obtain a test result.
And the loading module 501 is configured to load a test configuration for the FPGA chip to obtain a corresponding test stimulus and an expected test signal. Here, the test configuration data can be downloaded and programmed to connect the resources to be tested in the chip into a certain circuit structure, and after the test configuration of the FPGA chip is loaded, the FPGA chip to be tested includes the test stimulus and the expected test signal which are designed correspondingly. In actual operation, the FPGA chip can be tested, configured and loaded for multiple times, and corresponding test excitation is carried out, so that the test coverage rate of the FPGA internal resources is ensured.
And the issuing module 502 is used for issuing a test instruction to the test configuration tool by the upper computer.
Here, the upper computer may be an electronic device having a networking function, and the electronic device may be a configurator of an engineering device, a mobile phone, a tablet computer, a personal digital assistant, or the like. The test instruction may be a data stream issued from an upper computer. The test instructions include an address and a sector of the desired test signal. Illustratively, taking the length of 32-bit data as an address as an example, the 32-bit data is 4 bytes, the first 16 bits are divided into a fragment area, and the last 16 bits are divided into a fragment area. For example, the test command may select the corresponding address by 0, 1, 2, 3, etc., and the corresponding partition may be determined by 0 or 1, for example. The multi-byte address can improve the efficiency of processing data, and the test efficiency can be further improved by dividing the test data into a plurality of areas. The test configuration tool may be, for example, a slave write tool. In actual operation, the issuing module is also used for transmitting the upper computer to the test configuration tool through the USB interface.
The conversion module 503 is used for converting the test instruction into the test excitation by the test configuration tool, and applying the test excitation to the FPGA chip.
In some implementations, the conversion module is further to: the test configuration tool converts the test instruction corresponding to the USB interface into the test excitation corresponding to the SPI (serial peripheral interface) interface and transmits the test excitation to the FPGA chip. In the related art, a JTAG test method is adopted, but the JTAG test method can only transmit single bit and has lower speed. By adopting SPI transmission test excitation, the transmission speed can be greatly increased, and the test efficiency is improved.
And the analysis module 504 is used for analyzing the test excitation by the FPGA chip to obtain a current test signal.
In some embodiments, the FPGA chip parses the test stimulus through the test instruction parsing processing circuit to obtain an address and a chip area of the current test signal and the current test signal. Specifically, the test instruction is transmitted to a test instruction analysis processing circuit designed in the reconfigurable system through the SPI interface, the address and the chip area where the test signal needs to be observed are analyzed according to the relevant protocol, and the analyzed result is sent to the test signal output circuit. The test instruction parsing processing circuit may be, for example, a slave processing module.
The observation module 505 is configured to input the current test signal to the observation instrument, and the observation instrument observes the current test signal in real time and verifies the current test signal and the expected test signal to obtain a test result.
Here, the test signal may be output to a physical pin of the chip FPGA according to an address and a chip area of the current test signal, and the physical pin may be connected to the scope. Specifically, the address where the test signal to be observed is located is analyzed by the test instruction analysis processing circuit, the test signal to be observed is connected to the output circuit, and the test signal to be observed is finally output to the physical pin according to the chip area where the test signal to be observed is located, which is analyzed by the test instruction analysis processing circuit. And connecting the physical pin to an observation instrument, repeatedly carrying out configuration loading on the reconfigurable system, carrying out real-time observation on the test signal to be observed on the instrument and analyzing abnormal conditions.
In some embodiments, as shown in fig. 5, the testing device further comprises: a logic operation module 506, configured to determine whether test signals of other addresses and sectors need to be observed according to the test result; if the observation is not needed, the test is finished; if observation is needed, the address and the chip area of the subsequent expected test signal are selected according to the address and the chip area of the test signal in the current test result, and the steps of the test method of the embodiment are executed.
Specifically, when the test signal is observed in real time, whether other address and chip area signals need to be observed or not can be judged from the observed signals supplied by the designed test circuit, if the observation is not needed, the test is ended, and if the observation needs to be continued, the test signal in the test circuit is switched again. For example, if the test signal is consistent with the expected test signal, the test indicates that the FPGA chip has no fault; and if the test signal is inconsistent with the expected test signal, the FPGA chip is indicated to have a fault based on the test.
Therefore, the test coverage rate of the internal resources of the FPGA chip is ensured through multiple test configuration loads. In actual operation, various configuration patterns can be designed for different resources to be tested, test configuration is loaded for multiple times, test excitation and observation test signals are repeatedly applied, and faults are diagnosed through analysis of the test signals.
In practical applications, the loading module 501, the issuing module 502, the converting module 503, the analyzing module 504, the observing module 505, and the logic operation module 506 may be implemented by a Central Processing Unit (CPU), a microprocessor unit (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like in an embedded system.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where when the computer program is executed by a processor, the computer program executes: carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal; the upper computer sends a test instruction to a test configuration tool; the test configuration tool converts the test instruction into test excitation and applies the test excitation to the FPGA chip; analyzing the test excitation by the FPGA chip to obtain a current test signal; and inputting the current test signal into an observation instrument, observing the current test signal by the observation instrument in real time, and verifying the current test signal and the expected test signal to obtain a test result. The computer readable storage medium can be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, or CD-ROM; or may be a variety of devices including one or any combination of the above memories, such as a mobile phone, computer, tablet device, personal digital assistant, etc.
An embodiment of the present invention further provides a testing apparatus, including: a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is configured to execute any of the steps of the testing method when running the computer program.
To sum up, the embodiment of the invention loads the test configuration of the FPGA chip, the upper computer issues the test instruction, the test configuration tool converts the test instruction into the test excitation and then applies the test excitation to the FPGA chip, and the FPGA chip directly inputs the analyzed test signal to the observation instrument. Therefore, the test signal change can be observed in real time only by setting up the test environment once, and the test efficiency is improved. Meanwhile, as part of logic circuits in the reconfigurable system are multiplexed in the whole test flow, the processes of loading test configuration and analyzing test excitation to obtain the current test signal are the same as the partial configuration mode in the practical application process of the FPGA, so that repeated work of technicians and testers is reduced, and design and test are more convenient. And secondly, no additional logic test circuit is added in the FPGA chip, so that the FPGA chip can output as many test signals as possible while occupying less area of the chip.
The use of certain common english terms or letters for the clarity of the description is intended for illustrative purposes only and is not intended to limit the scope of the invention to the particular use or interpretation of the invention, and the possible chinese translations or specific letters used therein.
It is further noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Claims (11)
1. A method for testing an FPGA chip is characterized by comprising the following steps:
carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal;
the upper computer sends a test instruction to a test configuration tool;
the test configuration tool converts the test instructions into the test stimulus and applies the test stimulus to the FPGA chip;
the FPGA chip analyzes the test excitation to obtain a current test signal;
and inputting the current test signal into an observation instrument, observing the current test signal by the observation instrument in real time, and verifying the current test signal and the expected test signal to obtain a current test result.
2. The test method of claim 1,
the host computer issues the test instruction to the test configuration tool, including:
the upper computer transmits the test instruction to the test configuration tool through a USB interface;
the test configuration tool converting the test instructions into the test stimulus and applying the test stimulus to the FPGA chip, comprising:
and the test configuration tool converts the test instruction corresponding to the USB interface into the test excitation corresponding to the SPI interface and transmits the test excitation to the FPGA chip.
3. The test method according to claim 2,
the host computer issues the test instruction to the test configuration tool, including:
the test instruction comprises an address and a chip area of the expected test signal;
analyzing the test excitation by the FPGA chip to obtain a current test signal, wherein the method comprises the following steps:
the FPGA chip analyzes the test excitation through the test instruction analysis processing circuit to obtain the address and the chip area of the current test signal and the current test signal;
inputting the current test signal to a scope, comprising:
and outputting the current test signal to a chip FPGA physical pin based on the address and the area of the current test signal, and connecting the physical pin to an observation instrument.
4. The method of claim 1, wherein prior to loading the test configuration for the FPGA chip, the method further comprises:
carrying out application configuration loading on the FPGA chip to obtain response data, and determining the expected test signal according to the response data;
and switching the FPGA chip to a test mode, and connecting an external test circuit with an internal test circuit of the FPGA chip.
5. The method of claim 3, wherein after obtaining the current test result, the method further comprises:
judging whether test signals of other addresses and areas need to be observed or not according to the current test result; if the observation is not needed, the test is finished; if observation is required, selecting the address and the chip area of the subsequent expected test signal according to the address and the chip area of the test signal in the current test result, and repeatedly executing the steps of the test method according to any one of claims 1 to 4.
6. An FPGA chip testing device, characterized by comprising: the system comprises a loading module, a sending module, a conversion module, an analysis module and an observation module; wherein the content of the first and second substances,
the loading module is used for carrying out test configuration loading on the FPGA chip to obtain corresponding test excitation and an expected test signal;
the issuing module is used for issuing a test instruction to the test configuration tool by the upper computer;
the conversion module is used for converting the test instruction into the test excitation by the test configuration tool and applying the test excitation to the FPGA chip;
the analysis module is used for analyzing the test excitation by the FPGA chip to obtain a current test signal;
and the observation module is used for inputting the current test signal into an observation instrument, observing the current test signal in real time by the observation instrument, and verifying the current test signal and the expected test signal to obtain a current test result.
7. The test device of claim 6,
the issuing module is used for: the upper computer transmits the test instruction to the test configuration tool through a USB interface;
the conversion module is configured to: and the test configuration tool converts the test instruction corresponding to the USB interface into the test excitation corresponding to the SPI interface and transmits the test excitation to the FPGA chip.
8. The test device of claim 6,
the issuing module is used for: the test instruction comprises an address and a chip area of the expected test signal;
the parsing module is configured to: the FPGA chip analyzes the test excitation through the test instruction analysis processing circuit to obtain the address and the chip area of the current test signal and the current test signal;
the observation module is configured to: and outputting the current test signal to a chip FPGA physical pin based on the address and the area of the current test signal, and connecting the physical pin to an observation instrument.
9. The testing device of claim 6, further comprising:
the logic operation module is used for judging whether test signals of other addresses and areas need to be observed or not according to the test result;
if the observation is not needed, the test is finished;
if observation is required, selecting an address and a chip area of a subsequent expected test signal according to the address and the chip area of the test signal in the current test result, and repeatedly executing the steps of the test method according to any one of claims 1 to 4.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the testing method according to any one of claims 1 to 5.
11. A test apparatus, the apparatus comprising: a processor and a memory for storing a computer program capable of running on the processor;
wherein the processor is adapted to perform the steps of the testing method of any one of claims 1 to 5 when running the computer program.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116414639A (en) * | 2023-03-14 | 2023-07-11 | 珠海芯业测控有限公司 | Test scheduling method and device of chip tester, electronic equipment and storage medium |
| CN117310458A (en) * | 2023-11-29 | 2023-12-29 | 北京飘石科技有限公司 | Final testing method and device for FPGA chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116414639A (en) * | 2023-03-14 | 2023-07-11 | 珠海芯业测控有限公司 | Test scheduling method and device of chip tester, electronic equipment and storage medium |
| CN116414639B (en) * | 2023-03-14 | 2023-11-28 | 珠海芯业测控有限公司 | Test scheduling method and device of chip tester, electronic equipment and storage medium |
| CN117310458A (en) * | 2023-11-29 | 2023-12-29 | 北京飘石科技有限公司 | Final testing method and device for FPGA chip |
| CN117310458B (en) * | 2023-11-29 | 2024-01-30 | 北京飘石科技有限公司 | Final testing method and device for FPGA chip |
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