CN117310458B - Final testing method and device for FPGA chip - Google Patents
Final testing method and device for FPGA chip Download PDFInfo
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- CN117310458B CN117310458B CN202311612131.0A CN202311612131A CN117310458B CN 117310458 B CN117310458 B CN 117310458B CN 202311612131 A CN202311612131 A CN 202311612131A CN 117310458 B CN117310458 B CN 117310458B
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- 238000013100 final test Methods 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000009191 jumping Effects 0.000 claims abstract description 330
- 238000012360 testing method Methods 0.000 claims abstract description 159
- 230000005284 excitation Effects 0.000 claims description 58
- 238000004891 communication Methods 0.000 claims description 5
- 238000012986 modification Methods 0.000 claims description 3
- 230000004048 modification Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 235000008694 Humulus lupulus Nutrition 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- 238000012545 processing Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a final test method and device of an FPGA chip, and relates to the technical field of chip test. The final testing method of the FPGA chip comprises the following steps: judging whether preset configuration information of the test equipment is suitable for the resources to be tested, if not, modifying the preset jumping point number and the preset jumping point value into the target jumping point number and the target jumping point value, and operating a test module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final test result. According to the technical scheme, when the FPGA chip is subjected to final test and the preset configuration information is determined to be unsuitable for the resource to be tested, the preset configuration information suitable for the resource to be tested can be obtained by modifying the number of jumping points in the preset configuration information and the value of the preset jumping points, and the whole preset configuration information is not required to be burned again, so that the final test time of the FPGA chip is relatively short, and the final test efficiency of the FPGA chip is improved.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a final testing method and device for an FPGA chip.
Background
With the continuous development of technology, field programmable gate array (Field Programmable Gate Array, FPGA) chips are increasingly used. The FPGA chips can be applied to more fields such as network communication, aerospace, medical equipment, video image processing and the like, and the more the application fields of the FPGA chips are, the more the number of the required FPGA chips are, so that a large number of the FPGA chips are required to be manufactured. In the manufacturing process of the FPGA chips, due to factors such as manufacturing process defects, photolithography deviation, design defects, and used materials not reaching standards, a large number of FPGA chips with faults may occur. Therefore, final testing is required to be performed on the FPGA chip, and the quality of the FPGA chip is ensured through the final testing. And the final test is that the FPGA chip is tested after being packaged and before entering the market.
Currently, final testing is carried out on an FPGA chip, each resource to be tested of the FPGA chip needs to be determined, corresponding test configuration information is determined according to each resource to be tested, the test configuration information comprises the number of jumping points and the value of the jumping points of a state machine, and each resource to be tested comprises a plurality of jumping points; burning test configuration information corresponding to the first resource to be tested, and executing the following operation steps: when a start instruction is received, the test state machine starts to operate, a high-level signal is output when the value of the first jumping point is operated, so that the operation excitation module outputs excitation data, an operation result is obtained when the value of the second jumping point is operated, the operation result is obtained when the excitation data of the resource to be tested is operated, and the operation result is checked when the value of the third jumping point is operated, so that a test result is obtained; and burning the test configuration information corresponding to the nth resource to be tested, and executing the operation steps.
However, the FPGA chip has a large number of resources to be tested, and the number and the value of the jumping points of the test state machine corresponding to each resource to be tested may be different, and the test state machine can only configure the number and the value of the jumping points through the fixed configuration inside the test state machine; the limitation of the internal fixed configuration can lead to that the jump point number and the jump point value corresponding to the first resource to be measured cannot be directly changed so as to obtain the jump point number and the jump point value corresponding to the second resource to be measured; the change of the jump point number and the jump point value corresponding to different resources to be tested can be realized only by re-recording the whole test configuration information containing the jump point number and the jump point value, and the subsequent final test process of the FPGA chip can be performed after the whole test configuration information is recorded; and the time consumed for re-recording the jump point number and the jump point value corresponding to the resource to be tested is longer, so that the final test time of the FPGA chip is longer, and the final test efficiency of the FPGA chip is lower.
Disclosure of Invention
The embodiment of the invention aims to provide a final testing method and device for an FPGA chip, which solve the problem of lower final testing efficiency of the FPGA chip.
In order to solve the technical problems, the embodiment of the invention provides the following technical scheme:
the first aspect of the present invention provides a final test method for an FPGA chip, the method comprising:
when a test request is received, acquiring preset configuration information of test equipment;
judging whether preset configuration information is suitable for the resources to be tested or not, wherein the preset configuration information comprises the number of preset jumping points and the value of the preset jumping points;
if so, operating a testing module of the FPGA chip according to the preset jumping-point number and the preset jumping-point value to obtain a final testing result, wherein the final testing result is used for indicating whether the resource to be tested is correct or not;
if not, modifying the preset jumping point number and the preset jumping point value into the target jumping point number and the target jumping point value, and operating a testing module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final testing result.
A second aspect of the present invention provides a final test apparatus for an FPGA chip, the apparatus comprising:
the acquisition module is used for acquiring preset configuration information of the test equipment when receiving the test request;
the judging module is used for judging whether preset configuration information is suitable for the resources to be tested or not, wherein the preset configuration information comprises the number of preset jumping points and the value of the preset jumping points;
The running module is used for running the testing module of the FPGA chip according to the preset jumping-point number and the preset jumping-point value if applicable, so as to obtain a final testing result, wherein the final testing result is used for indicating whether the resource to be tested is correct or not;
and the modification module is used for modifying the preset jumping point number and the preset jumping point value into the target jumping point number and the target jumping point value if the preset jumping point number and the preset jumping point value are not applicable, and operating the testing module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final testing result.
A third aspect of the present invention provides an electronic apparatus, comprising: at least one processor; and at least one memory, bus, coupled to the processor; the processor and the memory complete communication with each other through a bus; the processor is configured to invoke the program instructions in the memory to perform the final test method of the FPGA chip of the first aspect or any of the alternative embodiments of the first aspect.
A fourth aspect of the present invention provides a computer readable storage medium, the storage medium including a stored program, wherein when the program is run, the device on which the storage medium is located is controlled to execute a final test method of the FPGA chip according to any of the above-mentioned first aspect or any of the alternative embodiments of the first aspect.
Compared with the prior art, the final testing method and device for the FPGA chip provided by the invention have the advantages that when a testing request is received, whether preset configuration information is suitable for a resource to be tested is judged, if yes, the testing module of the FPGA chip is directly operated through the original preset configuration information in the testing equipment, the final testing of the FPGA chip is finished, if no, the number of jumping points and the number of jumping points in the original preset configuration information in the testing equipment are modified to be suitable for the number of the jumping points and the number of the jumping points of the resource to be tested, and the testing module of the FPGA chip is operated through the modified number of the jumping points and the modified number of the jumping points, so that the final testing result is obtained to finish the testing of the FPGA chip; compared with the prior art that when all resources to be tested in the FPGA chip are subjected to final test, the method and the device have the advantages that compared with the prior art that the corresponding preset configuration information of the resources to be tested is determined through re-burning, when all the resources to be tested in the FPGA chip are subjected to final test, whether the original preset configuration information in the test equipment is suitable for the resources to be tested is determined, when the original preset configuration information is directly used when the original preset configuration information is suitable for the resources to be tested, when the preset configuration information is not suitable for the resources to be tested, the preset configuration information suitable for the resources to be tested can be obtained only by modifying the number of jumping points in the preset configuration information and the preset jumping point values, and the whole preset configuration information containing the number of jumping points and the preset jumping point values is not required to be re-burned, so that the consumption time for modifying the preset configuration information in the test equipment into the preset configuration information suitable for the resources to be tested is relatively short, further the final test time of the FPGA chip is relatively short, and the final test efficiency of the FPGA chip is improved.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, wherein like or corresponding reference numerals indicate like or corresponding parts, there are shown by way of illustration, and not limitation, several embodiments of the invention, in which:
FIG. 1 schematically shows a flow chart one of a final test method of an FPGA chip;
FIG. 2 schematically illustrates a second flowchart of the final test method of the FPGA chip;
FIG. 3 schematically shows a test schematic of the final test method of the FPGA chip;
FIG. 4 schematically shows a first block diagram of a final test apparatus of an FPGA chip;
FIG. 5 schematically shows a second block diagram of the final test apparatus of the FPGA chip;
fig. 6 schematically shows a structural diagram of the electronic device.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It should be noted that: unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
For final testing of the FPGA chip, the change of the jump point number and the jump point value corresponding to different resources to be tested in the prior art can be realized only by re-burning, and the whole testing configuration information comprising the jump point number and the jump point value can be completely burnt, so that the subsequent final testing process of the FPGA chip can be performed. Therefore, the invention considers that the prior art can only realize the change of the jumping point quantity and the jumping point value corresponding to different resources to be tested by re-burning, and the burning of the jumping point quantity and the jumping point value corresponding to the resources to be tested is carried out again, which requires longer time, so that the final test time of the FPGA chip is longer, a processing mode of changing the shorter time of the jumping point quantity and the jumping point value corresponding to the different resources to be tested is needed, and the changing mode of changing the jumping point quantity and the jumping point value corresponding to the different resources to be tested by re-burning in the prior art is replaced. Therefore, the method selects a mode of changing the corresponding jumping point number and the corresponding jumping point value of different resources to be tested, can judge whether the preset configuration information is suitable for the resources to be tested, and under the condition of inapplicability, modifies the preset jumping point number and the preset jumping point value into the target jumping point number and the target jumping point value, and operates a testing module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final testing result, can only modify the inapplicable preset jumping point number and the preset jumping point value, does not need to modify the applicable preset jumping point number and the preset jumping point value, does not need to re-burn all data in the preset configuration information, and ensures that the time consumption for changing the preset jumping point number and the preset jumping point value in the preset configuration information is short. The main idea of the invention is to judge whether the preset configuration information is suitable for the resource to be tested, for the unsuitable preset jumping point number and preset jumping point value, the final test result can be obtained by only modifying the preset jumping point number and the preset jumping point value and then operating the test module of the FPGA chip according to the modified jumping point number and the modified jumping point value, and for the suitable preset jumping point number and the suitable preset jumping point value, the final test result can be obtained by directly operating the test module of the FPGA chip through the original preset jumping point number and the preset jumping point value.
The method in the embodiment of the present invention is described in detail below.
Fig. 1 schematically illustrates a flowchart of a method for testing an FPGA chip in an embodiment of the present invention, and referring to fig. 1, the method may include:
s101, when a test request is received, acquiring preset configuration information of test equipment.
The execution subject of the invention can be a terminal device, and the terminal device can comprise a desktop computer, a notebook computer, a tablet personal computer, a mobile phone and the like. The test equipment may be a test state machine. The test equipment is arranged on the FPGA chip and is in communication connection with the terminal equipment.
S102, judging whether the preset configuration information is suitable for the resource to be tested.
The preset configuration information comprises a preset jumping point number and a preset jumping point value.
Specifically, it is determined whether the preset configuration information obtained in step S101 is suitable for the resource to be tested. The method mainly comprises the step of judging whether the preset jumping point number and the preset jumping point value are suitable for the resource to be tested.
The preset number of jumping points and the preset number of jumping points are set in the test device. The resources to be measured may be a lookup table, a digital signal processor, a register, an embedded memory block, and input/output, or other resources, which are not limited herein.
The FPGA chip comprises a plurality of resources to be tested, and because the preset configuration information corresponding to different resources to be tested possibly has the same condition, the test of different FPGA chips comprises the same resources to be tested, and the preset configuration information corresponding to the same resources to be tested possibly is the same, so that in order to save time by not repeatedly changing the same preset configuration information, whether the preset configuration information is applicable to the resources to be tested or not needs to be judged.
Judging whether the preset configuration information is suitable for the resource to be tested, if so, executing step S103, and if not, executing step S104.
And S103, running a testing module of the FPGA chip according to the preset jumping-point number and the preset jumping-point value to obtain a testing result.
The test result is used for indicating whether the resource to be tested is correct or not.
Specifically, when the preset jumping point number and the preset jumping point value of the testing device are determined to be suitable for the resources to be tested, the testing module of the FPGA chip is operated according to the preset jumping point number and the preset jumping point value, which are determined in step S102, to be suitable for the resources to be tested, so as to obtain a testing result.
S104, modifying the preset jumping point number and the preset jumping point value into the target jumping point number and the target jumping point value, and operating a testing module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a testing result.
Specifically, when it is determined that the preset jump point number and the preset jump point value of the test device are not suitable for the resource to be tested, modifying the preset jump point number and the preset jump point value, which are determined in the step S102 and are not suitable for the resource to be tested, into the target jump point number and the target jump point value, and operating the test module of the FPGA chip according to the target jump point number and the target jump point value, so as to obtain a test result.
The terminal device may modify the preset number of jumping points and the preset value of jumping points to a target number of jumping points and a target value of jumping points through a joint test workgroup (Joint Test Action Group, JTAG) interface.
Based on the implementation manner of fig. 1, it can be seen that, in the embodiment of the present invention, by judging whether the preset configuration information is suitable for the resource to be tested, and when the preset configuration information is not suitable for the resource to be tested, by modifying the number of jumping points and the preset value of the jumping points in the preset configuration information, the purpose of quickly modifying the preset configuration information including the number of jumping points and the preset value of the jumping points is achieved; when the preset configuration information is determined to be unsuitable for the resources to be tested, the preset configuration information suitable for the resources to be tested can be obtained by only modifying the number of jumping points in the preset configuration information and the preset jumping point value, and the whole preset configuration information comprising the number of the jumping points and the preset jumping point value is not required to be burned again, so that the consumption time for modifying the preset configuration information in the test equipment into the preset configuration information suitable for the resources to be tested is relatively short, the final test time of the FPGA chip is relatively short, and the final test efficiency of the FPGA chip is improved.
As a refinement and extension of the above embodiment, specific operations of the final test of the FPGA chip may be illustrated by fig. 2, and fig. 2 is a flowchart two of a final test method of the FPGA chip in the embodiment of the present invention, and referring to fig. 2, the final test method of the FPGA chip provided in the embodiment of the present invention may include:
s201, when a test request is received, preset configuration information of the test equipment is obtained.
Step S201 is the same as step S101, and thus will not be described here.
S202, searching target configuration information corresponding to the resource to be detected in a corresponding relation table of the resource to be detected and the target configuration information.
The target configuration information required by different resources to be tested may be the same or different. The corresponding relation between the resources to be tested and the target configuration information can be established, a corresponding relation table is generated, and the target configuration information corresponding to the resources to be tested is searched in the corresponding relation table of the resources to be tested and the target configuration information.
For example, all the resources to be tested in the FPGA chip include a resource to be tested a, a resource to be tested B, a resource to be tested C and a resource to be tested D, where the target configuration information corresponding to the resource to be tested a is the configuration information a, the target configuration information corresponding to the resource to be tested B is the configuration information B, the target configuration information corresponding to the resource to be tested C is the configuration information C, the target configuration information corresponding to the resource to be tested D is the configuration information D, the corresponding relation 1 between the resource to be tested a and the configuration information a is established, the corresponding relation 2 between the resource to be tested B and the configuration information B is established, the corresponding relation 3 between the resource to be tested C and the configuration information C is established, and the corresponding relation 4 between the resource to be tested D and the configuration information D is established; and the resource A to be tested in the FPGA chip needs to be tested, and the configuration information a in the corresponding relation 1 is found in the corresponding relation table.
S203, judging whether the preset configuration information is the same as the target configuration information.
Specifically, it is determined whether the preset configuration information in the test device is the same as the target configuration information found in step S202. The key is to judge whether the preset jumping point number and the preset jumping point value in the preset configuration information are the same as the target jumping point number and the target jumping point value in the target configuration information.
Judging whether the preset configuration information is the same as the target configuration information, if so, executing step S204a, and if not, executing step S204b.
S204a, determining that preset configuration information is suitable for the resources to be tested.
Specifically, if the preset configuration information determined in step S203 is the same as the target configuration information, it is determined that the preset configuration information is suitable for the resource to be tested. The method mainly comprises the step of determining that preset configuration information is applicable to resources to be tested under the condition that the preset jumping-point number and the preset jumping-point value in preset configuration information are the same as the target jumping-point number and the target jumping-point value in target configuration information.
The preset configuration information includes a preset jumping point number E and a preset jumping point value E, and the target configuration information includes a target jumping point number E and a target jumping point value E, and since the jumping point number E and the jumping point value E are the same, it can be determined that the preset configuration information is applicable to the resource to be measured.
S204b, determining that the preset configuration information is not suitable for the resource to be tested.
Specifically, in the case that the preset configuration information determined in step S203 is different from the target configuration information, it is determined that the preset configuration information is not suitable for the resource to be tested. The method mainly comprises the step of determining that preset configuration information is not suitable for resources to be tested under the condition that the preset jumping-point number and the preset jumping-point value in preset configuration information are different from the target jumping-point number and the target jumping-point value in target configuration information.
The preset configuration information includes a preset jumping point number E and a preset jumping point value E, the target configuration information includes a target jumping point number F and a target jumping point value F, and since the jumping point number E and the jumping point number F are different, the jumping point value E and the jumping point value F are different, it can be determined that the preset configuration information is not suitable for the resource to be measured.
S205, running a testing module of the FPGA chip according to the preset jumping-point number and the preset jumping-point value to obtain a final testing result.
The final test result is used for indicating whether the resource to be tested is correct or not.
Specifically, after determining that the preset configuration information is suitable for the resource to be tested in step S204a, the test module of the FPGA chip is operated according to the preset number of jumping points and the preset value of jumping points, so as to obtain a final test result.
After determining that the preset configuration information is not suitable for the resource to be tested in step S204b, the preset number of jumping points and the preset value of jumping points need to be modified into the target number of jumping points and the target value of jumping points. The following steps S206 and S207 are specific operation steps of modifying the preset number of jumping points and the preset value of jumping points to the target number of jumping points and the target value of jumping points.
S206, when the preset jumping point number is different from the target jumping point number, replacing the preset jumping point number with the target jumping point number, and replacing the preset jumping point value with the target jumping point value.
Wherein the target configuration information includes a target jumping point number and a target jumping point value.
Specifically, after determining that the preset configuration information is not suitable for the resource to be tested in step S204b, when the preset number of jumping points is different from the target number of jumping points, the preset number of jumping points is replaced with the target number of jumping points, and the preset number of jumping points is replaced with the target number of jumping points.
When the preset number of jumping points is different from the target number of jumping points, so that the preset number of jumping points needs to be replaced by the target number of jumping points, and the preset number of jumping points needs to be replaced by the target number of jumping points.
For example, the number of preset jumping points is 3, that is, 3 preset jumping points are respectively preset jumping point 1, preset jumping point 2 and preset jumping point 3, the number of target jumping points is 4, that is, 4 preset jumping points are respectively target jumping point 1, target jumping point 2, target jumping point 3 and target jumping point 4, the preset jumping point values corresponding to the 3 preset jumping points are respectively 10, 15, 25,4 target jumping points are respectively 10, 15, 25 and 115, the preset jumping point number is different from the target jumping point number, the preset jumping point value is different from the target jumping point value, the preset jumping point number 3 needs to be replaced with 4, and the preset jumping point values are replaced with 10, 15, 25 and 115.
S207, when the preset jumping point number is the same as the target jumping point number and the preset jumping point value is different from the target jumping point value, replacing the preset jumping point value with the target jumping point value.
Specifically, after determining that the preset configuration information is not suitable for the resource to be tested in step S204b, when the preset number of jumping points is the same as the target number of jumping points and the preset number of jumping points is different from the target number of jumping points, the preset number of jumping points is replaced with the target number of jumping points.
For example, the number of preset jumping points is 3, that is, 3 preset jumping points are respectively 1, 2 and 3, and the number of target jumping points is 3, that is, 4 preset jumping points are respectively 1, 2 and 3, and the number of target jumping points is respectively 10, 15 and 25, and the number of target jumping points is respectively 10, 115 and 215, and the number of preset jumping points is the same as the number of target jumping points, but the number of preset jumping points is different from the number of target jumping points, and the original values of 10, 15 and 25 of the preset jumping points need to be replaced by 10, 115 and 215.
S208, outputting the replaced target jumping point number and the target jumping point value or the replaced target jumping point value to the testing equipment through a joint testing work group JTAG interface in the FPGA chip.
Specifically, when the preset jumping point number is different from the target jumping point number, replacing the preset jumping point number with the target jumping point number, and outputting the replaced target jumping point number and the target jumping point number to the testing equipment through a joint testing work group JTAG interface in the FPGA chip; when the number of the preset jumping points is the same as the number of the target jumping points and the preset jumping point values are different from the target jumping point values, replacing the preset jumping point values with the target jumping point values, and outputting the replaced target jumping point values to the testing equipment through a joint testing working group JTAG interface in the FPGA chip.
Taking the example of step S206, replace the number of jumping points 3 with 4 and the number of jumping points with 10, 15, 25, 115, and output the number of jumping points 4 and the number of jumping points 10, 15, 25, 115 to the test device via the JTAG interface in the FPGA chip.
In the example of the receiving step S207, the original jump point values 10, 15, 25 are replaced with 10, 115, 215, and the jump point values 10, 115, 215 are output to the test equipment through the JTAG interface in the FPGA chip.
The JTAG interface is arranged on the FPGA chip, so that the FPGA chip and the terminal equipment can be communicated and transmitted.
After the test equipment receives the replaced target jumping point number and the target jumping point value or the replaced target jumping point value, a counter in the test equipment can perform counting work.
And step S208, outputting the replaced target jumping point number and the target jumping point value or the replaced target jumping point value to test equipment through a JTAG interface in the FPGA chip, and then operating a test module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final test result.
The following steps S209 to S214 are specific operation steps of running the test module of the FPGA chip according to the number of target jumping-points and the number of target jumping-points to obtain a final test result.
The step S205 may be executed according to the following manner from step S209 to step S214 to obtain a final test result by running the test module of the FPGA chip according to the preset number of jumping points and the preset number of jumping points.
S209, acquiring a counter value in the test equipment.
The testing module comprises an excitation module and a resource to be tested.
The counter is arranged in the test equipment and is used for accumulating jump point values, and the terminal equipment can acquire the counter values in the test equipment on the FPGA chip.
The counter values in the test device may be obtained at preset time intervals, which may be 0.5 seconds, which may be determined according to a specific scenario, which is not limited herein.
S210, when the counter value is the same as the first target jumping point value, the operation test device outputs a target level signal.
Specifically, when the counter value obtained in step S209 is the same as the first target jump point value, it is indicated that the counter has counted to the first jump point, and the test device is operated to output the target level signal.
Illustratively, the first target trip point value is 10, the second target trip point value is 15, and the third target trip point value is 25, and the operational test device outputs the target level signal when the counter value is 10.
S211, starting the excitation module and the resource to be tested by utilizing the target level signal.
Specifically, the excitation module and the resource to be tested are started by using the target level signal output in the operation of step S210.
S212, operating the excitation module so that the excitation module outputs test excitation data when the counter value is the same as the second target jumping-point value.
Specifically, after the excitation module and the resource to be tested are started by using the target level signal, the excitation module can be operated, and when the counter value is the same as the second target jump point value, the excitation module can output test excitation data.
Operating the stimulus module such that the counter value is the same as the second target jump point value, the stimulus module outputting specific operations of the test stimulus data, comprising:
step A1: and clearing the initial data of the excitation module and generating cleared instructions.
The initial data of the excitation module is cleared, so that the test excitation data output by the excitation module can be ensured to be accurate.
Step A2: and sending a cleared instruction to the excitation module, so that the excitation module converts the target level signal into a preset level signal when receiving the cleared instruction, and outputs test excitation data when the counter value is the same as the second target jumping-point value.
The excitation module can convert the target level signal into a preset level signal when receiving the emptied instruction sent by the terminal equipment, and output test excitation data when the counter value is the same as the second target jumping point value.
In the example of the receiving step S210, the target level signal is output when the counter value is 15.
Illustratively, the test stimulus data may be 0000, 1010, 0110, and 0001.
S213, running the resource to be tested so that the resource to be tested performs logic operation according to the test excitation data to obtain operation data.
Specifically, after the excitation module is operated, the resource to be tested is operated, so that the resource to be tested can perform logic operation according to the test excitation data output by the excitation module, and operation data is obtained.
The logical operation performed by the resource to be tested is performed according to the logic provided by the resource to be tested, and the logical operation may be "and" negation ", or may be other operations, and the logical operation is not limited herein.
The example of the acceptance step S212 is a logical operation of and-ing the test stimulus data of 0000, 1010, 0110, and 0001.
S214, comparing the operation data with preset data to output a final test result when the counter value is the same as the third target jumping-point value.
Specifically, the operation data obtained in step S213 is compared with the preset data, so as to output the final test result when the counter value is the same as the third target jump point value.
Illustratively, the first target jump point value is 10, the second target jump point value is 15, the third target jump point value is 25, and the final test result is output when the counter value is 25. The final test result can be printed out so as to intuitively see the test result of the resource to be tested. Because the FPGA chip is provided with a plurality of resources to be tested, the test result corresponding to each resource to be tested is correct, the test of the FPGA chip is passed, and the quality of the FPGA chip is qualified.
As another embodiment of the present invention, the present embodiment includes the steps of:
step one, determining the number of jumping points and the corresponding jumping point value of each jumping point according to the resources to be detected.
The jump point values corresponding to each resource to be measured may be the same or different, and several jump points and the jump point values corresponding to the jump points need to be determined according to the resource to be measured.
And step two, configuring a plurality of jumping points corresponding to the resources to be tested on the test equipment through the JTAG interface.
Specifically, a counter may be designed on the test device, and the counter is used to determine whether the counter has accumulated the jump point value. The terminal equipment is provided with the jumping point quantity and the jumping point value, and the terminal equipment can configure a plurality of jumping points and the jumping point value corresponding to the resource to be tested on the testing equipment through the JTAG interface. The last point of the jump point may be the test equipment exit point and may be configured to the test equipment via the JTAG interface.
Illustratively, the plurality of jumping-points may be 1, 2, … …, N.
And step three, when the obtained numerical value of the counter is the same as the jump point numerical value of the test equipment, operating the test equipment to output a corresponding sign signal.
The terminal device may obtain the value of the counter in the test device configured with the number of jumping points and the corresponding value of the jumping points, and when the obtained value of the counter is the same as the value of the jumping points of the test device, operate the test device to output the corresponding flag signal.
And step four, driving the excitation module and the resource to be tested according to the mark signal so as to finish the test.
The excitation module can be driven by the sign signal, the excitation module outputs excitation data through internal operation, then the resource to be tested is driven, logic operation is carried out on the resource to be tested according to the excitation data, an operation result is output, the operation result is compared with a preset result corresponding to the resource to be tested, a test result is obtained, whether the test of the resource to be tested is passed or not can be obtained through the test result, and the test can be completed.
Each FPGA chip is provided with a plurality of resources to be tested, and the FPGA chip is qualified when all the tests of the resources to be tested are passed.
Fig. 3 is a test schematic diagram of a final test method of an FPGA chip in an embodiment of the present invention, which has a JTAG unit, and includes a state machine starting point 0, a state machine jumping point 1, a state machine jumping point 2, a state machine jumping point N, and a state machine exit point M. The multiple jumping-points corresponding to the resource under test may be configured to the test device, i.e., state machine, via the JTAG interface, e.g., state machine jumping-point 1, state machine jumping-point 2, state machine jumping-point N, and state machine exit point M. When the value of the acquired counter is the same as the value of the jump point of the state machine, the running state machine outputs a corresponding flag signal, for example, when the value of the acquired counter is the same as the value of the jump point 1 of the state machine, the running state machine outputs the flag signal 1, when the value of the acquired counter is the same as the value of the jump point 2 of the state machine, the running state machine outputs the flag signal 2, when the value of the acquired counter is the same as the value of the jump point |N of the state machine, the running state machine outputs the flag signal N, and when the value of the acquired counter is the same as the value of the jump point M of the state machine, the counter does not count any more. And driving the excitation module and the resource to be tested according to the mark signal so as to complete the test. The enabling configuration of the excitation module and the resource to be tested can be performed according to the mark signal 1, the mark signals 2 and … … and the mark signal N, namely, the enabling of the excitation module and the resource to be tested is turned on to drive the excitation module and the resource to be tested. When the excitation module and the resource to be tested are driven, the excitation module is driven to output excitation, the resource to be tested is driven to perform logic operation according to the output excitation, an operation result is output, the operation result is sent to the terminal equipment through the JTAG unit, the terminal equipment compares the operation result with a preset result corresponding to the resource to be tested, a test result is obtained, whether the test of the resource to be tested is passed or not can be obtained through the test result, and the test can be completed.
Because the FPGA chip is provided with a plurality of resources to be tested, the number of jumping points and the value of the jumping points corresponding to each resource to be tested can be different, and the terminal equipment can be used for configuring different numbers of the jumping points and different values of the jumping points for the resources to be tested with different numbers of the jumping points and different values of the jumping points on the state machine. Different jumping point numbers and jumping point values can be configured on the state through JTAG, different configurations can be carried out on the state machine for resources to be tested with different jumping point numbers and jumping point values, and various application scenes can be tested.
The invention can allocate a plurality of jumping points (and the number of the jumping points and the value of the jumping points) corresponding to different resources to be measured to the state machine through the JTAG interface, namely, for the resources to be measured comprising different numbers of the jumping points and the value of the jumping points, the number of the jumping points and the value of the jumping points on the original state machine can be directly modified, the number of the jumping points and the value of the jumping points suitable for the new resources to be measured can be obtained, and the terminal equipment can realize the allocation of the state machine and unify the state jump design of the state machine by only modifying the number of the jumping points and the value of the jumping points through the JTAG interface. The state jump of the state machine can be configured on the state machine through the JTAG interface by a plurality of jump points corresponding to different resources to be tested, and the configuration of the number of the jump points and the jump point value can be realized through external configuration, thereby being convenient for test and debugging and configuring different test scenes. The invention unifies the resource testing flow framework to be tested of the FPGA chip, and is convenient for engineering writing, transplanting and maintenance.
Based on the same inventive concept, the embodiment of the invention also provides a testing device of the FPGA chip as an implementation of the testing method of the FPGA chip. Fig. 4 is a first structural diagram of an apparatus according to an embodiment of the present invention, and referring to fig. 4, the apparatus may include:
an obtaining module 401, configured to obtain preset configuration information of the test device when receiving the test request;
a judging module 402, configured to judge whether the preset configuration information obtained by the obtaining module 401 is applicable to the resource to be tested, where the preset configuration information includes a preset number of jumping points and a preset number of jumping points;
the operation module 403 is configured to operate the test module of the FPGA chip according to the preset jump point number and the preset jump point value if the preset configuration information determined by the determination module 402 is suitable for the resource to be tested, so as to obtain a final test result, where the final test result is used to indicate whether the resource to be tested is correct;
and a modifying module 404, configured to modify the preset jump point number and the preset jump point value into a target jump point number and a target jump point value if the preset configuration information determined by the determining module 402 is not suitable for the resource to be tested, and operate the testing module of the FPGA chip according to the target jump point number and the target jump point value, so as to obtain a final testing result.
The present invention further provides another embodiment of the apparatus on the basis of fig. 4, referring to fig. 5, fig. 5 is a second structural diagram of the apparatus in the embodiment of the present invention, where the apparatus may include:
the judging module 402 includes:
a searching unit 4021, configured to search, in a corresponding relation table of the to-be-detected resource and target configuration information, the target configuration information corresponding to the to-be-detected resource;
a judging unit 4022 configured to judge whether the preset configuration information is the same as the target configuration information found by the finding unit 4021;
a first determining unit 4023, configured to determine that the preset configuration information is applicable to the resource to be tested if the preset configuration information determined by the determining unit 4022 is the same as the target configuration information;
the second determining unit 4024 is configured to determine that the preset configuration information is not suitable for the resource to be tested if the preset configuration information determined by the determining unit 4022 is different from the target configuration information.
Further, the target configuration information includes the target number of hops and the target number of hops, and the modifying module 404 includes:
a first replacing unit 4041 for replacing the preset number of jumping points with the target number of jumping points and replacing the preset number of jumping points with the target number of jumping points when the preset number of jumping points is not the same as the target number of jumping points;
A second replacing unit 4042, configured to replace the preset jumping point value with the target jumping point value when the preset jumping point number is the same as the target jumping point number and the preset jumping point value is not the same as the target jumping point value.
Further, the apparatus further comprises:
and an output unit 4043, configured to, when the preset number of jumping points is the same as the target number of jumping points and the preset number of jumping points is different from the target number of jumping points, replace the preset number of jumping points with the target number of jumping points, and then replace the target number of jumping points and the target number of jumping points by the first replacing unit 4041, or replace the target number of jumping points by the second replacing unit 4042, output the target number of jumping points to the test device through a joint test workgroup JTAG interface in the FPGA chip.
Further, the test module includes an excitation module and a resource to be tested, and the modification module 404 includes:
an acquisition unit 4044 for acquiring a counter value in the test apparatus;
a first operation unit 4045 configured to operate the test apparatus to output a target level signal when the counter value acquired by the acquisition unit 4044 is the same as a first target jump point value;
An opening unit 4046, configured to open the excitation module and the resource to be tested by using the target level signal operated by the first operation unit 4045;
a second operation unit 4047, configured to operate the excitation module started by the starting unit 4046, so that the excitation module outputs the test excitation data when the counter value is the same as the second target jump point value;
a third operation unit 4048, configured to operate the resource to be tested opened by the opening unit 4046, so that the resource to be tested performs a logic operation according to the test excitation data operated by the second operation unit 4047, to obtain operation data;
and a comparison unit 4049, configured to compare the operation data executed by the third execution unit 4048 with preset data, so as to output the final test result when the counter value is the same as the third target jump point value.
Further, the second operation unit 4047 includes:
a flushing subunit 40471, configured to flush initial data of the excitation module and generate a flushed instruction;
a transmitting subunit 40472, configured to transmit the cleared instruction generated by the clearing subunit 40471 to the excitation module, so that the excitation module, when receiving the cleared instruction, converts the target level signal into a preset level signal, and outputs the test excitation data when the counter value is the same as the second target jump point value.
Based on the same inventive concept, the embodiment of the invention also provides electronic equipment. Fig. 6 is a block diagram of an electronic device in an embodiment of the present invention, and referring to fig. 6, the electronic device 60 may include: at least one processor 601; and at least one memory 602, bus 603 connected to the processor 601; wherein, the processor 601 and the memory 602 complete communication with each other through the bus 603; the processor 601 is configured to invoke the program instructions in the memory 602 to perform the final test method of the FPGA chip in one or more embodiments described above.
It should be noted here that: the description of the final test device embodiment of the FPGA chip above is similar to that of the method embodiment described above, with similar benefits as the method embodiment. For technical details not disclosed in the embodiment of the final test device for FPGA chips of the embodiment of the present invention, please refer to the description of the method embodiment of the present invention for understanding.
Based on the same inventive concept, the embodiments of the present invention also provide a computer readable storage medium, where the computer readable storage medium includes a stored program, where the program controls a device where the storage medium is located to perform the method in one or more embodiments.
It should be noted here that: the description of the computer-readable storage medium embodiments above is similar to that of the method embodiments described above, with similar benefits as the method embodiments. For technical details not disclosed in embodiments of the computer-readable storage medium of embodiments of the present invention, please refer to the description of method embodiments of the present invention.
The foregoing is merely illustrative embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present invention, and the invention should be covered. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. A final test method of an FPGA chip, the method comprising:
when a test request is received, acquiring preset configuration information of test equipment;
judging whether the preset configuration information is suitable for the resource to be tested or not, wherein the preset configuration information comprises a preset jumping point number and a preset jumping point value;
if so, operating a test module of the FPGA chip according to the preset jump point number and the preset jump point value to obtain a final test result, wherein the final test result is used for indicating whether the resource to be tested is correct or not;
And if not, modifying the preset jumping point number and the preset jumping point value into a target jumping point number and a target jumping point value, and operating a test module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final test result.
2. The method of claim 1, wherein determining whether the configuration information is applicable to the resource under test comprises:
searching the target configuration information corresponding to the resource to be detected in a corresponding relation table of the resource to be detected and the target configuration information;
judging whether the preset configuration information is the same as the target configuration information;
if the preset configuration information is the same, determining that the preset configuration information is applicable to the resource to be tested;
if the preset configuration information is different, determining that the preset configuration information is not suitable for the resource to be tested.
3. The method of claim 1, wherein modifying the preset number of jumping points and the preset number of jumping points to a target number of jumping points and a target number of jumping points, comprises:
when the preset jumping point number is different from the target jumping point number, replacing the preset jumping point number with the target jumping point number, and replacing the preset jumping point value with the target jumping point value;
And when the preset jumping point number is the same as the target jumping point number and the preset jumping point value is different from the target jumping point value, replacing the preset jumping point value with the target jumping point value.
4. The method of claim 3, wherein after replacing the preset jumping point value with the target jumping point value when the preset number of jumping points is the same as the target jumping point number and the preset jumping point value is different from the target jumping point value, the method further comprises:
outputting the replaced target jumping point number and the target jumping point value or the replaced target jumping point value to the testing equipment through a joint testing working group JTAG interface in the FPGA chip.
5. The method of claim 1, wherein the test module comprises an excitation module and a resource to be tested, and wherein the running the test module of the FPGA chip according to the target jump point number and the target jump point value obtains a final test result, including:
acquiring a counter value in the test equipment;
When the counter value is the same as the first target jump point value, operating the test equipment to output a target level signal;
starting the excitation module and the resource to be detected by utilizing the target level signal;
operating the excitation module to output test excitation data when the counter value is the same as a second target trip point value;
operating the resource to be tested so as to enable the resource to be tested to perform logic operation according to the test excitation data to obtain operation data;
and comparing the operation data with preset data to output the final test result when the counter value is the same as the third target jumping-point value.
6. The method of claim 5, wherein the operating the incentive module to cause the counter value to be the same as a second target trip point value, the incentive module outputting test incentive data comprises:
clearing initial data of the excitation module and generating cleared instructions;
and sending the cleared instruction to the excitation module, so that the excitation module converts the target level signal into a preset level signal when receiving the cleared instruction, and outputs the test excitation data when the counter value is the same as the second target jumping point value.
7. The method of claim 1, wherein the resource under test comprises a look-up table, a digital signal processor.
8. A final test device for an FPGA chip, said device comprising:
the acquisition module is used for acquiring preset configuration information of the test equipment when receiving the test request;
the judging module is used for judging whether the preset configuration information is suitable for the resources to be tested or not, wherein the preset configuration information comprises the number of preset jumping points and the value of the preset jumping points;
the running module is used for running the testing module of the FPGA chip according to the preset jump point number and the preset jump point value if applicable to obtain a final testing result, wherein the final testing result is used for indicating whether the resource to be tested is correct or not;
and the modification module is used for modifying the preset jumping point number and the preset jumping point value into a target jumping point number and a target jumping point value if the preset jumping point number and the target jumping point value are not applicable, and operating the test module of the FPGA chip according to the target jumping point number and the target jumping point value to obtain a final test result.
9. An electronic device, the electronic device comprising:
At least one processor;
and at least one memory, bus connected to the processor;
the processor and the memory complete communication with each other through the bus; the processor is configured to invoke program instructions in the memory to perform the final test method of the FPGA chip of any of claims 1-7.
10. A computer readable storage medium, characterized in that the storage medium comprises a stored program, wherein the program, when run, controls a device in which the storage medium is located to perform the final test method of the FPGA chip according to any of claims 1 to 7.
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