CN103796009A - FPGA quality diagnostic test system - Google Patents
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Abstract
An FPGA quality diagnostic test system comprises a hardware circuit and FPGA software logic. The hardware circuit comprises a testing FPGA, a tested FPGA, a PROM, an SRAM, a power supply and configuration circuit, a tested FPGA temperature obtaining circuit, an IO port circuit between the FPGAs, an RS232 port circuit and an SAM output test circuit. The system overcomes the defect that in the prior art, the test coverage of FPGA internal resources is insufficient and is good in real-time performance, high in universality, easy to operation and capable of meeting requirements for an FPGA chip in the test process of an astronautic camera video electronic system.
Description
Technical field
The invention belongs to space remote sensor technical field, relate to a kind of FPGA quality diagnosis test macro that is applied to camera space video electronic system.
Background technology
Fpga chip is the Primary Component in space remote sensing camera video electronic system.In space remote sensing camera video electronic system, ccd sensor receives the light signal from optical system, complete the conversion of light signal to the signal of telecommunication, the signal of telecommunication after conversion is converted to digital signal after the operations such as signal processor correlated-double-sampling, A/D conversion, send fpga chip digital signal processor to, picture is processed and be output into synthetic, the image that complete multiway images signal.Wherein fpga chip is the control core of system, for generation of ccd sensor control sequential, produce signal processor control sequential, generation multiway images data are synthetic, image is processed and number passes sequential, and space remote sensing camera video electronic system theory diagram as shown in Figure 1.Because the environmental requirement of space remote sensing camera applications is higher, in the development process of video electronic system, need to carry out multi-functional and performance test to system control core fpga chip, likely there is the situation of the discontented pedal system requirement of part fpga chip, when causing economic loss, also affect the test job of subsequent video treatment circuit, and then affected the R&D cycle of camera entirety.
Therefore develop a kind of FPGA quality diagnosis test macro that is applied to camera space video electronic system, it is necessary before fpga chip falls weldering, doing exhaustive diagnosis test.
Summary of the invention
The technology of the present invention is dealt with problems: overcome prior art to the low deficiency of FPGA internal resource test coverage, a kind of FPGA quality diagnosis test macro is provided, real-time is good, highly versatile, simple to operate, can be deep into register stage test, not only can realize the quality screening to not using FPGA, also contribute to the problem place of location generation permanent fault FPGA, to meet the requirement to fpga chip in camera space video electronic system testing process.
A kind of FPGA quality diagnosis test macro, is characterized in that comprising: IO interface circuit, a RS232 interface circuit, the 2nd RS232 interface circuit and SMA output test circuit between test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, FPGA; PROM is for storing test FPGA configuration data, tested FPGA configuration data and the mask data for retaking of a year or grade functional verification; SRAM is for the tested FPGA configuration data of on-line storage and mask data; After system power-up, test FPGA completes after configuration, reads tested FPGA configuration data and mask data, and dumps in external SRAM, for tested FPGA configuration and retaking of a year or grade functional verification from PROM; Power supply and configuration circuit provide the needed power supply of normal work and configuring chip for testing FPGA; Temperature acquisition cuicuit is used for extracting tested FPGA working temperature; IO interface circuit is realized test FPGA and is communicated by letter with tested FPGA; SMA output test circuit is used for verifying tested FPGA global clock network checking, IO output level type and driving force test; PC is communicated by letter with test FPGA by a RS232 interface, to obtain test FPGA operating state; Test FPGA communicates by letter with tested FPGA by the 2nd RS232 interface, obtains tested FPGA operating state;
The RS232 instruction that test FPGA comes according to host computer is carried out tested FPGA configuration and retaking of a year or grade functional verification by SelectMAP parallel interface; Complete tested FPGA and realize the functional test of DSP48s multiplier unit; Complete tested FPGA register stage translocation examination; Complete the inner BRAM functional verification of tested FPGA; Obtain tested FPGA working temperature by temperature test circuit;
The RS232 instruction that tested FPGA comes according to host computer, completes the functional test of all inner DSP48s multiplier units, and to test FPGA feedback test result; Complete global clock network checking; Complete IO output level type and driving force test; Complete temperature sensing unit functional verification.
Described SMA output test circuit comprises 24 road FPGA clock performance test circuits, 24 IO level type test circuit He32 road, road IO driving force test circuits.
Described test FPGA is implemented as follows:
(1) after system power-up, test FPGA is configured from exterior arrangement PROM, after having configured, read tested FPGA configuration data, comparison data and mask data from exterior storage PROM, and tested FPGA configuration data, comparison data are stored into respectively in outside different SRAM with mask data, then enter wait instruction state.
(2) test FPGA receives after instruction, and instruction is carried out to decipher, the corresponding test of according to the instruction of specifically receiving, complete (3)～(7) process.
(3) if test FPGA receives tested FPGA configuration and retaking of a year or grade functional verification instruction, first test FPGA reads tested FPGA configuration data in SRAM, and by SelectMAP parallel interface, tested FPGA is configured; After having configured, tested FPGA enters operating state; After at least 3 seconds, test FPGA carries out retaking of a year or grade by SelectMAP parallel interface to tested FPGA, and by retaking of a year or grade data and SRAM, deposit compare data, mask data compares in real time, add up discrepant bit, and statistic is sent to PC by a RS232 interface.
(4) if test FPGA receives the inner DSP48s multiplier unit of tested FPGA functional test instruction, test FPGA is forwarded to tested FPGA by the 2nd RS232 interface by instruction, and receive the test result of the inner DSP48s multiplier unit of tested FPGA by the 2nd RS232 interface, by a RS232 interface feedback test result to PC.
(5) if test FPGA receives the inner BRAM functional verification of tested FPGA instruction, test FPGA writes test data by IO interface to tested FPGA, and pass through IO interface from the inner BRAM read test of tested FPGA data, add up discrepant bit, and statistic is sent to PC by a RS232 interface.
(6) obtain the instruction of tested FPGA working temperature if test FPGA receives, test FPGA obtains tested FPGA working temperature by temperature test circuit, and Temperature numerical is sent to PC by a RS232 interface.
(7) if test FPGA receives the test instruction of tested FPGA register stage connection, test FPGA is configured tested FPGA by SelectMAP parallel interface, makes tested FPGA be operated in register cascade state; Test FPGA writes test data by IO interface to tested FPGA, and passes through IO interface from tested FPGA read test data, adds up discrepant bit, and statistic is sent to PC by a RS232 interface.
(8) test FPGA completes in (3)～(7) after a content measurement, enters wait instruction state, then implementation (2).
Described tested FPGA is implemented as follows:
Tested FPGA is configured to two kinds of operating states, is configured to self-test state implementation procedure:
(1), after system power-up, tested FPGA is configured by SelectMAP parallel interface by testing FPGA.
(2), after having configured, tested FPGA carries out the functional test of inner DSP48s multiplier unit, after having tested, and logging test results.
(3) tested FPGA carries out global clock network checking, tested FPGA exports master clock by IO, master clock 2 frequency-dividing clocks and master clock 10 frequency-dividing clocks, every kind of clock all adopts single-ended and difference output, uses frequency values, duty ratio and the jitter amplitude of every kind of clock of oscillograph recording.
(4) tested FPGA carries out the test of IO output level type and driving force, and tested FPGA exports 3 kinds of level types by IO, records respectively the magnitude of voltage of every kind of level type low and high level, and the driving force of load while being 10K Ω.
(5) tested FPGA completes after the test of (2)～(4), enter wait instruction state, tested FPGA receives instruction from the 2nd RS232, instruction is carried out to decipher, if instruction is for obtaining the inner DSP48s multiplier unit of tested FPGA functional verification result, tested FPGA is by the 2nd RS232 feedback test result, and any operation is not done in other instructions, continues to enter wait instruction state.
When tested FPGA is configured to register cascade state, do not carry out any operation, passive reception test FPGA controls.
The present invention's advantage is compared with prior art:
(1) the present invention overcomes prior art to the low deficiency of FPGA internal resource test coverage;
(2) the present invention can be at FPGA for the quality diagnosis of carrying out to FPGA before space remote sensing camera video electronic system, reliability to FPGA is tested, reduce fpga chip in space remote sensing camera video electronic system test process and occurred the risk that function and performance do not meet the demands, improved the feasibility of fpga chip quality diagnosis test.
(3) the present invention can carry out register stage test to FPGA, real-time is good, highly versatile, simple to operate, not only can realize the quality screening to not using FPGA, also contribute to the problem place of location generation permanent fault FPGA, to meet the demand to fpga chip failure diagnosis in camera space video electronic system testing process.
(4) the present invention can and change FPGA Test bench by change FPGA software, the FPGA of diagnostic test different model, and highly versatile, can meet the demand of space remote sensing camera video electronic system to FPGA.
Accompanying drawing explanation
Fig. 1 remote sensing camera video electronic system principle diagram;
Fig. 2 fpga chip quality diagnosis of the present invention test system hardware block diagram;
In Fig. 3 the present invention, test the realization flow figure of FPGA;
Tested FPGA specific functional units DPS48s test philosophy block diagram in Fig. 4 the present invention;
Tested FPGA register cascade theory diagram in Fig. 5 the present invention;
The realization flow figure of tested FPGA in Fig. 6 the present invention.
Embodiment
For meeting space remote sensing camera video electronic system to fpga chip quality diagnosis test request, as shown in Figure 2, the present invention includes test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, IO interface circuit between FPGA, the one RS232 interface circuit, the 2nd RS232 interface circuit and SMA output test circuit, PROM is used for storing test FPGA configuration data, tested FPGA configuration data and for the comparison data of retaking of a year or grade functional verification, mask data, SRAM is for the tested FPGA configuration data of on-line storage, comparison data and mask data.The present invention is in concrete enforcement, and test FPGA selects the Virtex V Series FPGA XC5FXL130T-1FF1738 of Xilinx company, and tested FPGA selects the Virtex IV Series FPGA XC4VSX55-10FF1148 of Xilinx company.
First carry out corresponding initialization operation, after powering on, test FPGA and automatically complete program loading and configuration.Test FPGA is configured from exterior arrangement PROM, after having configured, read tested FPGA configuration data, comparison data and mask data from exterior storage PROM, and tested FPGA configuration data, comparison data are stored into respectively in outside different SRAM with mask data.The signal input of test FPGA cycle detection the one RS232 interface circuit, if receive tested FPGA configuration and retaking of a year or grade functional verification instruction, the inner DSP48s multiplier unit of tested FPGA functional test instruction, the inner BRAM functional verification of tested FPGA instruction, obtain the instruction of tested FPGA working temperature or the test instruction of tested FPGA register stage connection from a RS232 interface, test FPGA carries out corresponding operation, and sends detecting information by a RS232 interface circuit to host computer.The configuration of tested FPGA and operating state are determined by test FPGA.
As shown in Figure 3, be a kind of FPGA quality diagnosis of the present invention test system and test FPGA workflow diagram.After system powers on, test FPGA is configured from exterior arrangement PROM, after having configured, read tested FPGA configuration data, comparison data and mask data from exterior storage PROM, and tested FPGA configuration data, comparison data are stored into respectively in outside different SRAM with mask data, then enter wait instruction state.Test FPGA cycle detection the one RS232 interface circuit has no signal input.If no signal input, continues cycle detection; If there is signal input, input signal is decoded, obtain the corresponding control command that host computer sends from a RS232 interface circuit.After control order finishes receiving, test FPGA judges instruction:
Test FPGA receives tested FPGA configuration and retaking of a year or grade functional verification instruction, and first test FPGA reads tested FPGA configuration data in SRAM, and by SelectMAP parallel interface, tested FPGA is configured; After having configured, tested FPGA enters operating state; After at least 3 seconds, test FPGA carries out retaking of a year or grade by SelectMAP parallel interface to tested FPGA, and by retaking of a year or grade data and SRAM, deposit compare data, mask data compares in real time, add up discrepant bit, and statistic is sent to PC by a RS232 interface.
Test FPGA receives the inner DSP48s multiplier unit of tested FPGA functional test instruction, test FPGA is forwarded to tested FPGA by the 2nd RS232 interface by instruction, and receive the test result of the inner DSP48s multiplier unit of tested FPGA by the 2nd RS232 interface, by a RS232 interface feedback test result to PC.The functional test of the inner DSP48s multiplier unit of tested FPGA as shown in Figure 4, main by DSP48s being inputted to different test datas, obtain after corresponding result of calculation, by result of calculation be pre-stored in the correct value comparison in register group, compare and verify by result.
Test FPGA receives the inner BRAM functional verification of tested FPGA instruction, test FPGA writes test data by IO interface to tested FPGA, and pass through IO interface from the inner BRAM read test of tested FPGA data, add up discrepant bit, and statistic is sent to PC by a RS232 interface.Mentality of designing, for all tested FPGA inner BRAM are configured to a memory module, carries out read-write operation then to the interface opening of this memory module test FPGA, completes its inner BRAM functional memory cell test.Take the tested Virtex IV of Xilinx company Series FPGA XC4VSX55-10FF1148 as example, FPGA developing instrument ISE by Xilinx can obtain memory module port definition: need altogether 82 Pin interfaces, wherein 2 clocks, 80 common IO, read and write data independent with read/write address, wherein data bit width 18, address bit wide 19, the read-write degree of depth 327680, can make inner 320 the 18KbitBRAM memory cell of tested FPGA all use like this.Main by inner BRAM is write to different test datas, and then reading out data, compare and verify by result.
Test FPGA receives and obtains the instruction of tested FPGA working temperature, tests FPGA and obtains tested FPGA working temperature by temperature test circuit, and Temperature numerical is sent to PC by a RS232 interface.
Test FPGA receives the test instruction of tested FPGA register stage connection, and test FPGA is configured tested FPGA by SelectMAP parallel interface, makes tested FPGA be operated in register cascade state; Test FPGA writes test data by IO interface to tested FPGA, and passes through IO interface from tested FPGA read test data, adds up discrepant bit, and statistic is sent to PC by a RS232 interface.As shown in Figure 5, after tested FPGA has configured, internal register is configured to link, makes register cascade as much as possible in tested FPGA register stage translocation examination test.Take the tested Virtex IV of Xilinx company Series FPGA XC4VSX55-10FF1148 as example, situation about wherein realizing is that D0:D7 is that 8bit is wide, and N is that 7, M is 5994 grades, and tested FPGA register utilization rate reaches 97%.Main by chain of registers being write to different test datas, and then reading out data, compare and verify by result.
As shown in Figure 6, be the tested FPGA workflow diagram of a kind of FPGA quality diagnosis test macro of the present invention.Tested FPGA is configured to two kinds of operating states, is configured to self-test state implementation procedure: after system power-up, tested FPGA is configured by SelectMAP parallel interface by testing FPGA.After having configured, tested FPGA carries out the functional test of inner DSP48s multiplier unit, after having tested, and logging test results.Tested FPGA carries out global clock network checking, tested FPGA exports master clock by IO, master clock 2 frequency-dividing clocks and master clock 10 frequency-dividing clocks, every kind of clock all adopts single-ended and difference output, uses frequency values, duty ratio and the jitter amplitude of every kind of clock of oscillograph recording when debugging.Tested FPGA carries out the test of IO output level type and driving force, and tested FPGA exports 3 kinds of level types by IO, records respectively the magnitude of voltage of every kind of level type low and high level, and the driving force of load while being 10K Ω.Tested FPGA completes after above-mentioned test, enter wait instruction state, tested FPGA receives instruction from the 2nd RS232, instruction is carried out to decipher, if instruction is for obtaining the inner DSP48s multiplier unit of tested FPGA functional verification result, tested FPGA is by the 2nd RS232 feedback test result, and any operation is not done in other instructions, continues to enter wait instruction state.
When tested FPGA is configured to register cascade state, do not carry out any operation, passive reception test FPGA controls.
Claims (4)
1. a FPGA quality diagnosis test macro, is characterized in that comprising: IO interface circuit, a RS232 interface circuit, the 2nd RS232 interface circuit and SMA output test circuit between test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, FPGA; PROM is for storing test FPGA configuration data, tested FPGA configuration data and comparison data, mask data for retaking of a year or grade functional verification; SRAM is for the tested FPGA configuration data of on-line storage, comparison data and mask data; After system power-up, test FPGA completes after configuration, reads tested FPGA configuration data, comparison data and mask data, and dumps in external SRAM, for tested FPGA configuration and retaking of a year or grade functional verification from PROM; Power supply and configuration circuit provide the needed power supply of normal work and configuring chip for testing FPGA; Temperature acquisition cuicuit is used for extracting tested FPGA working temperature; IO interface circuit is realized test FPGA and is communicated by letter with tested FPGA; SMA output test circuit is used for verifying tested FPGA global clock network checking, IO output level type and driving force test; PC is communicated by letter with test FPGA by a RS232 interface, to obtain test FPGA operating state; Test FPGA communicates by letter with tested FPGA by the 2nd RS232 interface, obtains tested FPGA operating state;
The RS232 control command that test FPGA comes according to host computer is carried out tested FPGA configuration and retaking of a year or grade functional verification by SelectMAP parallel interface; Complete tested FPGA and realize the functional test of DSP48s multiplier unit; Complete tested FPGA register stage translocation examination; Complete the inner BRAM functional verification of tested FPGA; Obtain tested FPGA working temperature by temperature test circuit;
The RS232 control command that tested FPGA comes according to test FPGA, completes the functional test of all inner DSP48s multiplier units, and to test FPGA feedback test result; Complete global clock network functional verification; Complete IO output level type and driving force test.
2. FPGA quality diagnosis test macro according to claim 1, is characterized in that: described SMA output test circuit comprises 24 road FPGA clock performance test circuits, 24 IO level type test circuit He32 road, road IO driving force test circuits.
3. FPGA quality diagnosis test macro according to claim 1, is characterized in that: described test FPGA is implemented as follows:
(1) after system power-up; test FPGA is configured from exterior arrangement PROM; after having configured; read tested FPGA configuration data, comparison data and mask data from outside PROM; and tested FPGA configuration data, comparison data are stored into respectively in outside different SRAM with mask data, then enter wait instruction state;
(2) test FPGA receives after control command, and instruction is carried out to decipher, the corresponding test of according to the instruction of specifically receiving, complete (3)～(7) process;
(3) if test FPGA receives tested FPGA configuration and retaking of a year or grade functional verification instruction, first test FPGA reads tested FPGA configuration data in SRAM, and by SelectMAP parallel interface, tested FPGA is configured; After having configured, tested FPGA enters operating state; After 3 seconds, test FPGA carries out retaking of a year or grade by SelectMAP parallel interface to tested FPGA, and by retaking of a year or grade data and SRAM, deposit compare data, mask data compares in real time, adds up discrepant bit, and statistic is sent to PC by a RS232 interface;
(4) if test FPGA receives the inner DSP48s multiplier unit of tested FPGA functional test instruction, test FPGA is forwarded to tested FPGA by the 2nd RS232 interface by instruction, and receive the test result of the inner DSP48s multiplier unit of tested FPGA by the 2nd RS232 interface, by a RS232 interface feedback test result to PC;
(5) if test FPGA receives the inner BRAM functional verification of tested FPGA instruction, test FPGA writes test data by IO interface to tested FPGA, and pass through IO interface from the inner BRAM read test of tested FPGA data, add up discrepant bit, and statistic is sent to PC by a RS232 interface;
(6) obtain the instruction of tested FPGA working temperature if test FPGA receives, test FPGA obtains tested FPGA working temperature by temperature test circuit, and Temperature numerical is sent to PC by a RS232 interface;
(7) if test FPGA receives the test instruction of tested FPGA register stage connection, test FPGA is configured tested FPGA by SelectMAP parallel interface, makes tested FPGA be operated in register cascade state; Test FPGA writes test data by IO interface to tested FPGA, and passes through IO interface from tested FPGA read test data, adds up discrepant bit, and statistic is sent to PC by a RS232 interface;
(8) test FPGA completes in (3)～(7) after a content measurement, enters wait instruction state, then implementation (2).
4. FPGA quality diagnosis test macro according to claim 1, is characterized in that: described tested FPGA is implemented as follows:
(1), after system power-up, tested FPGA is configured by SelectMAP parallel interface by testing FPGA;
(2), after having configured, tested FPGA carries out the functional test of inner DSP48s multiplier unit, after having tested, and logging test results;
(3) tested FPGA carries out global clock network checking, tested FPGA exports master clock by IO, master clock 2 frequency-dividing clocks and master clock 10 frequency-dividing clocks, every kind of clock all adopts single-ended and difference output, uses frequency values, duty ratio and the jitter amplitude of every kind of clock of oscillograph recording;
(4) tested FPGA carries out the test of IO output level type and driving force, and tested FPGA exports 3 kinds of level types by IO, records respectively the magnitude of voltage of every kind of level type low and high level, and the driving force of load while being 10K Ω;
(5) tested FPGA completes after the test of (2)～(4), enter wait instruction state, tested FPGA receives instruction from the 2nd RS232 interface, instruction is carried out to decipher, if instruction is for obtaining the inner DSP48s multiplier unit of tested FPGA functional verification result, tested FPGA is by the 2nd RS232 interface feedback test result, and any operation is not done in other instructions, continues to enter wait instruction state.
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