CN102332307A - Test system and method for single event effect of SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array) - Google Patents
Test system and method for single event effect of SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array) Download PDFInfo
- Publication number
- CN102332307A CN102332307A CN201110214108A CN201110214108A CN102332307A CN 102332307 A CN102332307 A CN 102332307A CN 201110214108 A CN201110214108 A CN 201110214108A CN 201110214108 A CN201110214108 A CN 201110214108A CN 102332307 A CN102332307 A CN 102332307A
- Authority
- CN
- China
- Prior art keywords
- fpga
- configuration
- test
- tested
- particle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a test system and method for a single event effect of an SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array). The test system comprises a single chip microcomputer processor, an RS232 interface circuit, a USB (Universal Serial Bus) interface circuit, a test FPGA and a storage unit. The test system and method can be used for fault injection tests of a configuration memory and a BRAM (Battery Random Access Memory) of the SRAM type FPGA, and single event function interrupting detection, single event locking detection and single event turning detection including single event turning detection for a configuration storage region, the BRAM and a trigger of the SRAM type FPGA are realized. The invention has the advantages of simplicity in operation, entirety in detection, high accuracy, good real-time property and strong universality.
Description
Technical field
The present invention relates to a kind of SRAM type FPGA single particle effect pilot system and method.
Background technology
FPGA is reconfigurable new device, in the satellite development, uses FPGA, can accelerate the Development Schedule of satellite, shortens the lead time, improves the performance of satellite simultaneously.Satellite is operated in the space radiation environment, and radiation effect can cause FPGA performance degradation even inefficacy, and the FPGA performance degradation that the single-particle radiation effect causes is particularly evident.Before satellite uses FPGA, must carry out single particle effect to FPGA and detect, through test, assessment single particle effect susceptibility is selected for use device and system to carry out the radiation hardening design for model foundation is provided.
Domestic single particle experiment mainly concentrates on the fixed function device of each quasi-tradition; Like microprocessor, storer, DLC(digital logic circuit), A/D, D/A converter etc.; And FPGA has the difference of essence with the device of former studies on the 26S Proteasome Structure and Function principle; Function and the interconnector in system, realized are determined by configuration file; And therefore configuration file stores can not carry out the single-particle simulation test with its device of regarding the fixed logic function as on the detection principle in the responsive SRAM district of single-particle, detects but need to carry out single particle effect to the brand-new detection system of its design feature design.
The unit that the at present domestic SRAM of being engaged in type FPGA single particle effect detects research is mainly the National University of Defense Technology.The detection method of single-particle inversion and device in the field programmable gate array of the National University of Defense technology only to the detection of SRAM type FPGA single-particle inversion effect, adopt retaking of a year or grade configuration frame and original configuration frame to carry out the detection mode of direct byte comparison.Because there is the data redundancy of some in the retaking of a year or grade of SRAM type FPGA configuration frame, adopt retaking of a year or grade configuration frame and original configuration frame to carry out the detection mode that direct byte is compared, do not get rid of the redundant data of retaking of a year or grade configuration frame, can influence detection efficiency; In addition, the single-particle function interrupts the meeting of single-particle inversion result precision is caused certain influence, the single detection mode that adopts retaking of a year or grade configuration frame and original configuration frame to carry out direct byte comparison, and the single-particle inversion testing result that obtains might be inaccurate.
SRAM type FPGA single particle effect fault is injected and is mainly used under the non-radiation environment, and the single-particle inversion effect of simulation SRAM type FPGA configuration store district and BRAM is carried out the influence research of single-particle inversion effect.The unit that the at present domestic SRAM of being engaged in type FPGA single particle effect fault is injected research is mainly Shanghai Engineering Center for Microsatellites and Beijing Times Minxin Technology Co., Ltd.The automatic intelligent single-particle fault injector of Shanghai Engineering Center for Microsatellites mainly adopts the software emulation mode to carry out, and no longer the actual hardware platform is carried out experimental study.The fault injection system of Beijing Times Minxin Technology Co., Ltd and method thereof need be through making the trouble unit module, and the gate leve HDL code of modifying target circuit generates faulty circuit, and it is higher to operate required professional ability, and process is complicated.
The report of being engaged in the single particle effect experimental study abroad mainly contains U.S. XILINX company and European SAAB testing laboratory; U.S. XILINX company is the production design side of FPGA; The core technology of such device on top of; Adopted custom-designed check-out console, upper computer detection software and IP kernel, the single particle effect that can accomplish more all sidedly tested FPGA internal resource detects and the fault injection, but the FPGA internal resource detection technique of test application and unexposed; Domestic can't the acquisition of a large amount of technology; And its detection method is that tested FPGA is configured to the fixed logic function, device universal internal resource is detected through special software by outer computer, and its detection scheme is not directed against the application specific logic of device; Europe SAAB testing laboratory cooperates with Xilinx company, has adopted custom-designed check-out console, upper computer detection software and IP kernel to carry out single particle effect detection and fault injection, and its detection technique details is unexposed, domestic can't the acquisition.
Summary of the invention
The technical matters that the present invention solves is: overcome the deficiency of prior art, provide simple to operate, detect comprehensively, accuracy is high, real-time good, the SRAM type FPGA single particle effect pilot system and the method for highly versatile.
Technical solution of the present invention is: SRAM type FPGA single particle effect pilot system comprises: processor of single chip computer, RS232 interface, USB interface, test FPGA and storage unit, wherein:
Processor of single chip computer: receive outside configuration data and the control command that transmits, and data and order are delivered to test FPGA; According to the external control order, it is configuration operation state, refresh operation state, fault injection state, single-particle inversion and function break detection mode of operation and trigger upset detecting operation state that test FPGA is set; FPGA receives control command feedback signal and testing result from test, and exports to the outside;
Test FPGA: the order according to processor of single chip computer transmits is carried out initialization to storage unit, receives the configuration data that processor of single chip computer transmits, and deposits to storage unit; The order of transmitting according to processor of single chip computer gets into corresponding mode of operation, and said mode of operation comprises configuration operation state, refresh operation state, fault injection state, single-particle inversion and function break detection mode of operation and trigger upset detecting operation state; When the configuration operation state, test FPGA reads configuration data from storage unit, to the operation that is configured of tested FPGA, and to processor of single chip computer feedback configuration operating result; During the refresh operation state, to the operation that is configured of tested FPGA, and to processor of single chip computer feedback configuration operating result; When fault is injected state; After test FPGA receives the fault implant operation order of processor of single chip computer; So receive drop data information from host computer via USB interface, the series arrangement mouth through tested FPGA carries out the part reprovision to tested FPGA, in the configuration bit Write fault data of assigned address; Said part reprovision is only to make amendment to the segment of FPGA configuration file, thereby accomplish tested FPGA is carried out the fault injection; When single-particle inversion and function break detection mode of operation; From the current configuration data of tested FPGA retaking of a year or grade; The single-particle inversion that relatively carries out through with the original configuration data detects, and carries out single-particle function break detection through reading and writing tested FPGA configuration address register with detection DONE pin, when confirming that FPGA does not take place to have no progeny in the function; Send synch command and configuration data retaking of a year or grade order to tested FPGA successively; And detect the BUSY pin of tested FPGA, when the BUSY pin is invalid, the corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and memory stores is compared in real time; The statistics upset is total, and statistics is sent to processor of single chip computer; During trigger upset detecting operation state; Test FPGA at first refreshes the configuration data of tested FPGA; Guarantee that tested FPGA user logical link is communicated with, user's trigger value of reading tested FPGA then compares with the institute initialize; The statistics upset is total, and statistics is sent to processor of single chip computer;
Storage unit: be used to store the configuration data that the outside is transmitted;
RS232 interface: accomplish host computer to the processor of single chip computer transmitting control commands, and receive control command feedback or testing result from single-chip microcomputer;
USB interface: accomplish host computer and send tested FPGA original configuration data to processor of single chip computer.
The course of work of described processor of single chip computer is:
Processor of single chip computer at first carries out initialization operation, enters into cycling then; During cycling, the operation that next step need carry out is confirmed in the input of processor of single chip computer cycle detection RS232 interface signal; If processor of single chip computer is received configuration operation order, refresh operation order, fault injection order, single-particle inversion and function break detection operational order or the order of trigger upset detecting operation from the RS232 interface; Then the corresponding command is sent to test FPGA; After FPGA to be tested accomplishes corresponding operating; FPGA receives control command feedback signal or testing result from test, transmits to the outside through the RS232 interface.Processor of single chip computer gets into cycling again accomplishing all after dates of a command operation, waits for Next Command.
The course of work that described configuration data receives is:
Test FPGA at first carries out initialization operation, enters into cycling then; During cycling; The signal input of test FPGA cycle detection USB interface if test FPGA receives the configuration data download command from USB interface, then stops other operations; Receive the original configuration data of tested FPGA from USB interface continuously, and transfer to test FPGA and store.
The configuration operation process of described test FPGA is:
After receiving the configuration operation order of processor of single chip computer, enable configuration control pin CS, WRITE and the PROGRAM of tested FPGA, and guarantee that the PROGRAM signal keeps low level 300ns at least; Detect the INIT pin of tested FPGA output then; When the INIT pin is effective, reads configuration data and write tested FPGA, detect the BUSY pin of tested FPGA simultaneously, when the BUSY pin is invalid from the first address of config memory; Represent that these address configuration data have been written into tested FPGA; Cyclic address change with config memory repeats write operation, finishes until the whole configuration datas in the config memory are sent; Detect the DONE pin of tested FPGA output then, when the DONE pin is effective, represent the configuration successful of tested FPGA; After tested FPGA configuration successful, test FPGA begins user's trigger of tested FPGA is carried out initialization operation, and after initialization operation was accomplished, whole configuration operation was all over.
The refresh operation process of described test FPGA is:
After receiving the refresh operation order of processor of single chip computer; Read configuration data and write tested FPGA from the first address of config memory, detect the BUSY pin of tested FPGA simultaneously, when the BUSY pin is invalid; Represent that these address configuration data have been written into tested FPGA; Cyclic address change with config memory repeats write operation, finishes until the whole configuration datas in the config memory are sent.
SRAM type FPGA single particle effect test method is characterized in that comprising the fault injection; Single-particle inversion detects, and comprises that configuration store district, BRAM and trigger upset detect; Single-particle function break detection; Locking single particle detects one of four parts;
Wherein said fault filling method step is following:
(a) host computer is confirmed fault injection configuration bit position, and abort situation information is sent to processor of single chip computer;
(b) processor of single chip computer sends to test FPGA with abort situation information;
(c) test FPGA is according to the positional information that receives, and the series arrangement mouth through tested FPGA carries out the part reprovision to tested FPGA, and the configuration data of change corresponding configuration position is realized the fault injection;
Said single-particle inversion detects and single-particle function break detection merges completion, and performing step is following:
(1) selective radiation source;
(2) send initialization command by the outside, configuration data is delivered in the storage unit, accomplish initialization;
(3) after initialization finishes, send configuration order to processor of single chip computer, start test FPGA tested FPGA is configured operation by the outside;
(4) after configuration operation is accomplished, send sense command to processor of single chip computer, start the cycle detection operation of test FPGA by the outside;
(5) use radiation source to produce high energy particle and shine tested fpga chip surface;
(6) test FPGA detects configuration address register and the DONE pin of tested FPGA, judges whether tested FPGA the single-particle function takes place interrupt, and accomplishes the single-particle function interrupt test of tested FPGA;
(7) confirming that FPGA does not take place under the situation of single-particle function interruption; The configuration data of the tested FPGA of test FPGA retaking of a year or grade; The corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and memory stores is compared in real time; Add up configuration store district and BRAM upset sum respectively, and statistics is sent to processor of single chip computer;
(8) circulation execution in step (6)～(7) are until the high energy particle end of radiation;
(9) refresh the configuration data of tested FPGA, user's trigger value of reading tested FPGA compares with the institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer, accomplish the trigger function interrupt test;
Said locking single particle detection method performing step is following:
(A) selective radiation source;
(B) send initialization command by the outside, configuration data is delivered in the storage unit, accomplish initialization;
(C) after initialization finishes, send configuration order to processor of single chip computer, start test FPGA tested FPGA is configured operation by the outside;
(D) use radiation source to produce high energy particle and shine tested fpga chip surface;
(E) configuration data of the tested FPGA of periodic refreshing prevents that the working current when locking single particle does not take place tested FPGA is excessive;
(F) become big suddenly if find tested FPGA working current, surpass detection threshold, after the refresh configuration data, the basic no change of electric current judges that then locking single particle takes place tested FPGA.
Radiation source among said step (1), (A) is cyclotron or tandem accelerator, and the range of the high energy particle of its generation in silicon is greater than 30 μ m, and the LET value is greater than 30MeV.cm
2/ mg.
The condition of end of radiation is in the said step (8): the single-particle function takes place and interrupts in tested FPGA, and perhaps the fluence of radiation source irradiation particle reaches 9 * 10
4～10
5/ cm
2
The present invention's advantage compared with prior art is:
(1) the present invention is simple to operate.The existing fault method for implanting need be through making the trouble unit module, and the gate leve HDL code of modifying target circuit generates faulty circuit, and it is higher to operate required professional ability, and process is complicated.Fault filling method of the present invention only needs the specified fault position, just can accomplish fault through the part reprovision and inject, and is simple to operate.
(2) the present invention detects comprehensively.The single-particle inversion that can only detect configuration store district and BRAM that prior art has, the present invention can realize that the single-particle inversion of configuration store district, BRAM and trigger detects, single-particle function break detection, locking single particle detects, and detects comprehensively.
(3) single-particle inversion accuracy in detection of the present invention is high.Prior art directly with the difference position sum of retaking of a year or grade configuration data and original configuration data, as the single-particle inversion sum, is not considered the influence of single-particle function interruption to single-particle inversion testing result accuracy.The present invention assert final single-particle inversion testing result through taking all factors into consideration the testing result that single-particle inversion and single-particle function are interrupted, and accuracy is high.
(4) single-particle inversion detection real-time of the present invention is good.Some configuration data with retaking of a year or grade of prior art is stored as the retaking of a year or grade configuration file, compares through the non real-time of retaking of a year or grade configuration file and original configuration file and draws testing result; Some lets whole retaking of a year or grade configuration datas all participate in the comparison operation, and efficient is low, and real-time is poor.Single-particle inversion of the present invention detects the significance bit of directly extracting the retaking of a year or grade data and compares in real time, obtains the testing result of overturning, and gets rid of the influence of redundant data, and efficient is high, and real-time is good.
(5) configuration file that the present invention can be through any function of host computer remote download is realized any applied logic function of tested FPGA, highly versatile to tested FPGA; This Remote configuration function can be used for the FPGA single-particle simulation test on the space flight model, and the effective single-particle susceptibility of effect card concrete configuration function is for the know the real situation test and have practical significance in the rail failure analysis of practical applications single-particle.
Description of drawings
Fig. 1 is the theory diagram of SRAM type FPGA single particle effect pilot system of the present invention;
Fig. 2 is the workflow diagram of SRAM type FPGA single particle effect pilot system monolithic processor of the present invention;
Fig. 3 is configured the workflow diagram of operation to tested FPGA for SRAM type FPGA single particle effect pilot system test FPGA of the present invention;
Fig. 4 carries out the workflow diagram of refresh operation to tested FPGA for SRAM type FPGA single particle effect pilot system test FPGA of the present invention;
Fig. 5 carries out the workflow diagram of fault implant operation to tested FPGA for SRAM type FPGA single particle effect pilot system test FPGA of the present invention.
Fig. 6 carries out single-particle inversion and the operation of function break detection for SRAM type FPGA single particle effect pilot system test FPGA of the present invention to tested FPGA workflow diagram.
Fig. 7 carries out the workflow diagram of trigger upset detecting operation to tested FPGA for SRAM type FPGA single particle effect pilot system test FPGA of the present invention.
Embodiment
As shown in Figure 1, the composition frame chart for SRAM type FPGA single particle effect pilot system of the present invention comprises processor of single chip computer, RS232 interface circuit, usb circuit, test FPGA and storage unit.The present invention is in practical implementation; Processor of single chip computer is selected the C8051F020 of Silicon Laboratories company for use; Test FPGA selects the Cyclone III Series FPGA EP3C120F780C7 of altera corp for use; Tested FPGA selects the Virtex Series FPGA XQV300-4CB228 of Xilinx company for use, and the series arrangement mouth of this FPGA is the JTAG mouth, and parallel configuration mouth is the SelectMAP mouth.
At first carry out corresponding initialization operation, the back processor of single chip computer that powers on loads and initialization with test FPGA completion program automatically.The signal input of test FPGA cycle detection USB interface if receive the configurator download instruction from USB interface, then stops other operations, starts the configuration data down operation, receives configuration data, write storage unit from USB interface.The signal input of processor of single chip computer cycle detection RS232 interface; If receive configuration operation order, refresh operation order, fault injection order, single-particle inversion and function break detection operational order or the order of trigger upset detecting operation from the RS232 interface, then the corresponding command sent to test FPGA.Test FPGA reads desired data from storage unit; Series arrangement mouth or parallel configuration mouth through tested FPGA; Accomplish corresponding operation, and control command feedback signal or testing result are sent to processor of single chip computer, send to host computer through RS232 by processor of single chip computer.
As shown in Figure 2, be the processor of single chip computer workflow diagram of SRAM type FPGA single particle effect pilot system of the present invention.After system powered on, processor of single chip computer cycle detection RS232 interface had the no signal input.If the no signal input then continues cycle detection; If the signal input is arranged, then input signal is decoded, and send corresponding control command to test FPGA.After order was sent and accomplished, processor of single chip computer cycle detection test FPGA had or not control command feedback signal or testing result.If test FPGA does not provide control command feedback signal or testing result in setting-up time, then processor of single chip computer sends the time-out error signal to host computer; If receive orders feedback signal or testing result, then will order feedback signal or testing result to be sent to host computer.After sending completion, processor of single chip computer cycle detection RS232 interface again has the no signal input.
As shown in Figure 3, be the configuration operation workflow diagram of SRAM type FPGA single particle effect pilot system of the present invention.When test FPGA receives configuration operation when order from processor of single chip computer, start configuration operation to tested FPGA.At first enable configuration control signal CS, WRITE and the PROGRAM of tested FPGA, keep PEOGRAM low level 300ns at least, detect the INIT signal then.If the INIT signal is ineffective in official hour, then test FPGA and send the configuration failure signal to processor of single chip computer, finish this configuration operation; If the INIT signal effectively, then under the situation that detects configuration data transmitting counter and BUSY signal, sends configuration data through the SelectMAP mouth to tested FPGA in official hour, send up to all configuration datas and accomplish.After configuration data sends and accomplishes, detect the DONE signal of tested FPGA.If DONE is ineffective in official hour, then test FPGA and send the configuration failure signal to processor of single chip computer, finish this configuration operation; If DONE effectively, then tests FPGA to tested FPGA trigger initialize in official hour, and send the configuration successful signal, finish this configuration operation to processor of single chip computer.
As shown in Figure 4, be the refresh operation workflow diagram of SRAM type FPGA single particle effect pilot system of the present invention.When test FPGA receives refresh operation when order from processor of single chip computer, start refresh operation to tested FPGA.At first enable configuration control signal CS, the WRITE of tested FPGA, under the situation that detects configuration data transmitting counter and BUSY signal, send configuration data to tested FPGA, send up to all configuration datas and accomplish through the SelectMAP mouth.After configuration data sent and accomplishes, test FPGA sent the Flushing success signal to processor of single chip computer, finishes this refresh operation.When refresh operation is used for trigger upset detection, under the situation that does not change the trigger storing value, refresh the configuration data of tested FPGA, guarantee that tested FPGA user logical link is communicated with; When being used for the locking single particle detection, prevent that the working current of tested FPGA when locking single particle does not take place is excessive.
As shown in Figure 5, be the fault implant operation workflow diagram of SRAM type FPGA single particle effect pilot system of the present invention.When test FPGA receives fault implant operation when order from processor of single chip computer, start fault implant operation to tested FPGA.Test FPGA at first sends synchronization character through the JTAG mouth of tested FPGA to tested FPGA; Inject in detection failure under the situation of counter and BUSY signal; To the reprovision data of tested FPGA transmitting section reprovision data address and appropriate address, the part reprovision of tested FPGA is realized the fault injection through adopting fault data.After all reprovision data were sent and accomplished, test FPGA sent fault to processor of single chip computer and is injected into function signal, finishes this fault implant operation.
As shown in Figure 6, be the single-particle inversion and the function break detection operation element process flow diagram of SRAM type FPGA single particle effect pilot system of the present invention.When test FPGA when processor of single chip computer receives single-particle inversion and function break detection operational order, start single-particle inversion and the function break detection of tested FPGA operated.Test FPGA at first detects the DONE leg signal of tested FPGA, if the DONE signal is effective, judges that then tested FPGA the POR function does not take place interrupts; If the DONE signal is a low level, judge that then tested FPGA the POR function takes place interrupts.After POR function break detection finishes; Test FPGA sends synchronization character through the JTAG mouth of tested FPGA to tested FPGA; Read and write the special function register of tested FPGA, judge whether the JTAG mouth function takes place interrupt, send then and separate synchronization character and tested FPGA separates synchronously.After JTAG mouth function break detection finished, test FPGA sent synchronization character through the SelectMAP mouth of tested FPGA to tested FPGA, reads and writes the special function register of tested FPGA, judged whether the SelectMAP mouth function takes place interrupt.After SelectMAP mouth function break detection finishes; Test FPGA sends configuration retaking of a year or grade order through the SelectMAP mouth of tested FPGA to tested FPGA; Under the situation that detects configuration data retaking of a year or grade counter and BUSY signal;, accomplish from tested FPGA retaking of a year or grade configuration data through the SelectMAP mouth up to all configuration data retakings of a year or grade.Test FPGA compares the statistical discrepancy figure place in real time to retaking of a year or grade configuration data and original configuration data in the process of retaking of a year or grade configuration data.If before retaking of a year or grade detects, tested FPGA has been detected and interruption of POR function or the interruption of SelectMAP mouth function have occurred, and then the difference figure place of statistics can verify further that the function corresponding interruption has appearred in tested FPGA; If before retaking of a year or grade detects, tested FPGA is undetected to occur that the POR function is interrupted or SelectMAP mouth function is interrupted, and then the difference figure place of statistics is the single-particle inversion number of tested FPGA configuration data.After the configuration data single-particle inversion detects and finishes; Test FPGA sends BRAM retaking of a year or grade order through the SelectMAP mouth of tested FPGA to tested FPGA; Under the situation that detects BRAM data readback counter and BUSY signal;, accomplish from tested FPGA retaking of a year or grade BRAM data through the SelectMAP mouth up to all BRAM data readbacks.Test FPGA compares the statistical discrepancy figure place in real time to retaking of a year or grade BRAM data and original BRAM data in the process of retaking of a year or grade BRAM data.If before retaking of a year or grade detects, tested FPGA has been detected and interruption of POR function or the interruption of SelectMAP mouth function have occurred, and then the difference figure place of statistics can verify further that the function corresponding interruption has appearred in tested FPGA; If before retaking of a year or grade detects, tested FPGA is undetected to occur that the POR function is interrupted or SelectMAP mouth function is interrupted, and then the difference figure place of statistics is the single-particle inversion number of tested FPGA BRAM data.
As shown in Figure 7, be the trigger upset detecting operation workflow diagram of SRAM type FPGA single particle effect pilot system of the present invention.When test FPGA when processor of single chip computer receives the order of trigger upset detecting operation, start trigger upset detecting operation to tested FPGA.Test FPGA at first refreshes the configuration data of tested FPGA, the trigger value of the tested FPGA of retaking of a year or grade, and compare with the institute initialize, the statistical discrepancy figure place is trigger upset number.Test FPGA sends testing result to processor of single chip computer, finishes this trigger upset detecting operation.
When carrying out the single particle effect detection, method is following:
(1) test specimen is handled
Device is 300,000 FPGAXQV300-4CB228 of Xilinx company.Before the test, adopt " flat package FPGA device is opened the cap anchor clamps and opened the cap method around the pottery " that sample is opened cap, open not damage device inner structure of cap process.
(2) radiation source
Locking single particle detects radiation source and selects the Lanzhou HIRFL of modern physics research institute of Chinese Academy of Sciences cyclotron, and particle is Bi, and test is carried out in vacuum environment.The high energy particle that cyclotron produces in vacuum environment, the exposure experiment sample.Test is seen table 1 with the LET value and the range of particle.
Table 1 test is with effective LET value of particle
Single-particle inversion and function break detection radiation source are selected the HI-13 of China Atomic Energy Science Research Institute swindletron, and particle is Cu, and test is carried out in vacuum environment.The high energy particle that cyclotron produces in vacuum environment, the exposure experiment sample.Test is seen table 2 with the LET value and the range of particle.
Table 2 test is with effective LET value of particle
(3) locking single particle detects
1) sends initialization command by the outside, configuration data is delivered in the storage unit;
2) after initialization finishes, send configuration order to processor of single chip computer, start test FPGA tested FPGA is configured operation by the outside;
3) use radiation source to produce high energy particle and shine tested fpga chip surface;
4) configuration data of the tested FPGA of periodic refreshing prevents that the working current when locking single particle does not take place tested FPGA is excessive;
5) in whole experiment, tested FPGA working current is not found to become big suddenly, surpasses detection threshold, judges that locking single particle does not take place tested FPGA.
(4) single-particle function interruption, configuration store district, BRAM and trigger upset detect
1) sends initialization command by the outside, configuration data is delivered in the storage unit;
2) after initialization finishes, send configuration order to processor of single chip computer, start test FPGA tested FPGA is configured operation by the outside;
3) after configuration operation is accomplished, send it back read command to processor of single chip computer, start the read operation that loops back of test FPGA by the outside;
4) use radiation source to produce high energy particle and shine tested fpga chip surface;
5) test FPGA detects configuration address register and the DNOE pin of tested FPGA, judges whether tested FPGA the single-particle function takes place interrupt, and accomplishes the single-particle function interrupt test of tested FPGA;
6) confirming that FPGA does not take place under the situation of single-particle function interruption; The configuration data of the tested FPGA of test FPGA retaking of a year or grade; The corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and memory stores is compared in real time; Add up configuration store district and BRAM upset sum respectively, and statistics is sent to processor of single chip computer.
7) circulation execution in step (6)～(7), the POR function is interrupted or SelectMAP mouth function is interrupted until taking place, then the high energy particle end of radiation.Do not interrupt if the single-particle function takes place, the high energy particle fluence reaches 9 * 10
4～10
5/ cm
2The time end of radiation.
8) refresh the configuration data of tested FPGA, user's trigger value of reading tested FPGA compares with the institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer, accomplish the trigger function interrupt test.Test findings is seen table 3.
Table 3 single particle effect test experience result
The content of not doing to describe in detail in the instructions of the present invention belongs to this area professional and technical personnel's known technology.
Claims (8)
1.SRAM type FPGA single particle effect pilot system, its characteristic comprises: processor of single chip computer, test FPGA, storage unit, RS232 interface and USB interface, wherein:
Processor of single chip computer: receive outside configuration data and the control command that transmits, and said configuration data and order are delivered to test FPGA; According to the external control order, it is configuration operation state, refresh operation state, fault injection state, single-particle inversion and function break detection mode of operation and trigger upset detecting operation state that test FPGA is set; FPGA receives control command feedback signal and testing result from test, and exports to the outside;
Test FPGA: the order according to processor of single chip computer transmits is carried out initialization to storage unit, receives the configuration data that processor of single chip computer transmits, and deposits to storage unit; The order of transmitting according to processor of single chip computer gets into corresponding mode of operation, and said mode of operation comprises configuration operation state, refresh operation state, fault injection state, single-particle inversion and function break detection mode of operation and trigger upset detecting operation state; When the configuration operation state, test FPGA reads configuration data from storage unit, to the operation that is configured of tested FPGA, and to processor of single chip computer feedback configuration operating result; During the refresh operation state, to the operation that is configured of tested FPGA, and to processor of single chip computer feedback configuration operating result; When fault is injected state; After test FPGA receives the fault implant operation order of processor of single chip computer; Receive fault data information via USB interface from host computer, the series arrangement mouth through tested FPGA carries out the part reprovision to tested FPGA, in the configuration bit Write fault data of assigned address; Said part reprovision is only to make amendment to the segment of FPGA configuration file, thereby accomplish tested FPGA is carried out the fault injection; When single-particle inversion and function break detection mode of operation; From the current configuration data of tested FPGA retaking of a year or grade; The single-particle inversion that relatively carries out through with the original configuration data detects, and carries out single-particle function break detection through reading and writing tested FPGA configuration address register with detection DONE pin, when confirming that FPGA does not take place to have no progeny in the function; Send synch command and configuration data retaking of a year or grade order to tested FPGA successively; And detect the BUSY pin of tested FPGA, when the BUSY pin is invalid, the corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and memory stores is compared in real time; The statistics upset is total, and statistics is sent to processor of single chip computer; During trigger upset detecting operation state; Test FPGA at first refreshes the configuration data of tested FPGA; Guarantee that tested FPGA user logical link is communicated with, user's trigger value of reading tested FPGA then compares with the institute initialize; The statistics upset is total, and statistics is sent to processor of single chip computer;
Storage unit: be used to store the configuration data that the outside is transmitted;
RS232 interface: accomplish host computer to the processor of single chip computer transmitting control commands, and receive control command feedback or testing result from single-chip microcomputer;
USB interface: accomplish host computer and send tested FPGA original configuration data to test FPGA.
2. SRAM type FPGA single particle effect pilot system according to claim 1, it is characterized in that: the course of work of described processor of single chip computer is:
Processor of single chip computer at first carries out initialization operation, enters into cycling then; During cycling, the operation that next step need carry out is confirmed in the input of processor of single chip computer cycle detection RS232 interface signal; If processor of single chip computer is received configuration operation order, refresh operation order, fault injection order, single-particle inversion and function break detection operational order or the order of trigger upset detecting operation from the RS232 interface; Then the corresponding command is sent to test FPGA; After FPGA to be tested accomplishes corresponding operating; FPGA receives control command feedback signal or testing result from test, transmits to the outside through the RS232 interface.Processor of single chip computer gets into cycling again accomplishing all after dates of a command operation, waits for Next Command.
3. SRAM type FPGA single particle effect pilot system according to claim 1 is characterized in that: the course of work that described configuration data receives is:
Test FPGA at first carries out initialization operation, enters into cycling then; During cycling; The signal input of test FPGA cycle detection USB interface if test FPGA receives the configuration data download command from USB interface, then stops other operations; Receive the original configuration data of tested FPGA from USB interface continuously, and transfer to test FPGA and store.
4. SRAM type FPGA single particle effect pilot system according to claim 1 is characterized in that: the configuration operation process of described test FPGA is:
After receiving the configuration operation order of processor of single chip computer, enable configuration control pin CS, WRITE and the PROGRAM of tested FPGA, and guarantee that the PROGRAM signal keeps low level 300ns at least; Detect the INIT pin of tested FPGA output then; When I NIT pin is effective, reads configuration data and write tested FPGA, detect the BUSY pin of tested FPGA simultaneously, when the BUSY pin is invalid from the first address of config memory; Represent that these address configuration data have been written into tested FPGA; Cyclic address change with config memory repeats write operation, finishes until the whole configuration datas in the config memory are sent; Detect the DONE pin of tested FPGA output then, when the DONE pin is effective, represent the configuration successful of tested FPGA; After tested FPGA configuration successful, test FPGA begins user's trigger of tested FPGA is carried out initialization operation, and after initialization operation was accomplished, whole configuration operation was all over.
5. SRAM type FPGA single particle effect pilot system according to claim 1 is characterized in that: the refresh operation process of described test FPGA is:
After receiving the refresh operation order of processor of single chip computer; Read configuration data and write tested FPGA from the first address of config memory, detect the BUSY pin of tested FPGA simultaneously, when the BUSY pin is invalid; Represent that these address configuration data have been written into tested FPGA; Cyclic address change with config memory repeats write operation, finishes until the whole configuration datas in the config memory are sent.
6.SRAM type FPGA single particle effect test method is characterized in that comprising the fault injection; Single-particle inversion detects, and comprises that configuration store district, BRAM and trigger upset detect; Single-particle function break detection; Locking single particle detects one of four parts;
Wherein said fault filling method step is following:
(a) host computer is confirmed fault injection configuration bit position, and abort situation information is sent to processor of single chip computer;
(b) processor of single chip computer sends to test FPGA with abort situation information;
(c) test FPGA is according to the positional information that receives, and the series arrangement mouth through tested FPGA carries out the part reprovision to tested FPGA, and the configuration data of change corresponding configuration position is realized the fault injection;
Said single-particle inversion detects and single-particle function break detection merges completion, and performing step is following:
(1) selective radiation source;
(2) send initialization command by the outside, configuration data is delivered in the storage unit, accomplish initialization;
(3) after initialization finishes, send configuration order to processor of single chip computer, start test FPGA tested FPGA is configured operation by the outside;
(4) after configuration operation is accomplished, send sense command to processor of single chip computer, start the cycle detection operation of test FPGA by the outside;
(5) use radiation source to produce high energy particle and shine tested fpga chip surface;
(6) test FPGA detects configuration address register and the DONE pin of tested FPGA, judges whether tested FPGA the single-particle function takes place interrupt, and accomplishes the single-particle function interrupt test of tested FPGA;
(7) confirming that FPGA does not take place under the situation of single-particle function interruption; The configuration data of the tested FPGA of test FPGA retaking of a year or grade; The corresponding positions of the original configuration data of the significance bit of the configuration data of retaking of a year or grade and memory stores is compared in real time; Add up configuration store district and BRAM upset sum respectively, and statistics is sent to processor of single chip computer;
(8) circulation execution in step (6)～(7) are until the high energy particle end of radiation;
(9) refresh the configuration data of tested FPGA, user's trigger value of reading tested FPGA compares with the institute initialize, statistics upset sum, and statistics is sent to processor of single chip computer, accomplish the trigger function interrupt test;
Said locking single particle detection method performing step is following:
(A) selective radiation source;
(B) send initialization command by the outside, configuration data is delivered in the storage unit, accomplish initialization;
(C) after initialization finishes, send configuration order to processor of single chip computer, start test FPGA tested FPGA is configured operation by the outside;
(D) use radiation source to produce high energy particle and shine tested fpga chip surface;
(E) configuration data of the tested FPGA of periodic refreshing prevents that the working current when locking single particle does not take place tested FPGA is excessive;
(F) become big suddenly if find tested FPGA working current, surpass detection threshold, after the refresh configuration data, the basic no change of electric current judges that then locking single particle takes place tested FPGA.
7. SRAM type FPGA single particle effect test method according to claim 6; It is characterized in that: the radiation source among said step (1), (A) is cyclotron or tandem accelerator; The range of the high energy particle of its generation in silicon is greater than 30 μ m, and the LET value is greater than 30MeV.cm
2/ mg.
8. SRAM type FPGA single particle effect test method according to claim 6 is characterized in that: the condition of end of radiation is in the said step (8): the single-particle function takes place and interrupts in tested FPGA, and perhaps the fluence of radiation source irradiation particle reaches 9 * 10
4～10
5/ cm
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110214108.7A CN102332307B (en) | 2011-07-28 | 2011-07-28 | SRAM type FPGA single particle effect test system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110214108.7A CN102332307B (en) | 2011-07-28 | 2011-07-28 | SRAM type FPGA single particle effect test system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102332307A true CN102332307A (en) | 2012-01-25 |
| CN102332307B CN102332307B (en) | 2015-08-05 |
Family
ID=45484048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110214108.7A Active CN102332307B (en) | 2011-07-28 | 2011-07-28 | SRAM type FPGA single particle effect test system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102332307B (en) |
Cited By (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102636744A (en) * | 2012-04-24 | 2012-08-15 | 中国科学院空间科学与应用研究中心 | Device and method for detecting relationship between single event effects and time sequence characteristics of FPGA (Field Programmable Gate Array) |
| CN103033524A (en) * | 2012-12-31 | 2013-04-10 | 中国科学院微电子研究所 | Detection method for single-particle radiation effect |
| CN103063961A (en) * | 2012-12-28 | 2013-04-24 | 中国科学院微电子研究所 | Single event effect testing device and system |
| CN103165192A (en) * | 2013-04-16 | 2013-06-19 | 西北核技术研究所 | SRAM (Static Random Access Memory) single event latch-up effect testing system and method |
| CN103293468A (en) * | 2013-04-09 | 2013-09-11 | 北京时代民芯科技有限公司 | Fault injection system and fault injection method facilitating device fault sensitivity test |
| CN103323715A (en) * | 2013-06-20 | 2013-09-25 | 中国空间技术研究院 | Particle fluence rate selection method for large scale integrated circuit accelerator single particle test |
| CN103529380A (en) * | 2012-07-06 | 2014-01-22 | 北京圣涛平试验工程技术研究院有限责任公司 | Monitoring system and monitoring method for SRAM type FPGA (field-programmable gate array) single particle functional interruption |
| CN103577643A (en) * | 2013-11-06 | 2014-02-12 | 中国空间技术研究院 | SRAM type FPGA single event upset effect simulation method |
| CN103631738A (en) * | 2013-08-15 | 2014-03-12 | 中国科学院电子学研究所 | Off-chip configuration and readback FPGA device |
| CN103796009A (en) * | 2014-01-14 | 2014-05-14 | 北京空间机电研究所 | FPGA quality diagnostic test system |
| CN103792487A (en) * | 2012-10-31 | 2014-05-14 | 中国科学院电子学研究所 | FPGA testing device and method |
| CN103809109A (en) * | 2014-02-26 | 2014-05-21 | 工业和信息化部电子第五研究所 | Single event effect detection device and system for integrated circuit |
| CN103837839A (en) * | 2012-11-23 | 2014-06-04 | 北京圣涛平试验工程技术研究院有限责任公司 | Secondary electric power supply single event effect test method |
| CN104007427A (en) * | 2014-05-20 | 2014-08-27 | 上海微小卫星工程中心 | Mean free error time assessment method and system based on irradiation test satellite-borne responder |
| CN104181421A (en) * | 2014-08-22 | 2014-12-03 | 中国科学院空间科学与应用研究中心 | Device and method for field programmable gate array (FPGA) single event effect dynamic fault testing |
| CN104200846A (en) * | 2014-07-23 | 2014-12-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN104483622A (en) * | 2014-11-27 | 2015-04-01 | 北京时代民芯科技有限公司 | Single-particle irradiation experiment test system and method based on JTAG (joint test action group) interface |
| CN104698314A (en) * | 2015-03-05 | 2015-06-10 | 中国空间技术研究院 | Device-level automatic testing platform and testing method for SRAM type FPGA |
| CN104851467A (en) * | 2015-05-20 | 2015-08-19 | 中国空间技术研究院 | Function verification method for SRAM with EDAC function for use in space navigation |
| CN105068969A (en) * | 2015-07-17 | 2015-11-18 | 西安空间无线电技术研究所 | Single event effect protection system and method for digital signal processing platform architecture |
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN105590651A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | DRAM (dynamic random access memory) neutron single event effect test method |
| CN105590653A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | Neutron single event effect testing method of a SRAM type FPGA |
| CN105589780A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | Neutron single event effect testing method of CPU |
| CN105717443A (en) * | 2016-02-17 | 2016-06-29 | 北京时代民芯科技有限公司 | SRAM type FPGA trigger single-event upset resistance performance assessment system and method |
| CN105895163A (en) * | 2016-03-28 | 2016-08-24 | 工业和信息化部电子第五研究所 | Single event effect detection method and system based on image backup |
| CN107356864A (en) * | 2017-06-30 | 2017-11-17 | 西安电子科技大学 | PLL circuit anti-radiation performance appraisal procedure |
| CN107452426A (en) * | 2017-07-24 | 2017-12-08 | 中国空间技术研究院 | The detection circuit and detection method of memory element in a kind of fpga chip |
| CN107678896A (en) * | 2017-09-13 | 2018-02-09 | 湖南斯北图科技有限公司 | A kind of SRAM type FPGA upset fault injectors and fault filling method |
| CN107918097A (en) * | 2017-10-20 | 2018-04-17 | 西安空间无线电技术研究所 | A kind of disconnected section auto-adapted fitting method in systemic-function for realizing variable L ET values |
| CN108023587A (en) * | 2017-11-07 | 2018-05-11 | 北京时代民芯科技有限公司 | A kind of programmable configuration logic single-particle in the block reinforces clock control circuit and control method |
| CN108257646A (en) * | 2018-03-29 | 2018-07-06 | 榆林学院 | SRAM read-write indirectly testing device and methods based on LabVIEW |
| US10083043B2 (en) | 2013-02-11 | 2018-09-25 | Dspace Digital Signal Processing And Control Engineering Gmbh | Random access to signal values of an FPGA at runtime |
| CN108733552A (en) * | 2017-04-18 | 2018-11-02 | 北京大学 | A kind of FPGA remote debugging systems and remote debugging method |
| CN109189624A (en) * | 2018-09-11 | 2019-01-11 | 西安微电子技术研究所 | A kind of magnanimity information processing device single particle experiment implementation method and single particle test plate |
| CN109508271A (en) * | 2018-08-15 | 2019-03-22 | 西北工业大学 | A kind of device and method for the clock sources single-particle dynamic overturning detecting FPGA |
| CN104981807B (en) * | 2013-02-11 | 2019-04-23 | 帝斯贝思数字信号处理和控制工程有限公司 | Change the signal value of FPGA in operation |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110568347A (en) * | 2019-08-07 | 2019-12-13 | 北京空间飞行器总体设计部 | Rapid estimation method for single-particle function interruption rate of satellite-borne FPGA |
| CN112433894A (en) * | 2020-10-27 | 2021-03-02 | 深圳市紫光同创电子有限公司 | FPGA test method and test system |
| CN112447201A (en) * | 2020-10-29 | 2021-03-05 | 中国空间技术研究院 | System-level space single particle protection method suitable for SRAM type FPGA product |
| CN112988431A (en) * | 2021-03-18 | 2021-06-18 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113376514A (en) * | 2021-06-09 | 2021-09-10 | 深圳米飞泰克科技有限公司 | FPGA chip testing method, device, system and storage medium |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135920A (en) * | 2011-01-17 | 2011-07-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
-
2011
- 2011-07-28 CN CN201110214108.7A patent/CN102332307B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102135920A (en) * | 2011-01-17 | 2011-07-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 于庆奎: "SRAM FPGA电离辐射效应试验研究", 《航天器环境工程》 * |
Cited By (71)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102636744A (en) * | 2012-04-24 | 2012-08-15 | 中国科学院空间科学与应用研究中心 | Device and method for detecting relationship between single event effects and time sequence characteristics of FPGA (Field Programmable Gate Array) |
| CN102636744B (en) * | 2012-04-24 | 2014-06-11 | 中国科学院空间科学与应用研究中心 | Device and method for detecting relationship between single event effects and time sequence characteristics of FPGA (Field Programmable Gate Array) |
| CN103529380A (en) * | 2012-07-06 | 2014-01-22 | 北京圣涛平试验工程技术研究院有限责任公司 | Monitoring system and monitoring method for SRAM type FPGA (field-programmable gate array) single particle functional interruption |
| CN103529380B (en) * | 2012-07-06 | 2016-08-03 | 北京圣涛平试验工程技术研究院有限责任公司 | The monitoring system and method for SRAM type FPGA single particle functional interruption |
| CN103792487A (en) * | 2012-10-31 | 2014-05-14 | 中国科学院电子学研究所 | FPGA testing device and method |
| CN103837839A (en) * | 2012-11-23 | 2014-06-04 | 北京圣涛平试验工程技术研究院有限责任公司 | Secondary electric power supply single event effect test method |
| CN103837839B (en) * | 2012-11-23 | 2016-07-06 | 北京圣涛平试验工程技术研究院有限责任公司 | Secondary power supply single particle effect test method |
| CN103063961A (en) * | 2012-12-28 | 2013-04-24 | 中国科学院微电子研究所 | Single event effect testing device and system |
| CN103033524A (en) * | 2012-12-31 | 2013-04-10 | 中国科学院微电子研究所 | Detection method for single-particle radiation effect |
| US10083043B2 (en) | 2013-02-11 | 2018-09-25 | Dspace Digital Signal Processing And Control Engineering Gmbh | Random access to signal values of an FPGA at runtime |
| CN104981807B (en) * | 2013-02-11 | 2019-04-23 | 帝斯贝思数字信号处理和控制工程有限公司 | Change the signal value of FPGA in operation |
| US10311193B2 (en) | 2013-02-11 | 2019-06-04 | Dspace Digital Signal Processing And Control Engineering Gmbh | Alteration of a signal value for an FPGA at runtime |
| CN103293468A (en) * | 2013-04-09 | 2013-09-11 | 北京时代民芯科技有限公司 | Fault injection system and fault injection method facilitating device fault sensitivity test |
| CN103165192A (en) * | 2013-04-16 | 2013-06-19 | 西北核技术研究所 | SRAM (Static Random Access Memory) single event latch-up effect testing system and method |
| CN103323715A (en) * | 2013-06-20 | 2013-09-25 | 中国空间技术研究院 | Particle fluence rate selection method for large scale integrated circuit accelerator single particle test |
| CN103323715B (en) * | 2013-06-20 | 2015-08-05 | 中国空间技术研究院 | Particle fluence rate system of selection in large scale integrated circuit accelerator single particle experiment |
| CN103631738B (en) * | 2013-08-15 | 2016-08-10 | 中国科学院电子学研究所 | A kind of off-chip configuration and readback FPGA device |
| CN103631738A (en) * | 2013-08-15 | 2014-03-12 | 中国科学院电子学研究所 | Off-chip configuration and readback FPGA device |
| CN103577643B (en) * | 2013-11-06 | 2016-06-01 | 中国空间技术研究院 | A kind of SRAM type FPGA single particle upset effect emulation method |
| CN103577643A (en) * | 2013-11-06 | 2014-02-12 | 中国空间技术研究院 | SRAM type FPGA single event upset effect simulation method |
| CN103796009A (en) * | 2014-01-14 | 2014-05-14 | 北京空间机电研究所 | FPGA quality diagnostic test system |
| CN103796009B (en) * | 2014-01-14 | 2016-01-20 | 北京空间机电研究所 | A kind of FPGA quality diagnosis test macro |
| CN103809109A (en) * | 2014-02-26 | 2014-05-21 | 工业和信息化部电子第五研究所 | Single event effect detection device and system for integrated circuit |
| CN104007427A (en) * | 2014-05-20 | 2014-08-27 | 上海微小卫星工程中心 | Mean free error time assessment method and system based on irradiation test satellite-borne responder |
| CN104007427B (en) * | 2014-05-20 | 2017-01-25 | 上海微小卫星工程中心 | Mean free error time assessment method and system based on irradiation test satellite-borne responder |
| CN104200846A (en) * | 2014-07-23 | 2014-12-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN104200846B (en) * | 2014-07-23 | 2017-05-10 | 北京空间机电研究所 | Embedded-type PROM test system and achieving method |
| CN104181421B (en) * | 2014-08-22 | 2017-03-08 | 中国科学院空间科学与应用研究中心 | FPGA single particle effect dynamic fault test device and method |
| CN104181421A (en) * | 2014-08-22 | 2014-12-03 | 中国科学院空间科学与应用研究中心 | Device and method for field programmable gate array (FPGA) single event effect dynamic fault testing |
| CN105590653A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | Neutron single event effect testing method of a SRAM type FPGA |
| CN105589780A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | Neutron single event effect testing method of CPU |
| CN105590651A (en) * | 2014-10-22 | 2016-05-18 | 北京圣涛平试验工程技术研究院有限责任公司 | DRAM (dynamic random access memory) neutron single event effect test method |
| CN104483622A (en) * | 2014-11-27 | 2015-04-01 | 北京时代民芯科技有限公司 | Single-particle irradiation experiment test system and method based on JTAG (joint test action group) interface |
| CN104483622B (en) * | 2014-11-27 | 2017-08-25 | 北京时代民芯科技有限公司 | A kind of single particle radiation test system and method based on jtag interface |
| CN104698314B (en) * | 2015-03-05 | 2018-01-02 | 中国空间技术研究院 | A kind of SRAM type FPGA device level automatic test platform and its method of testing |
| CN104698314A (en) * | 2015-03-05 | 2015-06-10 | 中国空间技术研究院 | Device-level automatic testing platform and testing method for SRAM type FPGA |
| CN104851467B (en) * | 2015-05-20 | 2017-12-22 | 中国空间技术研究院 | A kind of aerospace band EDAC function SRAM memory function verification methods |
| CN104851467A (en) * | 2015-05-20 | 2015-08-19 | 中国空间技术研究院 | Function verification method for SRAM with EDAC function for use in space navigation |
| CN105068969B (en) * | 2015-07-17 | 2018-02-09 | 西安空间无线电技术研究所 | Single particle effect guard system and method for digital signal processing platform framework |
| CN105068969A (en) * | 2015-07-17 | 2015-11-18 | 西安空间无线电技术研究所 | Single event effect protection system and method for digital signal processing platform architecture |
| CN105185413A (en) * | 2015-09-24 | 2015-12-23 | 中国航天科技集团公司第九研究院第七七一研究所 | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure |
| CN105185413B (en) * | 2015-09-24 | 2018-06-22 | 中国航天科技集团公司第九研究院第七七一研究所 | For the automatic verification platform and method of on piece MMU memory management unit fault-tolerant architecture |
| CN105548866A (en) * | 2015-12-08 | 2016-05-04 | 中国科学院电子学研究所 | SRAM type FPGA test method based on irradiation test environment simulation |
| CN105717443A (en) * | 2016-02-17 | 2016-06-29 | 北京时代民芯科技有限公司 | SRAM type FPGA trigger single-event upset resistance performance assessment system and method |
| CN105895163B (en) * | 2016-03-28 | 2018-09-28 | 工业和信息化部电子第五研究所 | Single particle effect detection method based on mirror back-up and system |
| CN105895163A (en) * | 2016-03-28 | 2016-08-24 | 工业和信息化部电子第五研究所 | Single event effect detection method and system based on image backup |
| CN108733552A (en) * | 2017-04-18 | 2018-11-02 | 北京大学 | A kind of FPGA remote debugging systems and remote debugging method |
| CN108733552B (en) * | 2017-04-18 | 2020-12-22 | 北京大学 | FPGA remote debugging system and remote debugging method |
| CN107356864B (en) * | 2017-06-30 | 2019-07-16 | 西安电子科技大学 | PLL circuit anti-radiation performance appraisal procedure |
| CN107356864A (en) * | 2017-06-30 | 2017-11-17 | 西安电子科技大学 | PLL circuit anti-radiation performance appraisal procedure |
| CN107452426B (en) * | 2017-07-24 | 2020-04-07 | 中国空间技术研究院 | Detection circuit and detection method for storage element in FPGA chip |
| CN107452426A (en) * | 2017-07-24 | 2017-12-08 | 中国空间技术研究院 | The detection circuit and detection method of memory element in a kind of fpga chip |
| CN107678896B (en) * | 2017-09-13 | 2020-11-27 | 湖南斯北图科技有限公司 | SRAM (static random Access memory) type FPGA (field programmable Gate array) upset fault injector and fault injection method |
| CN107678896A (en) * | 2017-09-13 | 2018-02-09 | 湖南斯北图科技有限公司 | A kind of SRAM type FPGA upset fault injectors and fault filling method |
| CN107918097B (en) * | 2017-10-20 | 2020-03-24 | 西安空间无线电技术研究所 | Adaptive fitting method for system function interrupt section capable of realizing variable LET value |
| CN107918097A (en) * | 2017-10-20 | 2018-04-17 | 西安空间无线电技术研究所 | A kind of disconnected section auto-adapted fitting method in systemic-function for realizing variable L ET values |
| CN108023587B (en) * | 2017-11-07 | 2022-01-11 | 北京时代民芯科技有限公司 | Single-particle reinforced clock control circuit and control method in programmable configuration logic block |
| CN108023587A (en) * | 2017-11-07 | 2018-05-11 | 北京时代民芯科技有限公司 | A kind of programmable configuration logic single-particle in the block reinforces clock control circuit and control method |
| CN108257646A (en) * | 2018-03-29 | 2018-07-06 | 榆林学院 | SRAM read-write indirectly testing device and methods based on LabVIEW |
| CN109508271A (en) * | 2018-08-15 | 2019-03-22 | 西北工业大学 | A kind of device and method for the clock sources single-particle dynamic overturning detecting FPGA |
| CN109189624A (en) * | 2018-09-11 | 2019-01-11 | 西安微电子技术研究所 | A kind of magnanimity information processing device single particle experiment implementation method and single particle test plate |
| CN109189624B (en) * | 2018-09-11 | 2022-02-01 | 西安微电子技术研究所 | Mass information processor single particle test implementation method and single particle test board |
| CN110444243A (en) * | 2019-07-31 | 2019-11-12 | 至誉科技（武汉）有限公司 | Store test method, system and the storage medium of equipment read error error correcting capability |
| CN110568347A (en) * | 2019-08-07 | 2019-12-13 | 北京空间飞行器总体设计部 | Rapid estimation method for single-particle function interruption rate of satellite-borne FPGA |
| CN110568347B (en) * | 2019-08-07 | 2021-11-09 | 北京空间飞行器总体设计部 | Rapid estimation method for single-particle function interruption rate of satellite-borne FPGA |
| CN112433894A (en) * | 2020-10-27 | 2021-03-02 | 深圳市紫光同创电子有限公司 | FPGA test method and test system |
| CN112433894B (en) * | 2020-10-27 | 2022-09-13 | 深圳市紫光同创电子有限公司 | FPGA test method and test system |
| CN112447201A (en) * | 2020-10-29 | 2021-03-05 | 中国空间技术研究院 | System-level space single particle protection method suitable for SRAM type FPGA product |
| CN112988431A (en) * | 2021-03-18 | 2021-06-18 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN112988431B (en) * | 2021-03-18 | 2022-07-08 | 中国人民解放军国防科技大学 | Reliability evaluation method and system for different exceptions of SRAM (static random Access memory) type FPGA (field programmable Gate array) |
| CN113376514A (en) * | 2021-06-09 | 2021-09-10 | 深圳米飞泰克科技有限公司 | FPGA chip testing method, device, system and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102332307B (en) | 2015-08-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102332307B (en) | SRAM type FPGA single particle effect test system and method | |
| CN102332310B (en) | FPGA (Field Programmable Gate Array)-based single event effect test system for NAND FLASH device | |
| CN102332311B (en) | FPGA (Field Programmable Gate Array)-based single event effect test method for NAND FLASH device | |
| CN108710551B (en) | SPARC processor-based single event upset fault injection test method and system | |
| CN103325411B (en) | A kind of anti-single particle overturn hardened system and method thereof for FPGA | |
| CN109858195B (en) | Online simulation system for necessary bit single-particle upset fault on SRAM (static random Access memory) type FPGA (field programmable Gate array) | |
| CN106484581B (en) | It may be programmed SOC device single-particle inversion detection system and method under space radiation environment | |
| CN103150228B (en) | Synthesizable pseudorandom verification method and device for high-speed buffer memory | |
| CN103971732A (en) | Method and system for monitoring single event upset effect of FPGA (field programmable gate array) and correcting reloading | |
| CN103198868A (en) | Fault simulation system and fault analysis method for single event upset | |
| CN102043878B (en) | Reusable verification device and verification method of SOC chip based on DW8051 core | |
| CN103021469A (en) | Universal single event effect detecting method of memory circuit | |
| CN108226748A (en) | For the single particle effect test method of SoC systems on chip | |
| CN105185413A (en) | Automatic verification platform and method for on-chip memory management unit fault-tolerant structure | |
| CN102135920A (en) | Fault injection system for embedded spaceborne computer and injection method thereof | |
| CN103019177A (en) | Single event effect monitoring system of space general-purpose memory | |
| CN105548866A (en) | SRAM type FPGA test method based on irradiation test environment simulation | |
| CN109491821A (en) | Primary particle inversion resistant hardened system and method | |
| CN104181421A (en) | Device and method for field programmable gate array (FPGA) single event effect dynamic fault testing | |
| CN1983286A (en) | Automatic intelligent single-particle fault injector | |
| CN103944778B (en) | A kind of distributed event injection device based on combined test collection | |
| CN202443461U (en) | Single-particle error injection simulation test system | |
| CN112710913A (en) | Two-class multi-type COTS device single event soft error testing hardware system | |
| CN107356864B (en) | PLL circuit anti-radiation performance appraisal procedure | |
| CN202677396U (en) | Heterogeneous fault-tolerant circuit design system based on space searching technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |