CN103796009B - A kind of FPGA quality diagnosis test macro - Google Patents
A kind of FPGA quality diagnosis test macro Download PDFInfo
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Abstract
A kind of FPGA quality diagnosis test macro, comprise hardware circuit and FPGA software logic, hardware circuit comprises I/O interface circuit, RS232 interface circuit and SMA between test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, FPGA and exports test circuit.The present invention overcomes the prior art deficiency low to FPGA internal resource test coverage, and real-time is good, and highly versatile is simple to operate, meets the requirement to fpga chip in camera space video electronic system testing process.
Description
Technical field
The invention belongs to space remote sensor technical field, relate to a kind of FPGA quality diagnosis test macro being applied to camera space video electronic system.
Background technology
Fpga chip is the Primary Component in space remote sensing camera video electronic system.In space remote sensing camera video electronic system, ccd sensor receives the light signal from optical system, complete the conversion of light signal to the signal of telecommunication, the signal of telecommunication after conversion is converted to digital signal after the operations such as signal processor correlated-double-sampling, A/D conversion, send fpga chip digital signal processor to, complete the synthesis of multiway images signal, image procossing and be output into picture.Wherein fpga chip is the control core of system, for generation of ccd sensor Control timing sequence, produce signal processor Control timing sequence, produce multiway images Data Synthesis, image procossing and number and pass sequential, space remote sensing camera video electronic system theory diagram as shown in Figure 1.Because the environmental requirement of space remote sensing camera applications is higher, in the development process of video electronic system, need to carry out multi-functional and performance test to Systematical control core FPGA chip, likely occur that part fpga chip is discontented with the situation of pedal system requirement, also have impact on the test job of subsequent video treatment circuit while causing economic loss, and then affect the R&D cycle of camera entirety.
Therefore develop a kind of FPGA quality diagnosis test macro being applied to camera space video electronic system, before fpga chip falls weldering, do exhaustive diagnosis test is necessary.
Summary of the invention
The technology of the present invention is dealt with problems: overcome the deficiency that prior art is low to FPGA internal resource test coverage, provide a kind of FPGA quality diagnosis test macro, real-time is good, highly versatile, simple to operate, register stage test can being deep into, not only can realizing not using the quality of FPGA to screen, also contribute to locating the problem place that permanent fault FPGA occurs, to meet the requirement to fpga chip in camera space video electronic system testing process.
A kind of FPGA quality diagnosis test macro, is characterized in that comprising: between test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, FPGA, I/O interface circuit, a RS232 interface circuit, the 2nd RS232 interface circuit and SMA export test circuit; PROM is used for On-board test FPGA configuration data, tested FPGA configuration data and the mask data for retaking of a year or grade functional verification; SRAM is used for the tested FPGA configuration data of on-line storage and mask data; After system power-up, after test FPGA completes configuration, from PROM, read tested FPGA configuration data and mask data, and dump in external SRAM, for tested FPGA configuration and retaking of a year or grade functional verification; Power supply and configuration circuit provide the power supply required for normally working and configuring chip for testing FPGA; Temperature acquisition cuicuit is for extracting tested FPGA working temperature; I/O interface circuit realizes test FPGA and communicates with tested FPGA; SMA exports test circuit for verifying that tested FPGA global clock network is verified, IO output level type and driving force test; PC is communicated with test FPGA by a RS232 interface, to obtain test FPGA operating state; Test FPGA is communicated with tested FPGA by the 2nd RS232 interface, obtains tested FPGA operating state;
Test FPGA carries out tested FPGA according to the RS232 instruction that host computer comes by SelectMAP parallel interface and configures and retaking of a year or grade functional verification; Complete tested FPGA and realize the functional test of DSP48s multiplier unit; Complete tested FPGA register stage translocation examination; Complete the inner BRAM functional verification of tested FPGA; Tested FPGA working temperature is obtained by temperature test circuit;
The RS232 instruction that tested FPGA comes according to host computer, completes the functional test of all inner DSP48s multiplier units, and to test FPGA feedback test result; Complete global clock network checking; Complete IO output level type and driving force test; Complete temperature sensing unit functional verification.
Described SMA exports test circuit and comprises 24 road FPGA clock performance test circuits, 24 road IO multilevel type test circuits and 32 road IO driving force test circuits.
Described test FPGA is implemented as follows:
(1) after system power-up, test FPGA is configured from exterior arrangement PROM, after having configured, tested FPGA configuration data, comparison data and mask data is read from exterior storage PROM, and tested FPGA configuration data, comparison data and mask data are stored into respectively in outside different SRAM, then enter wait instruction state.
(2) after test FPGA receives instruction, decipher is carried out to instruction, according to the instruction specifically received, complete (3) ~ (7) process correspondence test.
(3) configure and retaking of a year or grade functional verification instruction if test FPGA receives tested FPGA, first test FPGA reads tested FPGA configuration data in SRAM, and is configured tested FPGA by SelectMAP parallel interface; After having configured, tested FPGA enters operating state; After at least 3 seconds, test FPGA carries out retaking of a year or grade by SelectMAP parallel interface to tested FPGA, and back read data is compared in real time with the comparison data deposited in SRAM, mask data, add up discrepant bit, and statistic is sent to PC by a RS232 interface.
(4) if test FPGA receives tested FPGA inner DSP48s multiplier unit functional test instruction, instruction is forwarded to tested FPGA by the 2nd RS232 interface by test FPGA, and pass through the test result of the inner DSP48s multiplier unit of the tested FPGA of the 2nd RS232 interface, by a RS232 interface feedback test result to PC.
(5) if test FPGA receives tested FPGA inner BRAM functional verification instruction, test FPGA writes test data by I/O interface to tested FPGA, and by I/O interface from tested FPGA inner BRAM read test data, add up discrepant bit, and statistic is sent to PC by a RS232 interface.
(6) if test FPGA receives obtain the instruction of tested FPGA working temperature, test FPGA obtains tested FPGA working temperature by temperature test circuit, and Temperature numerical is sent to PC by a RS232 interface.
(7) if test FPGA receives the test instruction of tested FPGA register stage connection, test FPGA is configured tested FPGA by SelectMAP parallel interface, makes tested FPGA be operated in register tandem states; Test FPGA writes test data by I/O interface to tested FPGA, and by I/O interface from tested FPGA read test data, adds up discrepant bit, and statistic is sent to PC by a RS232 interface.
(8) testing FPGA to complete in (3) ~ (7) after a content measurement, enters wait instruction state, then implementation (2).
Described tested FPGA is implemented as follows:
Tested FPGA is configured to two kinds of operating states, is configured to self-test state implementation procedure:
(1), after system power-up, tested FPGA is configured by SelectMAP parallel interface by testing FPGA.
(2), after having configured, tested FPGA carries out the functional test of inner DSP48s multiplier unit, after having tested, and logging test results.
(3) tested FPGA carries out global clock network checking, tested FPGA exports master clock by IO, master clock 2 frequency-dividing clock and master clock 10 frequency-dividing clock, often kind of clock all adopts single-ended and difference output, uses oscillograph recording often to plant the frequency values of clock, duty ratio and jitter amplitude.
(4) tested FPGA carries out IO output level type and driving force test, and tested FPGA exports 3 kinds of multilevel type by IO, records the magnitude of voltage of often kind of multilevel type low and high level respectively, and driving force when load is 10K Ω.
(5) after tested FPGA completes (2) ~ (4) test, enter wait instruction state, after tested FPGA receives instruction from the 2nd RS232, decipher is carried out to instruction, if instruction is for obtaining tested FPGA inner DSP48s multiplier unit functional verification result, then tested FPGA is by the 2nd RS232 feedback test result, and any operation is not done in other instructions, continues to enter wait instruction state.
When tested FPGA is configured to register tandem states, do not carry out any operation, passive reception test FPGA controls.
The present invention's advantage is compared with prior art:
(1) the present invention overcomes the prior art deficiency low to FPGA internal resource test coverage;
(2) the present invention can be used for carrying out quality diagnosis to FPGA before space remote sensing camera video electronic system at FPGA, the reliability of FPGA is tested, reduce fpga chip in space remote sensing camera video electronic system test process and occur the risk that function and performance do not meet the demands, improve the feasibility of fpga chip quality diagnosis test.
(3) the present invention can carry out register stage test to FPGA, real-time is good, highly versatile, simple to operate, not only can realize not using the quality of FPGA to screen, also contribute to locating the problem place that permanent fault FPGA occurs, to meet the demand to fpga chip failure diagnosis in camera space video electronic system testing process.
(4) the present invention by change FPGA software and can change FPGA Test bench, and the FPGA of diagnostic test different model, highly versatile, can meet space remote sensing camera video electronic system to the demand of FPGA.
Accompanying drawing explanation
Fig. 1 remote sensing camera video electronic system principle diagram;
Fig. 2 fpga chip quality diagnosis of the present invention test system hardware block diagram;
The realization flow figure of FPGA is tested in Fig. 3 the present invention;
Tested FPGA specific functional units DPS48s test philosophy block diagram in Fig. 4 the present invention;
Tested FPGA register cascade theory diagram in Fig. 5 the present invention;
The realization flow figure of tested FPGA in Fig. 6 the present invention.
Embodiment
For meeting space remote sensing camera video electronic system to fpga chip quality diagnosis test request, as shown in Figure 2, the present invention includes test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, I/O interface circuit between FPGA, one RS232 interface circuit, 2nd RS232 interface circuit and SMA export test circuit, PROM is used for On-board test FPGA configuration data, tested FPGA configuration data and the comparison data for retaking of a year or grade functional verification, mask data, SRAM is used for the tested FPGA configuration data of on-line storage, comparison data and mask data.The present invention is in concrete enforcement, and test FPGA selects the VirtexV Series FPGA XC5FXL130T-1FF1738 of Xilinx company, and tested FPGA selects the VirtexIV Series FPGA XC4VSX55-10FF1148 of Xilinx company.
First carry out corresponding initialization operation, test FPGA after powering on and automatically complete program loading and configuration.Test FPGA is configured from exterior arrangement PROM, after having configured, read tested FPGA configuration data, comparison data and mask data from exterior storage PROM, and tested FPGA configuration data, comparison data and mask data are stored into respectively in outside different SRAM.The signal input of test FPGA cycle detection the one RS232 interface circuit, if configuration and retaking of a year or grade functional verification instruction, tested FPGA inner DSP48s multiplier unit functional test instruction, tested FPGA inner BRAM functional verification instruction from a RS232 interface to tested FPGA, obtain the instruction of tested FPGA working temperature or tested FPGA register stage joins test instruction, test FPGA performs corresponding operation, and sends detecting information by a RS232 interface circuit to host computer.The configuration of tested FPGA and operating state are then determined by test FPGA.
As shown in Figure 3, be a kind of FPGA quality diagnosis of the present invention test system and test FPGA workflow diagram.After system electrification, test FPGA is configured from exterior arrangement PROM, after having configured, tested FPGA configuration data, comparison data and mask data is read from exterior storage PROM, and tested FPGA configuration data, comparison data and mask data are stored into respectively in outside different SRAM, then enter wait instruction state.Test FPGA cycle detection the one RS232 interface circuit has no signal to input.If no signal inputs, then continue cycle detection; If there is signal to input, then input signal is decoded, obtain the corresponding control command that host computer sends from a RS232 interface circuit.After control order finishes receiving, test FPGA judges instruction:
Test FPGA receives tested FPGA and configures and retaking of a year or grade functional verification instruction, and first test FPGA reads tested FPGA configuration data in SRAM, and is configured tested FPGA by SelectMAP parallel interface; After having configured, tested FPGA enters operating state; After at least 3 seconds, test FPGA carries out retaking of a year or grade by SelectMAP parallel interface to tested FPGA, and back read data is compared in real time with the comparison data deposited in SRAM, mask data, add up discrepant bit, and statistic is sent to PC by a RS232 interface.
Test FPGA receives tested FPGA inner DSP48s multiplier unit functional test instruction, instruction is forwarded to tested FPGA by the 2nd RS232 interface by test FPGA, and pass through the test result of the inner DSP48s multiplier unit of the tested FPGA of the 2nd RS232 interface, by a RS232 interface feedback test result to PC.The functional test of tested FPGA inner DSP48s multiplier unit as shown in Figure 4, mainly through inputting different test datas to DSP48s, after obtaining corresponding result of calculation, result of calculation is compared with the correct value prestored in the register bank, verified by result comparison.
Test FPGA receives tested FPGA inner BRAM functional verification instruction, test FPGA writes test data by I/O interface to tested FPGA, and by I/O interface from tested FPGA inner BRAM read test data, add up discrepant bit, and statistic is sent to PC by a RS232 interface.The interface opening of this memory module, for all for tested FPGA inner BRAM are configured to a memory module, carry out read-write operation then to test FPGA, has carried out its inner BRAM functional memory cell test by mentality of designing.For tested Xilinx company VirtexIV Series FPGA XC4VSX55-10FF1148, memory module port definition can be obtained: need 82 Pin interfaces altogether by the FPGA developing instrument ISE of Xilinx, wherein 2 clocks, 80 common IO, read and write data independent with read/write address, wherein data bit width 18, address bit wide 19, the read-write degree of depth 327680, can make inner 320 the 18KbitBRAM memory cell of tested FPGA all use like this.Mainly through writing different test datas to inner BRAM, and then reading data, being verified by result comparison.
Test FPGA receives and obtains the instruction of tested FPGA working temperature, and test FPGA obtains tested FPGA working temperature by temperature test circuit, and Temperature numerical is sent to PC by a RS232 interface.
Test FPGA receives the test instruction of tested FPGA register stage connection, and test FPGA is configured tested FPGA by SelectMAP parallel interface, makes tested FPGA be operated in register tandem states; Test FPGA writes test data by I/O interface to tested FPGA, and by I/O interface from tested FPGA read test data, adds up discrepant bit, and statistic is sent to PC by a RS232 interface.As shown in Figure 5, after tested FPGA has configured, internal register has been configured to link, makes register cascade as much as possible in tested FPGA register stage translocation examination test.For tested Xilinx company VirtexIV Series FPGA XC4VSX55-10FF1148, situation about wherein realizing is D0:D7 is that 8bit is wide, and namely N is 7, M is 5994 grades, and tested FPGA register utilization rate reaches 97%.Mainly through writing different test datas to chain of registers, and then reading data, being verified by result comparison.
As shown in Figure 6, be the tested FPGA workflow diagram of a kind of FPGA quality diagnosis test macro of the present invention.Tested FPGA is configured to two kinds of operating states, is configured to self-test state implementation procedure: after system power-up, and tested FPGA is configured by SelectMAP parallel interface by testing FPGA.After having configured, tested FPGA carries out the functional test of inner DSP48s multiplier unit, after having tested, and logging test results.Tested FPGA carries out global clock network checking, tested FPGA exports master clock by IO, master clock 2 frequency-dividing clock and master clock 10 frequency-dividing clock, often kind of clock all adopts single-ended and difference output, uses oscillograph recording often to plant the frequency values of clock, duty ratio and jitter amplitude during debugging.Tested FPGA carries out IO output level type and driving force test, and tested FPGA exports 3 kinds of multilevel type by IO, records the magnitude of voltage of often kind of multilevel type low and high level respectively, and driving force when load is 10K Ω.After tested FPGA completes above-mentioned test, enter wait instruction state, after tested FPGA receives instruction from the 2nd RS232, decipher is carried out to instruction, if instruction is for obtaining tested FPGA inner DSP48s multiplier unit functional verification result, then tested FPGA is by the 2nd RS232 feedback test result, and any operation is not done in other instructions, continues to enter wait instruction state.
When tested FPGA is configured to register tandem states, do not carry out any operation, passive reception test FPGA controls.
Claims (4)
1. a FPGA quality diagnosis test macro, is characterized in that comprising: between test FPGA, tested FPGA, PROM, SRAM, power supply and configuration circuit, tested FPGA temperature acquisition cuicuit, FPGA, I/O interface circuit, a RS232 interface circuit, the 2nd RS232 interface circuit and SMA export test circuit; PROM is used for On-board test FPGA configuration data, tested FPGA configuration data and comparison data, mask data for retaking of a year or grade functional verification; SRAM is used for the tested FPGA configuration data of on-line storage, comparison data and mask data; After system power-up, after test FPGA completes configuration, from PROM, read tested FPGA configuration data, comparison data and mask data, and dump in external SRAM, for tested FPGA configuration and retaking of a year or grade functional verification; Power supply and configuration circuit provide the power supply required for normally working and configuring chip for testing FPGA; Temperature acquisition cuicuit is for extracting tested FPGA working temperature; I/O interface circuit realizes test FPGA and communicates with tested FPGA; SMA exports test circuit for verifying that tested FPGA global clock network is verified, IO output level type and driving force test; PC is communicated with test FPGA by a RS232 interface, to obtain test FPGA operating state; Test FPGA is communicated with tested FPGA by the 2nd RS232 interface, obtains tested FPGA operating state;
Test FPGA carries out tested FPGA according to the RS232 control command that PC comes by SelectMAP parallel interface and configures and retaking of a year or grade functional verification; Complete tested FPGA and realize the functional test of DSP48s multiplier unit; Complete tested FPGA register stage translocation examination; Complete the inner BRAM functional verification of tested FPGA; Tested FPGA working temperature is obtained by temperature test circuit;
The RS232 control command that tested FPGA comes according to test FPGA, completes the functional test of all inner DSP48s multiplier units, and to test FPGA feedback test result; Complete global clock network functional verification; Complete IO output level type and driving force test.
2. FPGA quality diagnosis test macro according to claim 1, is characterized in that: described SMA exports test circuit and comprises 24 road FPGA clock performance test circuits, 24 road IO multilevel type test circuits and 32 road IO driving force test circuits.
3. FPGA quality diagnosis test macro according to claim 1, is characterized in that: described test FPGA is implemented as follows:
(1) after system power-up, test FPGA is configured from exterior arrangement PROM, after having configured, tested FPGA configuration data, comparison data and mask data is read from outside PROM, and tested FPGA configuration data, comparison data and mask data are stored into respectively in outside different SRAM, then enter wait instruction state;
(2) after test FPGA receives control command, decipher is carried out to instruction, according to the instruction specifically received, complete (3) ~ (7) process correspondence test;
(3) configure and retaking of a year or grade functional verification instruction if test FPGA receives tested FPGA, first test FPGA reads tested FPGA configuration data in SRAM, and is configured tested FPGA by SelectMAP parallel interface; After having configured, tested FPGA enters operating state; After 3 seconds, test FPGA carries out retaking of a year or grade by SelectMAP parallel interface to tested FPGA, and back read data is compared in real time with the comparison data deposited in SRAM, mask data, add up discrepant bit, and statistic is sent to PC by a RS232 interface;
(4) if test FPGA receives tested FPGA inner DSP48s multiplier unit functional test instruction, instruction is forwarded to tested FPGA by the 2nd RS232 interface by test FPGA, and pass through the test result of the inner DSP48s multiplier unit of the tested FPGA of the 2nd RS232 interface, by a RS232 interface feedback test result to PC;
(5) if test FPGA receives tested FPGA inner BRAM functional verification instruction, test FPGA writes test data by I/O interface to tested FPGA, and by I/O interface from tested FPGA inner BRAM read test data, add up discrepant bit, and statistic is sent to PC by a RS232 interface;
(6) if test FPGA receives obtain the instruction of tested FPGA working temperature, test FPGA obtains tested FPGA working temperature by temperature test circuit, and Temperature numerical is sent to PC by a RS232 interface;
(7) if test FPGA receives the test instruction of tested FPGA register stage connection, test FPGA is configured tested FPGA by SelectMAP parallel interface, makes tested FPGA be operated in register tandem states; Test FPGA writes test data by I/O interface to tested FPGA, and by I/O interface from tested FPGA read test data, adds up discrepant bit, and statistic is sent to PC by a RS232 interface;
(8) testing FPGA to complete in (3) ~ (7) after a content measurement, enters wait instruction state, then implementation (2).
4. FPGA quality diagnosis test macro according to claim 1, is characterized in that: described tested FPGA is implemented as follows:
(1), after system power-up, tested FPGA is configured by SelectMAP parallel interface by testing FPGA;
(2), after having configured, tested FPGA carries out the functional test of inner DSP48s multiplier unit, after having tested, and logging test results;
(3) tested FPGA carries out global clock network checking, tested FPGA exports master clock by IO, master clock 2 frequency-dividing clock and master clock 10 frequency-dividing clock, often kind of clock all adopts single-ended and difference output, uses oscillograph recording often to plant the frequency values of clock, duty ratio and jitter amplitude;
(4) tested FPGA carries out IO output level type and driving force test, and tested FPGA exports 3 kinds of multilevel type by IO, records the magnitude of voltage of often kind of multilevel type low and high level respectively, and driving force when load is 10K Ω;
(5) after tested FPGA completes (2) ~ (4) test, enter wait instruction state, after tested FPGA receives instruction from the 2nd RS232 interface, decipher is carried out to instruction, if instruction is for obtaining tested FPGA inner DSP48s multiplier unit functional verification result, then tested FPGA is by the 2nd RS232 interface feedback test result, and any operation is not done in other instructions, continues to enter wait instruction state.
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| CN106680698B (en) * | 2015-11-11 | 2023-08-18 | 上海复旦微电子集团股份有限公司 | Multi-station rapid configuration device for FPGA test and configuration method thereof |
| CN109445365B (en) * | 2018-12-27 | 2021-07-09 | 青岛中科青芯电子科技有限公司 | Screening test method of FPGA embedded multiplier |
| CN109709472B (en) * | 2019-01-25 | 2020-12-22 | 华北水利水电大学 | Test system and test method for CFG (field programmable gate array) of FPGA (field programmable gate array) configuration circuit |
| CN113985256A (en) * | 2021-11-01 | 2022-01-28 | 北京中科胜芯科技有限公司 | FPGA life test method |
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