CN105068908B - A kind of building method of functional verification platform for KVM ASIC - Google Patents
A kind of building method of functional verification platform for KVM ASIC Download PDFInfo
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- CN105068908B CN105068908B CN201510452605.9A CN201510452605A CN105068908B CN 105068908 B CN105068908 B CN 105068908B CN 201510452605 A CN201510452605 A CN 201510452605A CN 105068908 B CN105068908 B CN 105068908B
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Abstract
The present invention discloses a kind of building method of the functional verification platform for KVM ASIC, belongs to IC design verifications field；The present invention is by integrating UVM, writing attribute register document, according to the functional verification platform for writing attribute register document and building KVM ASIC, realize the function rule that verification platform is completed by text document, quickly it is efficiently completed building for KVM ASIC functional verification platforms, and the present invention is easy to implement, flow is simple, efficient stable, the construction cycle that KVM ASIC build functional verification platform can be significantly shorten to, functional verification efficiency is improved.
Description
Technical field
The present invention discloses a kind of building method of functional verification platform, belongs to IC design verifications field, specifically one
Plant the building method of the functional verification platform for KVM ASIC.
Background technology
Ic manufacturing technology is developed rapidly, while market is also continuously increased to the demand of high integration product, enters one
Step facilitates the complexity of integrated circuit to be continuously increased.High integration product realizes design energy by using design storm frequency
The significantly lifting of power；But in terms of checking, Current Domestic mainly writes testbench to the checking means of integrated circuit
Orientation is encouraged, although is write orientation test proof scheme and is verified that early investment energy is less and validation test work startup is early, but
It is that demonstration plan is pushed slowly, and is difficult to weigh the completeness verified, can not especially meets the survey of demand high integration product
Examination is required.Therefore, the present invention proposes a kind of building method of the functional verification platform for KVM ASIC, passes through comprehensive UVM
A variety of design verification language such as verification methodology, System Verilog and script, realize and are completed by text document
The function rule of verification platform, is quickly efficiently completed building for KVM ASIC functional verification platforms.This method is easy to implement,
Flow is simple, efficient stable, can significantly shorten to the construction cycle that KVM ASIC build functional verification platform, improves function and tests
Demonstrate,prove efficiency.
UVM, Universal Verification Methodology, generic validation methodology are one with System
Verilog class libraries is the verification platform Development Framework of main body, verifies that engineer can build to have using its Reusable Module and marks
The functional verification environment of standardization hierarchical structure and interface.
KVM is the English head letter abbreviations of keyboard (Keyboard), video display (Video), mouse (Mouse), i.e.,
Switched with a set of or number set keyboard, display and mouse between the multiple host of multiple different operating systems.ASIC,
Application Specific Integrated Circuit english abbreviation, is considered as that one kind is in integrated circuit circle
Special purpose and the integrated circuit designed.KVM ASIC can realize that a user goes to visit using a set of keyboard, mouse, display
Ask and operate the function of more than one main frame.
The content of the invention
The present invention is pushed slowly for existing its demonstration plan of checking means, and is difficult to weigh the completeness verified,
The defect that the test request of demand high integration product can not especially be met is flat there is provided a kind of functional verification for KVM ASIC
The building method of platform, easy to implement, flow is simple, efficient stable, can significantly shorten to KVM ASIC and build functional verification to put down
The construction cycle of platform, improve functional verification efficiency.
Concrete scheme proposed by the present invention is：
A kind of building method of functional verification platform for KVM ASIC, the verification methodology based on UVM, according to KVM
ASIC design standard explanation and internal register explanation, writes attribute register document；
According to attribute register document, the functional verification platform for KVM ASIC is set up：
Have in design transaction pack assembly, KVM ASIC and communicated between different independent submodules, different independent submodules
Agreement is different, according to different communication protocol, using the corresponding packet module of script language calling, generates different
Transaction components；
According to affairs pack assembly, the different corresponding drivers of submodule, monitor are designed, affairs between different submodules are completed
The driving and collection of bag；
Script Automated Design register model is used according to the register and memory of chip explanation, and carried out initial
Change and set；According to the rule of communication design chips verification platform function ginseng between the workflow and submodule of each submodule of chip
Examine model；It is different according to the I/O signals between different submodules, the interface module between different submodules is designed, checking is realized
The connection of platform and KVM ASIC；
Test vector is provided, verification platform is debugged, building for verification platform is completed.
The attribute register document of writing includes writing bit wide, name, operation, address, the data of each internal register
Implication, initial value, wherein operation includes clear operation after readable, writeable, read-only, reading.
The comparator according between affairs pack assembly, in addition to the different submodules of design, in a comparator according to not
Same communication protocol, is the different buffering FIFO of different transaction packets designs and comparison task.
The workflow of one checking assembly driver of the functional verification platform is：While circulations are initially entered, are sentenced
Whether disconnected is reset or limited current state, if so, then sending invalid data, waits rising edge clock, is again introduced into while circulations；
Driven if it is not, then entering time multiplexing date；
Judge current port state, if IDLE, be included into INS_IDLE branches；Otherwise continue to judge port status；If
EOP, then be included into EOP branches；Otherwise continue to judge port status, if INS_IPG, be included into INS_IPG branches, be otherwise included into
Next INS_IDLE branches.
The one of System Verilog, Verilog, Perl language is used in the build process of described functional verification platform
Plant or several combinations.
Usefulness of the present invention is：By the present invention in that completing a variety of with data package template and shell script
Transaction generation, during group intermodule communication protocol changes, it is only necessary to related data is carried out in packet module library
The Attribute domain modification of bag module, script can complete new transaction generation.Verification platform can be used directly
New transaction is tested next time, without as original testbench, remodifying many header files, is carried out whole
The compiling of individual checking and design, then can just be tested；By using attribute register document, script is called to complete
The structure of register model.When changing attribute register, it is only necessary to re-call script and generate new register mould
Type.Therefore, control register attribute documents are passed through, it is possible to the register and memory that entirely designs in verification platform
Mirror image is managed, and is reduced mistake, is improved operating efficiency.
Brief description of the drawings
Fig. 1 is KVM ASIC verification platform block schematic illustrations；
The workflow schematic diagram of the driver of Fig. 2 verification platforms of the present invention.
Embodiment
With reference to accompanying drawing, the present invention will be further described.
A kind of building method of functional verification platform for KVM ASIC, the verification methodology based on UVM, according to KVM
ASIC design standard explanation and internal register explanation, writes attribute register document；It is described to write attribute register document
Including writing the bit wide of each internal register, name, operation, address, data implication, initial value, wherein operation include it is readable, can
Write, it is read-only, read after clear operation；For memory, data bit width, depth, operation, address width, block address, initial value are write
Deng；Such as following attribute register document：
According to attribute register document, the functional verification platform for KVM ASIC is set up：
Communication protocol is different between having different independent submodules in design transaction pack assembly, KVM ASIC, according to
Different communication protocol, using the corresponding packet module of script language calling, generates different transaction components；
According to affairs pack assembly, the different corresponding drivers of submodule, monitor are designed, affairs between different submodules are completed
The driving and collection of bag；
According to the register and memory of chip explanation using script Automated Design design register model, and carry out
Initialize installation；According to the rule of communication design chips verification platform work(between the workflow and submodule of each submodule of chip
Can reference model；It is different according to the I/O signals between different submodules, the interface module between different submodules is designed, is realized
The connection of verification platform and KVM ASIC；
Test vector is provided, verification platform is debugged, building for verification platform is completed.
In addition, in the functional verification platform build process of the above, according to affairs pack assembly, may also include the different submodules of design
Comparator between block, is that different transaction packets design different buffering FIFO in a comparator according to different communication protocol
And comparison task.
Many kinds of languages of System Verilog, Verilog, Perl can be used in the build process of function above verification platform
The combination of speech.
The workflow of one checking assembly driver of the functional verification platform is：While circulations are initially entered, are sentenced
Whether disconnected is reset or limited current state, if so, then sending invalid data, waits rising edge clock, is again introduced into while circulations；
Driven if it is not, then entering time multiplexing date；
Judge current port state, if IDLE, be included into INS_IDLE branches；Otherwise continue to judge port status；If
EOP, then be included into EOP branches；Otherwise continue to judge port status, if INS_IPG, be included into INS_IPG branches, be otherwise included into
Next INS_IDLE branches.
Claims (5)
1. a kind of building method of functional verification platform for KVM ASIC, the verification methodology based on UVM, it is characterized in that：
According to KVM ASIC design standard explanation and internal register explanation, attribute register document is write；
According to attribute register document, the functional verification platform for KVM ASIC is set up：
There is communication protocol between different independent submodules, different independent submodules in design transaction pack assembly, KVM ASIC
It is different, according to different communication protocol, using the corresponding packet module of script language calling, generate different
Transaction components；
According to affairs pack assembly, transaction packet between the different corresponding drivers of submodule, monitor, the different submodules of completion is designed
Driving and collection；
Script Automated Design register model is used according to the register and memory of chip explanation, and carries out initialization and is set
Put；Mould is referred to according to the rule of communication design chips verification platform function between the workflow and submodule of each submodule of chip
Type；It is different according to the I/O signals between different submodules, the interface module between different submodules is designed, verification platform is realized
With KVM ASIC connection；
Test vector is provided, verification platform is debugged, building for verification platform is completed.
2. the building method of a kind of functional verification platform for KVM ASIC according to claim 1, it is characterized in that institute
State write attribute register document include writing the bit wide of each internal register, it is name, operation, address, data implication, initial
Value, wherein operation includes clear operation after readable, writeable, read-only, reading.
3. a kind of building method of functional verification platform for KVM ASIC according to claim 1 or 2, it is characterized in that
According to the comparator between affairs pack assembly, in addition to the different submodules of design, in a comparator according to different communication protocol,
For the different buffering FIFO of different transaction packet designs and comparison task.
4. the building method of a kind of functional verification platform for KVM ASIC according to claim 3, it is characterized in that institute
The workflow for stating a checking assembly driver of functional verification platform is：While circulations are initially entered, are determined whether
Reset or limited current state, if so, then sending invalid data, wait rising edge clock, are again introduced into while circulations；If it is not, then
Into time multiplexing date driving；
Judge current port state, if IDLE, be included into INS_IDLE branches；Otherwise continue to judge port status；If EOP,
It is included into EOP branches；Otherwise continue to judge port status, if INS_IPG, be included into INS_IPG branches, be otherwise included into next
INS_IDLE branches.
5. a kind of building method of functional verification platform for KVM ASIC according to claim 1 or 4, it is characterized in that
The combination of one or both of Verilog or Perl language is used in the build process of described functional verification platform.
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| CN112560372B (en) * | 2020-11-27 | 2022-10-21 | 山东云海国创云计算装备产业创新中心有限公司 | Chip prototype verification method, device, equipment and medium |
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