CN112597719A - Data network design verification method and device and verification equipment - Google Patents
Data network design verification method and device and verification equipment Download PDFInfo
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Abstract
The disclosure provides a data network design verification method, a data network design verification device and verification equipment. The data network design verification method comprises the following steps: constructing a data transmission layer model aiming at the function module of the measured data network; arranging chip design functional units in the data transmission layer model to construct a data bus system; and performing data transmission verification on the data bus system based on the first test sequence. The chip design functional unit comprises a clock domain crossing interface module, a voltage domain crossing interface module or a relay unit.
Description
Technical Field
The embodiment of the disclosure relates to a data network design verification method, a data network design verification device and verification equipment.
Background
With the increasing complexity of digital integrated circuit systems, the number and the types of functional modules constituting a System-on-a-Chip (SoC) are increasing, and the data interaction network between the modules in the System is also becoming more and more complex. In order to quickly adapt to different system applications and integration requirements, currently, a network-on-chip data bus with scalable parameters and reconfigurable topological structure is mostly adopted in a large-scale integration system. At present, the verification process of the on-chip data network in the large-scale integrated circuit generally adopts a mode of respectively verifying at a module level and a system level. However, the verification at the module level cannot be guaranteed to be consistent with the scene when the actual chip is designed, and thus the verification is not sufficient. For system-level verification, problems of too long simulation time, limited verification scene and the like are inevitable due to the complexity of the integrated circuit.
Disclosure of Invention
The disclosure provides a data network design verification method, a data network design verification device and verification equipment, which are used for relieving the pressure of system level verification and improving the chip verification efficiency while performing more comprehensive and sufficient data verification on a functional module in the chip design process.
According to an aspect of the present disclosure, there is provided a data network design verification method, including: constructing a data transmission layer model aiming at the function module of the measured data network; arranging chip design functional units in the data transmission layer model to construct a data bus system; and performing data transmission verification on the data bus system based on the first test sequence.
According to another aspect of the present disclosure, there is provided a data network design verification apparatus including: a verification system construction unit configured to construct a data transmission layer model for the data network function module under test, and arrange a chip design function unit in the data transmission layer model to construct a data bus system; and a verification unit configured to perform data transmission verification on the data bus system based on the first test sequence.
According to still another aspect of the present disclosure, there is provided an authentication apparatus including: a processor; and a memory, wherein the memory has computer readable code stored therein. The computer readable code, when executed by a processor, performs the data network design verification method as described above.
According to the data network design verification method, the data network design verification device and the verification equipment, aiming at the tested data network function module, the chip design function unit is arranged on the basis of the data transmission layer model to serve as a data bus system to be verified, so that the verification environment of the tested equipment is closer to the verification scene of the tested equipment in the actual chip design, and the data verification can be carried out on the tested data network function module more comprehensively and fully. Meanwhile, more sufficient verification of the functional module is beneficial to relieving the pressure of system-level verification, namely, the functional module is more sufficiently verified before the system-level verification is carried out, so that the chip verification efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 illustrates a schematic flow chart diagram of a data network design verification method provided by the present disclosure;
FIG. 2 shows a schematic diagram of a data transport layer model;
FIG. 3 shows a schematic diagram of a built data bus system;
FIG. 4 shows a schematic diagram of a first validation pass;
FIG. 5A shows a schematic diagram of an extended data bus system including a memory module;
FIG. 5B shows a schematic diagram of an extended data bus system including a high speed input/output module;
FIG. 5C shows a schematic diagram of an extended data bus system including a direct memory access module;
FIG. 6 is a schematic diagram illustrating multi-chip interconnect verification;
FIG. 7 shows a schematic block diagram of a data network design validation apparatus provided by the present disclosure;
fig. 8 shows a schematic block diagram of an authentication device provided by the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely exemplary of some, and not all, of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without any inventive step, are intended to be within the scope of the present disclosure.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
The present disclosure provides a method for data design verification of functional modules in an integrated circuit, such as a system-on-a-chip, to perform more realistic data transmission verification of a device under test.
Fig. 1 shows a schematic flowchart of a data network design verification method provided by an embodiment of the present disclosure, which includes steps S110 to S130. As shown in fig. 1, first, in step S110, a data transmission layer model is constructed for the measured data network function module. A DUT is a functional module of a data network Under Test (DUT). For example, the data network function module under test may be a module within a currently designed chip for performing a certain function. For convenience of description, the data network function module under test is hereinafter referred to as a device under test.
The data transfer layer model built for the device under test may be based on the data transfer structure of the device described in a hardware language. The Hardware Description Language (HDL) is a Language for describing the Hardware behavior, the structure and the data stream of an electronic system. With this language, the design of digital circuitry can be described layer by layer from top to bottom (i.e., abstract to concrete), with hierarchically described modules representing extremely complex digital systems. Then, an electronic design automation tool can be used to perform simulation verification layer by layer, and then the module combination which needs to become the actual circuit of the chip is converted into a gate-level circuit netlist. And finally, converting the netlist into a specific circuit wiring structure to be realized by using an automatic layout and wiring tool of an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).
According to embodiments of the present disclosure, a data transport layer model may include data routing nodes and data channels of a device under test. Fig. 2 shows a schematic diagram of a data transport layer model. As shown in fig. 2, the data transport layer model corresponds to a structure within a solid line box, which includes data routing nodes represented by black dots and data channels represented by dashed lines. In addition, in the process of data verification of the data transmission layer model, an interface module for data interaction with the tested device needs to be constructed. For example, the interface modules may be divided into Master devices (Master, M) and Slave devices (Slave, S), and three types of Master device interface modules (denoted as M-A to M-C) and three types of Slave devices (denoted as S-A to S-C) connected to the daA transport layer model are schematically illustrated in fig. 2 as an example. The master device may refer to a device that issues a specific operation, and the slave device may refer to a device that responds to the operation. It can be understood that the data transmission layer model shown in fig. 2 is only a schematic structure, and the constructed data transmission layer model may be different for different devices under test.
Next, as shown in fig. 1, the data network design verification method provided in the embodiment of the present disclosure further includes: at step S120, arranging chip design functional units in the data transmission layer model to construct a data bus system; in step S130, data transmission verification is performed on the data bus system based on the first test sequence.
According to the embodiment of the present disclosure, a chip design functional unit refers to a unit that is inserted into a system according to chip design requirements in a process of constructing a system-on-chip by using a device under test. This is because, in the overall design of the chip, the devices to be tested may be distributed at various positions of the chip, and when the devices to be tested are integrated into the SoC, in order to meet the requirement of the back-end physical layout design, the modules are generally divided into the whole SoC. The various modules in the on-chip data network, such as the device under test, will be divided into different physical modules, so it is necessary to insert these functional units accordingly in the process of building the SoC to implement the functional design of the whole chip.
In view of this, the present disclosure proposes to arrange chip design functional units to construct a data bus system in the process of verifying a device under test, i.e., according to the design requirements of the whole chip. In other words, the chip design functional units arranged in the data transmission layer model are based on the layout of the device under test in the whole chip design, so that the data bus system with the chip design functional units arranged is closer to the layout structure of the device under test in the final chip, and thus, the data transmission verification on the chip is more real and sufficient. On the basis, when the tested device subjected to more real and sufficient data transmission verification is used for system-level chip verification, the reliability and the stability are higher, so that the verification pressure of the system-level verification is favorably relieved, and the chip design verification efficiency is improved.
The inventor has noted that, regarding the specific form of the functional unit of the chip design, on one hand, in the system-on-chip design, it is considered that the device under test may span different clock domains and power domains, and therefore, it is necessary to insert a corresponding clock synchronization circuit and a corresponding voltage conversion circuit into the data channel. On the other hand, in order to meet the limitation of timing requirements and ensure that the chip reaches the expected operating frequency, a relay unit (repeater) or a synchronization unit needs to be inserted into a part with a longer distance from the interface module to the data routing node and the data routing node.
Based on the above, in some embodiments according to the present disclosure, the chip design functional unit may be a cross-clock domain interface module, in which case constructing the data bus system includes: according to the clock design of the data routing node in the chip, a clock domain crossing interface module is arranged aiming at the data routing node. In some embodiments according to the present disclosure, the chip design functional unit may also be a cross-voltage domain interface module, in which case constructing the data bus system comprises: the voltage domain crossing interface module is arranged for the data routing node according to the voltage design of the data routing node in the chip. In still other embodiments according to the present disclosure, the chip design function unit may be a relay unit, in which case constructing the data bus system includes: and inserting the relay unit into the data channel according to the path delay.
In some embodiments, the chip design functional unit disposed in the data transmission layer model may include the clock domain crossing interface module, the voltage domain crossing interface module, and the relay unit, and a plurality of chip design functional units may be disposed according to actual chip design requirements. It should be understood that the chip design functional unit according to the present disclosure may also be other functional units besides the clock domain crossing interface module, the voltage domain crossing interface module and the relay unit, for example, a unit that assists in realizing the whole chip function in consideration of the whole layout design and the like in the process of designing the system-on-chip based on the device under test. For convenience of description, the above-mentioned cross-clock domain interface module and the cross-voltage domain interface module are hereinafter described as cross-clock/voltage domain interface modules.
As an example, fig. 3 shows a schematic diagram of a built data bus system, and a chip design functional unit according to the present disclosure and the data bus system will be described in detail below with reference to fig. 3.
As shown in fig. 3, in the data transmission layer model of the device under test, for data channels indicated by dotted lines between data routing nodes, a plurality of relay units (relay unit 0 to relay unit 8) are arranged to meet timing requirements of the device under test in a system on a chip, where the relay units may be arranged according to path delays between the data channels. In addition, in the data transmission layer model of the tested device, a plurality of cross clock/voltage domain interface modules are arranged aiming at the data routing nodes. Illustratively, the cross-clock domain interface module may be represented as VDCI0 in fig. 3, and the cross-voltage domain interface module may be VDCI1 in fig. 3. Wherein, the interface module crossing the clock/voltage domain can be arranged according to the clock/voltage design of the data routing node in the chip.
In addition, according to an embodiment of the present disclosure, constructing the data bus system may further include building a bare housing interface module driven by the universal validation component. The hollow shell interface module is used for simulating a functional module with data interaction with the tested equipment. A plurality of shell interface modules connected to a built data bus system is schematically shown in fig. 3. The shell interface (shell view interface) module is an interface between the device under test and an external device (such as a Master device, a Slave device) therein. In the stage of verifying the device under test, only the data consistency and the transaction quantity of the device under test are concerned, and the data transmission of other functional modules performing data interaction with the device under test is not concerned at present. As an example, a bare housing interface module that simulates or emulates a functional module having data interaction with a device under test may be driven by a Verification Component (UVM Verification Component, UVC) in Universal Verification Methodology (UVM). The advantage of this driving method is that the simulation time is fast, and it is possible to realize high verification coverage by flexibly controlling each master device to issue a specific operation and each slave device to perform a specific response.
After the data bus system as shown in fig. 3 has been built for the device under test, it can be data verified based on the test sequence. Due to the fact that the data bus system constructed according to the method of the present disclosure includes the chip design function units (the relay unit, the VDCI0/1, etc.), the structure and the composition structure of the device to be tested at the real level of the SoC can be verified, the operation quality of the device to be tested after the device to be tested is integrated into the SoC can be timely verified at the function module verification stage, and possible problems of the device to be tested can be found. For example, in the case that the data transmission verification of the device under test does not meet the expected verification standard, the design scheme can be timely improved based on the data verification result, and the potential design problem is prevented from lagging to the system level verification. Therefore, the verification design mode considering the whole layout of the chip for the tested equipment can improve the efficiency and quality of system level verification, quickly locate problems and accelerate the progress of subsequent stages of chip development, manufacturing and the like, and is extremely favorable in practical application.
In at least one example, verifying data transmission to a data bus system based on a first test sequence (step S130) includes, according to an embodiment of the present disclosure: the method comprises the steps of building a first validation path of the data bus system based on components in the universal validation framework, and validating data transmission of the data bus system based on a first test sequence by using the first validation path. For example, a component in a generic verification framework may include at least one of: an agent, a monitor, a checker, a scoreboard, or a sequencer.
As an example, the universal verification framework may be the above UVM, and after the data bus system as shown in fig. 3 is constructed, a corresponding verification environment, i.e. a verification path, may be built based on the UVM. For example, components such as a checker (checker) or a scoreboard (scoreboard) are added according to the need of authentication, so as to achieve the purpose of authenticating data transactions of the data bus system. Fig. 4 shows a schematic diagram of a first validation path, and the process of validating the data bus system shown in fig. 3 will be described in detail below in conjunction with fig. 4.
In fig. 4, the structure of a daA bus system to be authenticated may refer to fig. 3, which may be connected with a plurality of master devices (M-a to M-C) and a plurality of slave devices (SA to S-D) through, for example, an interface module. For a first test sequence for testing, it may be generated by a virtual sequencer and input to the data bus system via the UVM ENV component. In addition, a memory model and a score board can be set according to verification requirements so as to record and evaluate data verification effects.
The verification path in fig. 4 is based on a UVM verification framework, where a master device is driven by a UVC to initiate read/write access operations of data, and a slave device may also be driven by the UVC to passively accept accesses from a bus and perform corresponding responses as a behavior model. In addition, the authentication path in fig. 4 may also apply an ENV component (i.e., UVM _ ENV component) in the UVM authentication framework, which includes a register model, UVCs of corresponding modules, including an agent (agent), a monitor (monitor), a checker (checker), a score board (scoreboard), and the like. For example, the data verification may include write data detection, read data detection, transmission/reception amount detection, validity detection, and consistency detection.
Further, a top scoring board (top scoreboard) for the device under test may also be applied, for example, the top scoring board may be developed for monitoring data transactions from the slave device for one-to-one matching with data transactions recorded in the memory model for system-level data paths and concerns. For system level design, a UVM sequencer with master bus transactions (master bus transactions) as parameters may be added for the top level scoreboard for transmitting bus transactions between platform components. At this time, the test case can be extended through the parent class of the basic test case component. Finally, the top scoring board may perform data checking on the entire data path, and perform cross check (cross check) with data in the memory model to complete the overall data verification.
While the process of verifying a data bus system based on a test sequence is described above in conjunction with fig. 4, it should be understood that the verification path may be based on other verification platforms or verification frameworks besides UVM, and is not limited herein.
According to the data bus system built aiming at the tested equipment, the data bus system is closer to the structure of the tested equipment in chip design, so that the verification aiming at the data bus system is more sufficient and comprehensive, and the subsequent rapid verification of a system-level hardware structure is facilitated.
According to the data network design verification method of the present disclosure, in at least one example, the method may further include: an additional function module is added to the data bus system to construct an extended data bus system. In the process of verifying the device under test, not only the data path of the device under test itself needs to be verified, but also the requirements for verifying some additional functional modules connected with the device under test, such as read-write access and data interaction, exist. For example, the additional function module may be an input/output module, and the extended data bus system based on the extension of the input/output module may realize further verification of data interaction between the device under test and the input/output module.
According to the data network design verification method of the present disclosure, in at least one example, the method may further include: and constructing a second verification path aiming at the additional function module based on the components in the general verification framework, and verifying the data transmission of the extended data bus system based on the second test sequence by utilizing the second verification path. Specifically, the process of verifying data transmission of the extended data bus system based on the second test sequence may refer to the process of verifying the data bus system, where a new test sequence may be constructed for an added additional function module or a separate score board or other components may be provided for data interaction verification, which is not repeated here.
As an example, the additional function module may be in the form of a Register Transfer Level (RTL) that focuses further on the data transfer path to the Register Level than the dummy interface. As other examples, the additional functional modules may also be in other forms, such as gate level forms.
According to some embodiments of the present disclosure, the additional functional module may be a memory module, and fig. 5A shows a schematic diagram of an extended data bus system including the memory module. The data-on-chip network in fig. 5A may be the data bus system constructed in fig. 3, wherein, since the added memory module is in an RTL form, constructing an extended data bus system may further include: the hollow shell interface module in fig. 3 is modified to delete the slave device corresponding to the memory module from the hollow shell interface module, that is, the memory described in the form of the hollow shell interface is modified into the form of an RTL entity, and is driven in the RTL manner. By way of example, the Memory module may include, but is not limited to, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR), a Secure Digital (SD) Memory, a High Bandwidth Memory (HBM), a NAND flash Memory (NAND), and the like.
According to further embodiments of the present disclosure, the additional functional module may be a high speed input/output module, and fig. 5B shows a schematic diagram of an extended data bus system including the high speed input/output module. Likewise, the data network on chip in fig. 5B may be the data bus system constructed in fig. 3, wherein, since the added high-speed input/output module is in an RTL form, constructing an extended data bus system may further include: the bare housing interface module in fig. 3 is modified to delete the slave device corresponding to the high speed input/output module from the bare housing interface module, and a host driver (host driver) verification component is further arranged to drive the high speed input/output module to perform data transmission with the data bus system. By way of example, the high-speed input/output module includes, but is not limited to, a high-speed Serial computer expansion Bus (PCIE), a Serial Advanced Technology Attachment (SATA) interface, a Universal Serial Bus (USB), an Ethernet Access Controller (EMAC) interface, and the like.
According to still further embodiments of the present disclosure, the additional functional module may be a direct memory access module, and FIG. 5C shows a schematic diagram of an extended data bus system including a direct memory access module. Likewise, the data-on-chip network in fig. 5C may be the data bus system constructed in fig. 3, wherein constructing the extended data bus system may further include, since the increased direct memory access module is in an RTL form: the bare housing interface module of fig. 3 is modified to delete the master device corresponding to the direct memory access module from the bare housing interface module, and the host driver verification component is further arranged to drive the direct memory access module to perform data transfer with the data bus system.
In other embodiments according to the present disclosure, the additional functional module may also include a plurality of the above-mentioned memory module, high-speed input/output module, direct memory access module, or may also be other functional modules whose targets are verified, and is not limited herein.
By building the expanded data bus system with the emphasis, the read-write access between the data bus of the tested equipment and the memory, the I/O module and the like can be focused, the performance analysis during data interaction can be carried out, the access among a plurality of equipment can be realized, and the like. This enables more targeted data verification for the device under test. Furthermore, because the extended additional functional module is in an RTL form, the verification aiming at the tested device is closer to the verification environment of the tested device in system level verification, the problem in chip design can be found in time, and the chip design efficiency can be improved.
Furthermore, for large socs, it is common to include multiple cores (cores), i.e., a multi-chip interconnect, where a multi-chip may refer to two or more chips. Therefore, it is necessary to verify the correctness and stability of the basic data path of the device under test during interconnection of multiple chips.
According to the data network design verification method of the present disclosure, in at least one example, the method may further include: constructing another data transmission layer model aiming at another tested data network functional module; arranging the chip design functional unit in another data transmission layer model to construct another data bus system; connecting the data bus system with another data bus system by using an interconnection module; generating a third test sequence according to address space division between the data bus system and the other data bus system; and performing data transmission verification on the data bus system and the other data bus system based on the third test sequence.
Fig. 6 is a schematic diagram of multi-chip interconnect verification, which schematically illustrates a scenario of two-chip interconnect, wherein a data system bus 0 and another data bus system 1 are connected through an interconnect module (TOS) to implement data communication between the two systems, thereby forming a multi-chip interconnect verification path.
For a multi-chip interconnected verification environment such as that of FIG. 6, a third test case for data access between the multiple chips may be developed. The third test case may be generated according to the division of the address space, and the current data bus system 0 initiates data read-write access to the other data bus systems 1 that implement network interconnection based on the third test case, so as to perform corresponding data access verification. In addition, if the function of the master device bus/the slave device bus is distinguished when the data bus system per se is interconnected with multiple chips, the control flow between the master device bus and the slave device bus can be further verified.
The verification scheme shown in fig. 6 can be used as a prior step of system-on-chip interconnection verification, quickly start interconnection of important modules in the whole data path, share pressure for the following whole chip verification, and is beneficial to saving time and improving verification efficiency.
It is to be appreciated that in at least one embodiment, the various elements of FIGS. 2-6 may be, for example, "hardware elements" modeled using a Hardware Description Language (HDL).
According to another aspect of the present disclosure, a data network design verification apparatus is also provided. Fig. 7 shows a schematic block diagram of a data network design verification apparatus provided in at least one embodiment of the present disclosure, wherein the data network design verification apparatus 1000 may include a verification system construction unit 1010 and a verification unit 1020. The apparatus 1000 provided by the present disclosure may be used to implement the data network design verification method provided by the present disclosure.
The verification system building unit 1010 may be configured to build a data transmission layer model in which chip design function units are arranged to build a data bus system for the data network function module under test. According to the embodiment of the disclosure, the tested data network function module may be a tested Device (DUT) whose data transmission needs to be verified in the chip design process, for example, a certain function module in a chip. The structure of the data transfer layer model can be referred to fig. 2, and the structure of constructing the data bus system can be referred to fig. 3.
The validation unit 1020 may be configured to perform data transfer validation on the data bus system based on the first test sequence. The verification process may refer to the description above in connection with fig. 4.
In at least one example, a data transport layer model includes data routing nodes and data channels of a data network function under test, according to an embodiment of the present disclosure.
According to the embodiment of the present disclosure, in at least one example, the chip design functional unit includes a cross-clock domain interface module, and the verification system building unit 1010 may be configured to arrange the cross-clock domain interface module for the data routing node according to the clock design of the data routing node in the chip.
According to an embodiment of the present disclosure, in at least one example, the chip design function unit includes a voltage domain interface module, and the verification system building unit 1010 may be configured to arrange the voltage domain interface module for the data routing node according to a voltage design of the data routing node in the chip.
In at least one example, the chip design function unit includes a relay unit, and the verification system construction unit 1010 may be configured to insert the relay unit in the data channel according to the path delay according to the embodiment of the present disclosure.
In at least one example, according to the embodiment of the present disclosure, the verification system building unit 1010 may be further configured to build an empty shell interface module driven by the universal verification component, wherein the empty shell interface module is used for simulating a functional module having data interaction with the tested data network functional module.
In at least one example, according to embodiments of the present disclosure, the validation unit 1020 may be configured to construct the first validation path of the data bus system based on components in a generic validation framework, for example, the components in the generic validation framework including at least one of: an agent, monitor, checker, scoreboard or sequencer; and verifying the data transmission of the data bus system based on the first test sequence using the first verification path.
In at least one example, the data network design verification apparatus 1000 may further include an extension unit 1030 configured to add an additional functional module in the data bus system to construct an extended data bus system according to an embodiment of the present disclosure. The validation unit 1020 may be further configured to perform data transfer validation on the extended data bus system based on the second test sequence.
In at least one example, the additional functional module is in the form of a register transfer stage, according to an embodiment of the present disclosure.
According to an embodiment of the present disclosure, in at least one example, the additional function module is a memory module, wherein the extension unit 1030 may be further configured to modify the bare housing interface module to delete a slave device corresponding to the memory module from the bare housing interface module.
According to an embodiment of the present disclosure, in at least one example, the additional function module is a high-speed input/output module, wherein the extension unit 1030 may be further configured to modify the bare housing interface module to delete the slave device corresponding to the high-speed input/output module from the bare housing interface module; and arranging a host driver verification component to drive the high-speed input/output module to perform data transmission with the data bus system.
According to an embodiment of the present disclosure, in at least one example, the additional function module is a direct memory access module, wherein the extension unit 1030 may be further configured to modify the bare housing interface module to delete the master device corresponding to the direct memory access module from the bare housing interface module; and arranging a host driver verification component to drive the direct memory access module to perform data transmission with the data bus system.
In at least one example, according to embodiments of the present disclosure, the verification unit 1020 may be further configured to construct a second verification path for the additional function module based on the components in the generic verification framework; the data transmission of the extended data bus system is verified based on the second test sequence using the second verification path.
According to an embodiment of the present disclosure, in at least one example, the verification system building unit 1010 may also build another data transmission layer model for another tested data network function module, and arrange the chip design function unit in the another data transmission layer model to build another data bus system.
According to an embodiment of the present disclosure, in at least one example, the data network design verification apparatus 1000 may further include an interconnection verification unit 1040 configured to connect the data bus system with another data bus system using an interconnection module; generating a third test sequence according to address space division between the data bus system and the other data bus system; and performing data transmission verification on the data bus system and the other data bus system based on the third test sequence.
With regard to the specific steps performed by the data network design verification apparatus 1000 and the flow thereof, reference may be made to the above description of the data network design verification method according to the present disclosure, which is not repeated here.
According to the data network design verification device 1000 of the embodiment of the disclosure, since the chip design functional units (the relay unit, the VDCI0/1, etc.) are included in the constructed data bus system, the architecture and the composition structure of the device to be tested at the SoC real level can be verified, so that the operation quality of the device to be tested after being integrated into the SoC can be timely verified at the functional module verification stage, and possible problems of the device to be tested can be found. For example, in the case that the data transmission verification of the device under test does not meet the expected verification standard, the design scheme can be timely improved based on the data verification result, and the potential design problem is prevented from lagging to the system level verification. Therefore, the verification design mode considering the whole layout of the chip for the tested equipment can improve the efficiency and quality of system level verification, quickly locate problems and accelerate the progress of subsequent stages of chip development, manufacturing and the like, and is extremely favorable in practical application.
According to still another aspect of the present disclosure, there is also provided an authentication apparatus. Fig. 8 shows a schematic block diagram of an authentication device provided by the present disclosure, and as shown in fig. 8, an authentication device 2000 may include a processor 2010 and a memory 2020. The memory 2020 has stored therein computer readable code, which when executed by the processor 2020, may perform a data network design verification method as described above.
Those skilled in the art will appreciate that the disclosure of the present disclosure is susceptible to numerous variations and modifications. For example, the various devices or components described above may be implemented in hardware, or may be implemented in software, firmware, or a combination of some or all of the three.
Further, while the present disclosure makes various references to certain elements of a system according to embodiments of the present disclosure, any number of different elements may be used and run on a client and/or server. The units are merely illustrative and different aspects of the systems and methods may use different units.
Flow charts are used in this disclosure to illustrate steps of methods according to embodiments of the disclosure. It should be understood that the preceding and following steps are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Also, other operations may be added to the processes.
It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by a program instructing relevant hardware, and the program may be stored in a computer readable storage medium, such as a read only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.
Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The foregoing is illustrative of the present disclosure and is not to be construed as limiting thereof. Although a few exemplary embodiments of this disclosure have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is to be understood that the foregoing is illustrative of the present disclosure and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.
Claims (16)
1. A data network design verification method comprises the following steps:
constructing a data transmission layer model aiming at the function module of the measured data network;
arranging chip design functional units in the data transmission layer model to construct a data bus system; and
and performing data transmission verification on the data bus system based on the first test sequence.
2. The method of claim 1, wherein the data transport layer model comprises data routing nodes and data channels of the data network function under test.
3. The method of claim 2, wherein the chip design functional unit comprises a cross-clock domain interface module, the building a data bus system comprising:
and arranging the clock domain crossing interface module aiming at the data routing node according to the clock design of the data routing node in a chip.
4. The method of claim 2, wherein the chip design functional unit comprises a cross-voltage domain interface module, the building a data bus system comprising:
arranging the cross-voltage domain interface module for the data routing node according to a voltage design of the data routing node in a chip.
5. The method of claim 2, wherein the chip design function includes a relay unit, the building a data bus system includes:
and inserting the relay unit into the data channel according to the path delay.
6. The method of any of claims 3-5, wherein the building a data bus system further comprises:
and building a hollow shell interface module driven by a universal verification assembly, wherein the hollow shell interface module is used for simulating one or more functional modules with data interaction with the tested data network functional module.
7. The method of claim 6, further comprising:
providing additional functional modules in the data bus system to build an extended data bus system; and
and performing data transmission verification on the extended data bus system based on a second test sequence.
8. The method of claim 7, wherein the additional functional module is in the form of a register transfer stage.
9. The method of claim 7, wherein the additional functional module is a memory module, wherein the constructing an extended data bus system further comprises:
modifying the bare housing interface module to delete a slave device corresponding to the memory module from the bare housing interface module.
10. The method of claim 7, wherein the additional functional module is a high speed input/output module, wherein the building an extended data bus system further comprises:
modifying the bare housing interface module to delete the slave device corresponding to the high-speed input/output module from the bare housing interface module; and
a host driver authentication component is arranged to drive the high speed input/output module for data transfer with the data bus system.
11. The method of claim 7, wherein the additional functional module is a direct memory access module, wherein the building an extended data bus system further comprises:
modifying the bare housing interface module to delete the master device corresponding to the direct memory access module from the bare housing interface module; and
a host driver authentication component is arranged to drive the direct memory access module to perform data transfer with the data bus system.
12. The method of claim 7, wherein the verifying the data transfer to the extended data bus system based on the second test sequence comprises:
building a second verification path for the additional function module based on components in a generic verification framework; and
verifying, with the second verification path, data transmission of the extended data bus system based on the second test sequence.
13. The method of claim 1, wherein the verifying the data transfer to the data bus system based on the first test sequence comprises:
building a first validation path of the data bus system based on components in a universal validation framework, wherein the components in the universal validation framework include at least one of: an agent, monitor, checker, scoreboard or sequencer; and
verifying, with the first verification path, data transmission of the data bus system based on the first test sequence.
14. The method of claim 1, further comprising:
constructing another data transmission layer model aiming at another tested data network functional module;
arranging chip design functional units in the other data transmission layer model to construct another data bus system;
connecting the data bus system with the other data bus system by using an interconnection module;
generating a third test sequence according to address space division between the data bus system and the other data bus system; and
and performing data transmission verification on the data bus system and the other data bus system based on the third test sequence.
15. A data network design verification apparatus, comprising:
a verification system construction unit configured to construct a data transmission layer model in which a chip design function unit is arranged to construct a data bus system, for a measured data network function module; and
a validation unit configured to perform data transmission validation on the data bus system based on a first test sequence.
16. An authentication device comprising:
a processor; and
memory, wherein the memory has stored therein computer readable code which, when executed by the processor, performs a data network design verification method as claimed in any one of claims 1-14.
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