CN115345098B - SOC verification method and device, electronic equipment and storage medium - Google Patents
SOC verification method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The application provides an SOC verification method, an SOC verification device, electronic equipment and a storage medium, and relates to the field of chip verification, wherein the method comprises the following steps: the method comprises the steps of representing data transmission characteristics of a host terminal based on transmission characteristic parameters, constructing a host terminal model of the SOC, wherein the transmission characteristic parameters comprise transmission distance parameters, and the transmission distance parameters represent time intervals between a time point when the host terminal initiates one transmission operation and the last transmission operation; simulating a data transmission process of a host terminal based on the host terminal model; based on the data transmission process, the SOC is verified, and the method provided by the embodiment of the application can be used for carrying out high-level modeling on the behavior level of the Master transmission characteristic by newly introducing the designed data transmission characteristic, so that the microscopic transmission characteristic of the Master is accurately represented in microcosmic, and the SOC verification precision is improved.
Description
Technical Field
The present application relates to the field of chip verification, and in particular, to an SOC verification method, apparatus, electronic device, and storage medium.
Background
The SOC is a System On Chip (SOC), i.e., the main functions of the System are integrated onto a Chip, and at least include a processor core. Before the SOC is put into use, the SOC needs to be verified to ensure the performance and the reliability of the SOC. In the prior art, only a constraint parameter interface for the AXI Master can be provided, and the problem of low verification accuracy is only achieved by constraining the transmission behaviors of the AXI Master, wherein the transmission behaviors sent by the Master generally meet the design specification requirements for the Master from macroscopic view, but the microscopic transmission characteristics of each Master cannot be verified.
Disclosure of Invention
Based on the above, an object of the embodiments of the present application is to provide an SOC verification method, apparatus, electronic device, and storage medium, by newly introducing designed data transmission features to perform high-level modeling of behavior levels on Master transmission features, and accurately characterize microscopic transmission features of a Master in a microscopic manner, thereby improving SOC verification accuracy.
In a first aspect, an embodiment of the present application provides an SOC verification method, including:
the method comprises the steps of representing data transmission characteristics of a host terminal based on transmission characteristic parameters, constructing a host terminal model of the SOC, wherein the transmission characteristic parameters comprise transmission distance parameters, and the transmission distance parameters represent time intervals between a time point when the host terminal initiates one transmission operation and the last transmission operation;
simulating a data transmission process of a host terminal based on the host terminal model;
and verifying the SOC based on the data transmission process.
In the implementation process, the high-level modeling of the behavior level can be performed on the Master transmission characteristic based on the data transmission characteristic of the introduced design, namely the transmission distance parameter, so as to represent the microscopic behavior of the Master in data transmission, thereby realizing the control mechanism of the microscopic transmission behavior of the AXI Master and improving the accuracy of SOC verification.
In an alternative embodiment, the simulating the data transmission process of the host based on the host model may include:
generating constraint data according to the design parameter information of the host end;
configuring input parameters of the host model based on the constraint data, and generating a read-write data packet;
and sending the read-write data packet to the host model based on the input parameters so as to simulate the data transmission process of the host.
In an alternative embodiment, the sending the read-write data packet to the host model based on the input parameter may include:
determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter;
and applying transmission characteristic constraint to each transmission operation based on the transmission characteristic queue, and sending the read-write data packet to the host model based on the constrained transmission operation.
In an alternative embodiment, the applying a transmission characteristic constraint to each of the transmission operations based on the transmission characteristic queue may include:
taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation;
or extracting a plurality of constraint values from the transmission characteristic queue to construct a constraint range as the transmission characteristic constraint of the transmission operation.
In the implementation process, the complete control flow of the Master model can be completed through grouping constraint and layering constraint, so that the accurate constraint of the AXI Master can be realized, and reliable Master transmission behavior is provided for performance verification of the SOC chip.
In an alternative embodiment, the sending the read-write data packet to the host model based on the input parameter to simulate the data transmission process of the host may include:
before the read-write data packet is sent, a waiting time function is inserted into the control flow of the host end, and the parameter value of the waiting time is the value of the transmission distance parameter.
Optionally, the transmission characteristic parameters may further include an advanced transmission characteristic, a burst length characteristic, a first delay characteristic, a second delay characteristic and a third delay characteristic, where the advanced transmission characteristic characterizes an ability of the host to advance transmission, the burst length characteristic characterizes a burst length of the host to send out transmission, the first delay characteristic characterizes a delay of data of the host write operation relative to an address channel, the second delay characteristic characterizes a delay of the host to initiate a ready signal, and the third delay characteristic characterizes a delay of the host to initiate a reply signal.
The simulating the data transmission process of the host based on the host model may include:
determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter;
taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation;
and retrieving a minimum address and a maximum address from the transmission characteristic queue to construct a transmission address range as a transmission characteristic constraint of the transmission operation.
In a second aspect, an embodiment of the present application provides an SOC verification apparatus, which may include:
the model construction module is used for representing the data transmission characteristics of the host terminal based on the transmission characteristic parameters, constructing a host terminal model of the SOC, wherein the transmission characteristic parameters comprise transmission distance parameters, and the transmission distance parameters represent the time interval between the time point of the initiation of one transmission operation by the host terminal and the last transmission operation;
the simulation module is used for simulating the data transmission process of the host terminal based on the host terminal model;
and the verification module is used for verifying the SOC based on the data transmission process.
Alternatively, the simulation module may be specifically configured to:
generating constraint data according to the design parameter information of the host end; configuring input parameters of the host model based on the constraint data, and generating a read-write data packet; and sending the read-write data packet to the host model based on the input parameters so as to simulate the data transmission process of the host.
Optionally, the simulation module may be further configured to:
determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter; and applying transmission characteristic constraint to each transmission operation based on the transmission characteristic queue, and sending the read-write data packet to the host model based on the constrained transmission operation.
Optionally, the simulation module may be further configured to: taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation; or extracting a plurality of constraint values from the transmission characteristic queue to construct a constraint range as the transmission characteristic constraint of the transmission operation.
Optionally, the simulation module may be further configured to:
before the read-write data packet is sent, a waiting time function is inserted into the control flow of the host end, and the parameter value of the waiting time is the value of the transmission distance parameter.
Optionally, the transmission characteristic parameters may further include an advanced transmission characteristic, a burst length characteristic, a first delay characteristic, a second delay characteristic and a third delay characteristic, where the advanced transmission characteristic characterizes an ability of the host to advance transmission, the burst length characteristic characterizes a burst length of the host to send out transmission, the first delay characteristic characterizes a delay of data of the host write operation relative to an address channel, the second delay characteristic characterizes a delay of the host to initiate a ready signal, and the third delay characteristic characterizes a delay of the host to initiate a reply signal.
The simulation module may also be used to: determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter; taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation; and retrieving a minimum address and a maximum address from the transmission characteristic queue to construct a transmission address range as a transmission characteristic constraint of the transmission operation.
In a third aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a memory and a processor, where the memory stores program instructions, and when the processor reads and executes the program instructions, the processor executes the steps in any implementation manner described above.
In a fourth aspect, embodiments of the present application also provide a computer readable storage medium having stored therein computer program instructions which, when read and executed by a processor, perform the steps of any of the above implementations.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of steps of an SOC verification method according to an embodiment of the present application;
fig. 2 is a schematic diagram of steps of a data transmission process of an analog host according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating steps for providing a host input interface according to an embodiment of the present application;
fig. 4 is a schematic diagram of an SOC verification apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. For example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The applicant finds in the research process that the current verification of the SOC can be performed by a constraint random test platform, such as a UVM verification platform, but the constraint random test platform works normally to a certain extent, but cannot be extended to full-SOC verification, and although an embedded processor of the SOC usually has the capability of running codes in simulation, the UVM verification platform cannot provide any guidance on activities of all coordination processors and test platforms. Thus, the above limitations result in many SOC teams doing only minimal validation at the full-chip level. They simply verify that the modules are properly connected and possibly run some simple tests to verify that the primary modules are functioning properly. The real situation of module concatenation in SOC operation is rarely tested. This "latch and shift" approach carries a high risk because it never tests complex interactions between modules, which is quite likely to expose defects in design bug or performance verification.
Based on the above, the embodiment of the application realizes modeling of microscopic behaviors of the transmission characteristics of the AXI VIP (AXI Verification IP) in the verification environment by introducing a new data transmission characteristic, thereby improving the verification accuracy of the SOC. Referring to fig. 1, fig. 1 is a schematic diagram of steps of an SOC verification method according to an embodiment of the present application, where the SOC verification method may include the following steps:
in step S11, a host-side model of the SOC is constructed based on the data transmission characteristics of the transmission-characteristic-characterizing host-side.
The transmission characteristic parameter includes a transmission distance parameter, where the transmission distance parameter represents a time interval between a time point when the host initiates a transmission operation and a previous transmission operation.
In step S12, a data transmission process of the host is simulated based on the host model.
In step S13, the SOC is verified based on the data transmission process.
The method provided by the embodiment of the application can be applied to testing the SOC interface based on an AXI VIP (AXI Verification IP) module, an AXI bus protocol is adopted in the SOC, the AXI (Advanced eXtensible Interface) bus is a multi-channel transmission bus, address, read data, write data and handshake signals are sent in different channels, the sequence among different accesses can be disordered, and the BUSID is used for representing the attribution of each access. The master device may issue multiple read and write operations without obtaining the return data. The order of the read back data may be shuffled while also supporting unaligned data accesses.
The buses such as AMBA and the like are different according to protocols, and the buses are divided into a Master (Master), namely a slave, and a container (slave), namely a slave, wherein some devices can be used as the slave or the Master, such as a core, a debug module, an I2C, an SPI and the like, but only one Master occupies the buses at the same time.
The transmission characteristic parameters of the axivip for the host (Master) can be classified into two categories according to whether the system features of the Master are embodied:
the first type is a parameter which cannot mainly reflect the characteristics of the Master system, and can comprise parameters such as a read-write type, a read/write address, burst_size, burst_type, an ID value and the like. The second type is a parameter which can embody a system characteristic of a Master, and can include the transmission characteristic parameter, an advanced transmission characteristic, a burst length characteristic, a first delay characteristic, a second delay characteristic, a third delay characteristic and the like, wherein the advanced transmission characteristic represents the capability of advanced transmission of the host, the burst length characteristic represents the burst length of transmission sent by the host, the first delay characteristic represents the delay of data of write operation of the host relative to an address channel, the second delay characteristic represents the delay of initiation of a preparation signal of the host, and the third delay characteristic represents the delay of initiation of a response signal of the host. In the embodiment of the application, the advanced transmission characteristic is represented by the outtiming num, the burst length characteristic is represented by the burst_length, the first delay characteristic is represented by the wdata_delay, the second delay characteristic is represented by the rready_delay, the rready can be initiated after how long the Master initiates the command, the third delay characteristic is represented by the break_delay, and the break can be initiated after how long the Master initiates the command.
Therefore, in the embodiment of the application, the high-level modeling of the behavior level of the Master transmission characteristic can be performed on the basis of the data transmission characteristic of the introduced design, namely the transmission distance parameter, so as to represent the microscopic behavior of the Master in data transmission, thereby realizing the control mechanism of the microscopic transmission behavior of the AXI Master and improving the accuracy of SOC verification.
In an alternative embodiment, referring to fig. 2, fig. 2 is a schematic diagram of a step of the data transmission process of the analog host provided in the embodiment of the present application, for step S12, the step may include:
in step S21, constraint data is generated according to the design parameter information of the host side.
In the embodiment of the application, the design parameter information of the host end can comprise indexes such as functions, performances, interface specifications, temperature, power consumption and the like, and after the design description is determined, the SOC is verified through a constrained random test platform.
In step S22, input parameters of the host model are configured based on the constraint data, and a read-write data packet is generated.
In the embodiment of the application, the input parameter interface of the host model can comprise:
the trans-distance packet queues, i.e., the range of packet values for trans-distance and the duty cycle of the transmission of each packet value in the total number of transmissions. Such as trans distance_a0 (representing the first element of the queue) = [100, 200,5], where 100, 200 represents a range of trans distance between 100 and 200 and 5 represents 5% of the total transmission. While limiting the queue length to no more than 10 because too many classifications would make the packet too thin, the differentiation is not very large.
The burst length packet queue, i.e., each possible burst length and transmission duty cycle, e.g., burst length a0= [16,20] indicates that the transmission duty cycle of burst length=16 is 20%, again limiting the queue length to no more than 10.
The wdata_delay packet queue, i.e., the packet range of wdata_delay values and each packet range, gets the transmission duty cycle.
The rready_delay packet queue, i.e., the packet range of rready_delay value and the transmission duty cycle for each packet range.
The break_delay packet queue, i.e., the packet range of the break_delay value and the transmission duty cycle for each packet range.
The address range of the AXI transmission, i.e. the minimum address and the maximum address.
In step S23, the read-write data packet is sent to the host model based on the input parameters, so as to simulate the data transmission process of the host.
The generated constraint data is used for realizing constraint randomization of the data packet (transaction) according to the characteristic requirements corresponding to the IP module, so that a read-write data packet is obtained, and the behavior of the IP bus is simulated by sending the read-write data packet to the main VIP of the corresponding IP module, so that the modeling of the behavior of the IP bus is realized.
Therefore, the embodiment of the application can carry out grouping constraint on the transmission data packet through the input parameter interface, and can provide a constraint mechanism with an achievable microscopic transmission characteristic, so that the constructed Master model can simulate the microscopic behavior of the Master in data transmission, the SOC is verified based on the data transmission process of the Master model, and the accuracy of SOC verification can be improved.
Further, in the step S11, the trans distance parameter is a description of microscopic characteristics of each transmission, and the input parameter of the Master model cannot describe the behavior of each transmission completely, and the input of the model can only be a constraint rule of a relatively macroscopic scale. Therefore, further, an embodiment of the present application will describe how the input parameters of the model are implemented, please refer to fig. 3, fig. 3 is a schematic diagram of steps for providing the host input interface in the embodiment of the present application, which may include:
in step S31, a transmission characteristic parameter of each transmission operation is determined according to the input parameter of the host model, so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter.
In step S32, a transmission characteristic constraint is applied to each of the transmission operations based on the transmission characteristic queue, and the read-write data packet is sent to the host model based on the constrained transmission operation.
Among other things, since the AXI protocol is based on burst (burst) transmission. Burst transfer is to transfer data adjacent to a plurality of addresses continuously in one transaction. One burst transmission may include one or more data (Transfer). Each transfer is a transfer operation in the present application because it uses one cycle, which is also called a Beat of data (bet).
In the embodiment of the present application, the control over the Master is implemented by adopting a two-layer constraint solving manner, where the first-layer constraint is to solve, in step S31, transmission characteristic parameters of each data transmission, that is, parameters such as trans_ distance, burst _length, wdata_delay, rready_delay, break_delay, and the like in the above description, according to input parameters of the Master model, under the condition of given transmission length, and solve a total transmission queue of each parameter, so as to apply a packet constraint on the Master. Specifically, the total transmission length may be randomly generated according to an empirical value range, and in this embodiment, the total transmission length may be set to 20000-50000.
The second layer constraint is a transmission characteristic constraint applied to each transmission according to the AXI Master VIP requirement and the transmission characteristic queue of each parameter determined in the above steps, and specifically, step S32 may include: taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation; or extracting a plurality of constraint values from the transmission characteristic queue to construct a constraint range as the transmission characteristic constraint of the transmission operation.
Illustratively, the transmission distance is taken out of the value in the queue from the trans_distance as the trans_distance condition of the present transmission, and the control principle for the trans_distance is as follows: before the VIP transmission is sent out, a waiting time function is inserted in the Master control flow, and the parameter of the waiting time function is the currently acquired trans_distance value.
In addition, the burst length is a constraint on a value extracted from the burst length queue, and similarly, the delay of the data of the write operation with respect to the address channel, the delay of the host-side initiation ready signal, and the delay of the initiation response signal are a constraint on a value extracted from the wdata_day, read_delay, and read_delay queues, respectively.
The outlining value of the AXI Master is statically configured in the authentication environment as a configuration parameter for the Master VIP.
The data transmission address is constrained according to the address range, namely, the maximum address value and the minimum address value are taken out from the address transmission queue to form the address constraint range.
Therefore, the embodiment of the application completes the complete control flow of the Master model through grouping constraint and layering constraint, thereby realizing accurate constraint of the AXI Master and providing reliable Master transmission behavior for performance verification of the SOC chip.
In addition, for step S13, the data transmission process simulated by the Master model in the embodiment of the present application may be to obtain data bandwidth information corresponding to the data transmission operation, compare the obtained data bandwidth information with the total bandwidth of the bus, and determine whether the SOC passes the verification according to the comparison result.
Based on the same inventive concept, the embodiment of the present application further provides an SOC verifying apparatus 40, please refer to fig. 4, fig. 4 is a schematic diagram of the SOC verifying apparatus provided in the embodiment of the present application, and the SOC verifying apparatus 40 may include:
the model building module 41 is configured to characterize a data transmission characteristic of a host terminal based on a transmission characteristic parameter, and build a host terminal model of the SOC, where the transmission characteristic parameter includes a transmission distance parameter, and the transmission distance parameter represents a time interval between a time point at which the host terminal initiates a transmission operation and a previous transmission operation.
The simulation module 42 is configured to simulate a data transmission process of the host based on the host model.
And a verification module 43, configured to verify the SOC based on the data transmission process.
Therefore, in the embodiment of the application, the high-level modeling of the behavior level of the Master transmission characteristic can be performed on the basis of the data transmission characteristic of the introduced design, namely the transmission distance parameter, so as to represent the microscopic behavior of the Master in data transmission, thereby realizing the control mechanism of the microscopic transmission behavior of the AXI Master and improving the accuracy of SOC verification.
Alternatively, the simulation module 42 may be specifically configured to:
generating constraint data according to the design parameter information of the host end; configuring input parameters of the host model based on the constraint data, and generating a read-write data packet; and sending the read-write data packet to the host model based on the input parameters so as to simulate the data transmission process of the host.
Therefore, the embodiment of the application can carry out grouping constraint on the transmission data packet through the input parameter interface, and can provide a constraint mechanism with an achievable microscopic transmission characteristic, so that the constructed Master model can simulate the microscopic behavior of the Master in data transmission, the SOC is verified based on the data transmission process of the Master model, and the accuracy of SOC verification can be improved.
Optionally, the simulation module 42 may be further configured to:
determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter; and applying transmission characteristic constraint to each transmission operation based on the transmission characteristic queue, and sending the read-write data packet to the host model based on the constrained transmission operation.
Optionally, the simulation module 42 may be further configured to: taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation; or extracting a plurality of constraint values from the transmission characteristic queue to construct a constraint range as the transmission characteristic constraint of the transmission operation.
Optionally, the simulation module 42 may be further configured to:
before the read-write data packet is sent, a waiting time function is inserted into the control flow of the host end, and the parameter value of the waiting time is the value of the transmission distance parameter.
Optionally, the transmission characteristic parameters may further include an advanced transmission characteristic, a burst length characteristic, a first delay characteristic, a second delay characteristic and a third delay characteristic, where the advanced transmission characteristic characterizes an ability of the host to advance transmission, the burst length characteristic characterizes a burst length of the host to send out transmission, the first delay characteristic characterizes a delay of data of the host write operation relative to an address channel, the second delay characteristic characterizes a delay of the host to initiate a ready signal, and the third delay characteristic characterizes a delay of the host to initiate a reply signal.
The simulation module 42 may also be used to: determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter; taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation; and retrieving a minimum address and a maximum address from the transmission characteristic queue to construct a transmission address range as a transmission characteristic constraint of the transmission operation.
Based on the same inventive concept, the embodiment of the application also provides an electronic device, which comprises a memory and a processor, wherein the memory stores program instructions, and the processor executes the steps in any implementation mode when reading and running the program instructions.
Based on the same inventive concept, the embodiments of the present application also provide a computer readable storage medium, in which computer program instructions are stored, which when read and run by a processor, perform the steps in any of the above implementations.
The computer readable storage medium may be any of various media capable of storing program codes, such as random access Memory (Random Access Memory, RAM), read Only Memory (ROM), programmable Read Only Memory (Programmable Read-Only Memory, PROM), erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), and the like. The storage medium is used for storing a program, the processor executes the program after receiving an execution instruction, and the method executed by the electronic terminal defined by the process disclosed in any embodiment of the present application may be applied to the processor or implemented by the processor.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
Alternatively, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part.
The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.).
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. An SOC verification method, comprising:
characterizing data transmission characteristics of a host terminal based on the transmission characteristic parameters, and constructing a host terminal model of the SOC; the transmission characteristic parameters comprise transmission distance parameters, and the transmission distance parameters represent the time interval between the time point of initiating one transmission operation by the host terminal and the last transmission operation;
simulating a data transmission process of a host terminal based on the host terminal model;
verifying the SOC based on the data transmission process;
the data transmission process based on the host model for simulating the host comprises the following steps:
generating constraint data according to the design parameter information of the host end;
configuring input parameters of the host model based on the constraint data, and generating a read-write data packet;
transmitting the read-write data packet to the host model based on the input parameters so as to simulate the data transmission process of the host;
the sending the read-write data packet to the host model based on the input parameters includes:
determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter;
and applying transmission characteristic constraint to each transmission operation based on the transmission characteristic queue, and sending the read-write data packet to the host model based on the constrained transmission operation.
2. The method of claim 1, wherein said applying a transmission characteristic constraint to each of said transmission operations based on said transmission characteristic queue comprises:
taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation; or (b)
And taking out a plurality of constraint values from the transmission characteristic queue to construct a constraint range as the transmission characteristic constraint of the transmission operation.
3. The method of claim 1, wherein the sending the read-write data packet to the host model based on the input parameters to simulate a data transfer process of the host comprises:
before the read-write data packet is sent, a waiting time function is inserted into the control flow of the host end, and the parameter value of the waiting time is the value of the transmission distance parameter.
4. The method of claim 1, wherein the transmission characteristic parameters further comprise a look-ahead transmission characteristic, a burst length characteristic, a first delay characteristic, a second delay characteristic, and a third delay characteristic;
the advanced transmission feature characterizes the capability of the host to perform advanced transmission, the burst length feature characterizes the burst length of the host to transmit, the first delay feature characterizes the delay of the data of the host write operation relative to an address channel, the second delay feature characterizes the delay of the host to initiate a ready signal, and the third delay feature characterizes the delay of the host to initiate a response signal.
5. The method of claim 4, wherein simulating the data transfer process of the host based on the host model comprises:
determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter;
taking out a constraint value from the transmission characteristic queue as a transmission characteristic constraint of the transmission operation;
and retrieving a minimum address and a maximum address from the transmission characteristic queue to construct a transmission address range as a transmission characteristic constraint of the transmission operation.
6. An SOC verification apparatus, comprising:
the model construction module is used for representing the data transmission characteristics of the host terminal based on the transmission characteristic parameters, constructing a host terminal model of the SOC, wherein the transmission characteristic parameters comprise transmission distance parameters, and the transmission distance parameters represent the time interval between the time point of the initiation of one transmission operation by the host terminal and the last transmission operation;
the simulation module is used for simulating the data transmission process of the host terminal based on the host terminal model;
the verification module is used for verifying the SOC based on the data transmission process;
the simulation module may be specifically configured to: generating constraint data according to the design parameter information of the host end; configuring input parameters of the host model based on the constraint data, and generating a read-write data packet; transmitting the read-write data packet to the host model based on the input parameters so as to simulate the data transmission process of the host; determining transmission characteristic parameters of each transmission operation according to the input parameters of the host model so as to determine a transmission characteristic queue corresponding to each transmission characteristic parameter; and applying transmission characteristic constraint to each transmission operation based on the transmission characteristic queue, and sending the read-write data packet to the host model based on the constrained transmission operation.
7. An electronic device comprising a memory and a processor, the memory having stored therein program instructions which, when executed by the processor, perform the steps of the method of any of claims 1-5.
8. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein computer program instructions which, when executed by a processor, perform the steps of the method according to any of claims 1-5.
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