CN114417757A

CN114417757A - Method for automatically compiling and generating FPGA (field programmable Gate array) engineering with different functions

Info

Publication number: CN114417757A
Application number: CN202111676030.0A
Authority: CN
Inventors: 王晓霞; 谌彤
Original assignee: Xindong Technology Zhuhai Co ltd; Core Microelectronics Technology Zhuhai Co ltd
Current assignee: Xindong Technology Zhuhai Co ltd; Core Microelectronics Technology Zhuhai Co ltd
Priority date: 2021-12-31
Filing date: 2021-12-31
Publication date: 2022-04-29

Abstract

The invention discloses a method for generating FPGA engineering with different functions by automatic compiling. The method comprises the following steps: writing a first script file for describing instructions and setting global parameters; wherein the instructions described in the first script file are used for adding design files and constraint files of the functional module; writing a second script file for declaring configuration parameters and describing instructions; the instruction described by the second script file is used for calling the first script file; and operating the second script file to generate the FPGA project. The invention can effectively solve the problem that one or more FPGA projects are possibly updated and unsynchronized in the process of testing the large chip by utilizing a plurality of FPGA projects, remarkably reduces the workload of design, has strong universality and saves the verification time.

Description

Method for automatically compiling and generating FPGA (field programmable Gate array) engineering with different functions

Technical Field

The invention belongs to the technical field of chip testing, and particularly relates to a method for generating FPGA (field programmable gate array) engineering with different functions by automatic compiling.

Background

A chip, in essence, is a thumb-sized area of physical circuitry with hundreds of millions of transistors highly integrated. The development and manufacturing process of the chip involves the engineering of digital part design, analog part design, integration, mask generation, photolithography, particle implantation, etching and the like. The design workload is large, the period is long, the process is complex, at least millions of dollars are produced in a single trial production, the cost, the period and the workload determine that the chip design process is highly rigorous, and therefore, various testing means are needed to ensure that each process design meets the expectation.

At present, the means for testing the chip mainly includes designing software to perform virtual simulation, performing semi-physical simulation through a Field Programmable Gate Array (FPGA) chip, and performing near-actual test through a hardware simulation platform. The design software is mainly used for simulating excitation through modeling, can only be used for performing preliminary tests on the correctness of some function developments, and cannot simulate the working state of an actual chip, such as power supply fluctuation, electromagnetic interference and actual circuit element characteristics. The hardware simulation platform tests to be close to the actual state of the chip, the simulation speed is high, but the cost of the hardware simulation platform is over a million, and meanwhile, the simulation of 1-2 chips can be carried out, so that the method has great limitation.

The FPGA chip is a semi-custom chip, and the internal circuit of the FPGA chip is built through software programming to form a special circuit of the FPGA chip. The design chip is essentially to design a special circuit of the chip, and before the chip is formally produced, the FPGA chip can be used for testing whether the design of the chip meets the requirements of customers or not, and the performance of the chip in the actual use environment is obtained. The FPGA chip can be programmed for many times, is low in cost, can reflect the real performance of the chip to a certain degree, and is widely applied to chip design.

The FPGA has programmable logic resources, and the more the resources are, the cost rises exponentially. In order to further reduce the test cost, a plurality of FPGA chips with fewer logic resources are often adopted to work cooperatively, so as to realize the test of the large chip design. For example, when some large-scale SOC integrated circuits are prototype-verified on an FPGA, the large-scale design is designed by dividing, and a plurality of FPGA projects are formed for cooperative testing. Although the testing of a large chip can be realized by utilizing multiple FPGA chips through segmentation, the multiple cut FPGA projects are correlated, so that the updating iteration of a single FPGA project can influence the functions of other FPGAs, the version control is difficult, and the problem is easy to occur. For example: the integrated circuit design comprises a common function module, other function modules and a constraint module, and the integrated circuit is divided into 3 FPGA engineering implementations. If the design code of the common function module is updated, the other two FPGA projects need to be updated synchronously, otherwise, the risk of version error exists. This virtually increases the workload and reduces the test efficiency.

Disclosure of Invention

Aiming at the defects or improvement requirements in the prior art, the invention provides a method for automatically compiling and generating FPGA projects with different functions, which can effectively solve the problem that one or more FPGA projects are possibly updated asynchronously in the process of testing a large chip by utilizing a plurality of FPGA projects, and has the advantages of remarkably reducing the workload of design, having strong universality and saving the verification time.

To achieve the above object, according to an aspect of the present invention, there is provided a method for generating FPGA engineering by automatic compiling, including: writing a first script file for describing instructions and setting global parameters; wherein the instructions described in the first script file are used for adding design files and constraint files of the functional module; writing a second script file for declaring configuration parameters and describing instructions; the instruction described by the second script file is used for calling the first script file; and operating the second script file to generate the FPGA project.

In some embodiments, the method further comprises writing design files and constraint files for the functional modules.

In some embodiments, writing a design file for a functional module includes implementing the functionality of the functional module in a programming language; writing a constraint file for a functional module includes describing constraints for a logic design.

In some embodiments, writing the design file for the functional module further comprises instantiating each functional module using a conditional compilation statement; the constraints of the logic design include at least one of physical location constraints, electrical characteristic constraints, and timing constraints.

In some embodiments, the instructions described in the first script file include a first instruction, a second instruction, and a third instruction; the first instruction is used for building a project and setting a device target, and the second instruction is used for adding a design file, a constraint file and a library file of a functional module; the third instruction is for synthesis and implementation.

In some embodiments, the configuration parameters declared by the second script file correspond to functional modules, and the FPGA project generated by running the second script file corresponds to the functional modules.

In some embodiments, the configuration parameters include a first configuration parameter and a second configuration parameter, the functional modules include a first functional module and a second functional module, and the FPGA engineering includes a first FPGA engineering and a second FPGA engineering; the first configuration parameter and the first FPGA project correspond to a first functional module, and the second configuration parameter and the second FPGA project correspond to a second functional module; running a second script file, inputting a first configuration parameter, calling a design file and a constraint file of the first functional module, and generating a first FPGA project; and operating the second script file, inputting a second configuration parameter, calling the design file and the constraint file of the second functional module, and generating a second FPGA project.

In some embodiments, the global parameters set by the first script file include configuration parameters declared by the second script file.

In some embodiments, the first script file is a TCL script and the second script file is a makefile script.

According to another aspect of the invention, a chip testing method is provided, which comprises the steps of generating a plurality of FPGA projects by using the method; and adopting a plurality of FPGA engineering cooperative tests.

Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects: and adopting a makefile text for inputting configuration parameters, and adopting a TCL text to automatically load a design file and a constraint file to generate the FPGA project. In the actual test process, only the configuration parameters in the makefile need to be changed and replaced by the file after iteration, and then a plurality of FPGA projects can be automatically generated. That is to say, only one FPGA environment is used to change the input configuration parameters, so that a plurality of FPGA projects with different related functions can be automatically generated, and one FPGA environment does not need to be created for each FPGA project, so that the workload of design is reduced, the universality is strong, and the verification time is saved; on the other hand, the risk caused by the asynchronous updating of a plurality of projects is avoided.

Drawings

FIG. 1 is a flow chart of a method for generating FPGA projects with different functions by automatic compilation according to an embodiment of the present invention;

FIG. 2 is a flow diagram of a method of writing a first script file.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

As shown in fig. 1, the method for generating FPGA engineering with different functions by automatic compiling according to the embodiment of the present invention includes:

the method comprises the following steps: and writing design files and constraint files of the functional modules.

Specifically, writing the design file of the functional module includes implementing a predetermined function (i.e., a function of the functional module) in a program language, and obtaining the design file of the functional module. In some embodiments, the programming language is a verilog language, a VHDL language, or a systemverilog language. In some embodiments, the functional module includes a first functional module and a second functional module. In some embodiments, the functional modules include a first functional module, a second functional module, and a third functional module. Of course, more functional modules can be included, which are determined according to actual test requirements.

Writing the constraint file of the functional module comprises describing the constraint of the logic design to obtain the constraint file of the functional module. In some embodiments, the EDA tool's own constraint file editor is developed with a file editor and FPGA for editing. In some embodiments, the constraints of the logic design include physical location constraints, electrical characteristic constraints, and timing constraints. Through the constraint of logic design, the design can be ensured to correctly operate at a fixed position and a certain speed.

In some embodiments, writing the design file further includes instantiating the respective functional modules using the conditional compilation statement. Specifically, some selection conditions are set, and whether to call design files and constraint files of each functional module is determined according to input parameters. For example, the set selection conditions are: when the input is A, instantiating a first functional module (for example, the functional module A), and calling a design file and a constraint file of the first functional module; when the input is B, instantiating a second functional module (for example, the functional module B), and calling a design file and a constraint file of the second functional module; when the input is C, a third function module (e.g., function module C) is instantiated, and the design files and constraint files of the third function module are called.

Step two: a first script file is written for describing the instructions and setting global parameters.

In some embodiments, the instructions described in the first script file include a first instruction, a second instruction, and a third instruction. The first instruction is used for building engineering and setting device targets, the second instruction is used for adding design files, constraint files and library files of the functional modules, and the third instruction is used for synthesis and implementation.

Referring to fig. 2, in some embodiments, writing a first script file specifically includes: first, describing a first instruction to build a project and set a device target; describing a second instruction to add a design file, a constraint file and a library file of the functional module; finally, a third instruction is described to perform synthesis and implementation. In some embodiments, the global parameter is set after the first instruction is described and before the third instruction is described. The order of setting the global parameter and describing the second instruction can be exchanged, that is, the second instruction can be described first, and then the global parameter is set, or the global parameter can be set first, and then the second instruction is described.

In some embodiments, the first script file is a TCL script. TCL is a scripting language, and at present, each large FPGA development platform supports TCL scripts.

In some embodiments, the first instruction is described by a TCL script command create _ project.

In some embodiments, the design file of the added function module and the constraint file of the added function module in the second instruction are described by the TCL script command add _ files. In some embodiments, the library file of the added function module in the second instruction is described by the TCL script command set _ property.

In some embodiments, the parameters are set with the TCL script command set _ property.

In some embodiments, the synthesis in the third instruction is described by TCL script commands launch _ runs and wait _ on _ run. In some embodiments, implementations in the third instruction are described in TCL script commands launch _ runs and wait _ on _ run. It is understood that the script command may be replaced by other instructions that can achieve the same or similar functions, and the present invention is not limited thereto.

Step three: a second script file is written for declaring configuration parameters and describing instructions.

In some embodiments, the configuration parameters are used to generate each FPGA project.

In some embodiments, the configuration parameters correspond to functional modules. In some embodiments, the configuration parameters include a first configuration parameter and a second configuration parameter. In some embodiments, the configuration parameters include a first configuration parameter, a second configuration parameter, and a third configuration parameter. In some embodiments, the first configuration parameter corresponds to a first functional module, the second configuration parameter corresponds to a second functional module, and the third configuration parameter corresponds to a third functional module.

In some embodiments, the instructions described by the second script file are used to invoke the first script file, e.g., a TCL script.

In some embodiments, the second script file is a makefile script. It is understood that the first script file and the second script file may also be other file types that can achieve the same or similar functions, and the present invention is not limited thereto.

Step four: and operating the second script file to generate the FPGA project.

In some embodiments, the second script file is run, and the configuration parameters are input, so that the functional module corresponding to the configuration parameters can be automatically loaded, the design file and the constraint file of the functional module are called, and the corresponding FPGA project is generated.

In some embodiments, the FPGA engineering corresponds to a functional module. In some embodiments, the FPGA engineering includes a first FPGA engineering and a second FPGA engineering. In some embodiments, the FPGA engineering includes a first FPGA engineering, a second FPGA engineering, and a third FPGA engineering. In some embodiments, the first FPGA engineering corresponds to a first functional module, the second FPGA engineering corresponds to a second functional module, and the third FPGA engineering corresponds to a third functional module.

In some embodiments, the second script file is run, the first configuration parameter (for example, input parameter a) is input, the first function module (for example, function module a) can be automatically loaded, the design file and the constraint file of the first function module are called, and the first FPGA project is generated; running the second script file, inputting a second configuration parameter (such as an input parameter B), namely automatically loading a second functional module (such as a functional module B), calling a design file and a constraint file of the second functional module, and generating a second FPGA project; and running the third script file, inputting a third configuration parameter (such as an input parameter C), namely automatically loading a third functional module (such as a functional module C), calling a design file and a constraint file of the third functional module, and generating a third FPGA project.

In some embodiments, the first step, the second step and the third step are independently completed without any sequence. And step four is finally completed, namely after the step one, the step two and the step three are executed, the step four is executed again.

The method only needs to create a general FPGA engineering environment, and can automatically load the design file and the constraint file by inputting simple parameters to generate an FPGA engineering. Because the code is a set of codes, design iteration is easier, only one FPGA engineering environment needs to be maintained, and when the common design code is updated, only one general FPGA engineering environment needs to be updated. Compared with the situation of maintaining a plurality of engineering environments, the method has the advantages that the workload is obviously reduced, and the error probability is greatly reduced.

In addition, the method of the invention adopts TCL script command to quickly create engineering, adds design files, constraint files, statement macros, compiling, synthesizing, exporting process files and programming files, runs TCL script, and can automatically compile and complete the whole engineering realization flow on FPGA. Firstly, the manual participation degree is low, the labor cost is saved, and the times of design iteration caused by human errors are reduced; secondly, the universality is stronger, and if a new IC design file is only needed to be copied and pasted in the TCL script, a new IC prototype verification project can be generated; and thirdly, the verification time is saved, for example, by adopting a TCL command, the netlist can be automatically opened after the previous flow is completed, and an engineer does not need to check the comprehensive progress in real time and then open the netlist, so that the time can be remarkably saved, especially compared with the situation that the time is very long for opening the netlist of a large-scale design.

The invention also provides a chip testing method, which comprises the steps of generating a plurality of FPGA projects by using the method; and adopting a plurality of FPGA engineering cooperative tests.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps in the process. And the scope of the preferred embodiments of the present application includes other implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the method of the above embodiments may be implemented by hardware that is configured to be instructed to perform the relevant steps by a program, which may be stored in a computer-readable storage medium, and which, when executed, includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module may also be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for generating FPGA engineering by automatic compiling is characterized by comprising the following steps:

writing a first script file for describing instructions and setting global parameters; wherein the instructions described in the first script file are used for adding design files and constraint files of the functional module;

writing a second script file for declaring configuration parameters and describing instructions; the instruction described by the second script file is used for calling the first script file;

and operating the second script file to generate the FPGA project.

2. The method for automated compilation to generate FPGA engineering of claim 1 further comprising writing design files and constraint files for functional modules.

3. The method for automated compilation to generate FPGA engineering of claim 2 wherein writing design files for functional modules includes implementing the functions of the functional modules in a programming language; writing a constraint file for a functional module includes describing constraints for a logic design.

4. The method of automated compilation to generate FPGA engineering of claim 3, wherein writing a design file for a functional module further comprises instantiating each functional module with a conditional compilation statement; the constraints of the logic design include at least one of physical location constraints, electrical characteristic constraints, and timing constraints.

5. The method for automated compilation to generate FPGA engineering of claim 1 wherein the instructions described in the first script file include a first instruction, a second instruction, and a third instruction; the first instruction is used for building a project and setting a device target, and the second instruction is used for adding a design file, a constraint file and a library file of a functional module; the third instruction is for synthesis and implementation.

6. The method for automated compilation to produce FPGA engineering of claim 1 wherein the configuration parameters declared by the second script file correspond to functional modules and the FPGA engineering produced by running the second script file corresponds to functional modules.

7. The method for automated compilation to generate FPGA engineering of claim 6, wherein the configuration parameters comprise a first configuration parameter and a second configuration parameter, the functional modules comprise a first functional module and a second functional module, and the FPGA engineering comprises a first FPGA engineering and a second FPGA engineering;

the first configuration parameter and the first FPGA project correspond to a first functional module, and the second configuration parameter and the second FPGA project correspond to a second functional module;

running a second script file, inputting a first configuration parameter, calling a design file and a constraint file of the first functional module, and generating a first FPGA project; and operating the second script file, inputting a second configuration parameter, calling the design file and the constraint file of the second functional module, and generating a second FPGA project.

8. The method for automated compilation to generate FPGA engineering of claim 1 wherein the global parameters set by the first script file include configuration parameters declared by the second script file.

9. The method for generating FPGA projects through automatic compilation according to any one of claims 1 to 8, wherein the first script file is a TCL script and the second script file is a makefile script.

10. A method for testing a chip, comprising: generating a plurality of FPGA projects using the method of any one of claims 1 to 9; and adopting a plurality of FPGA engineering cooperative tests.