CN112926285A - Chip verification method, platform, device, equipment and storage medium - Google Patents
Chip verification method, platform, device, equipment and storage medium Download PDFInfo
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Abstract
The invention provides a chip verification method, a platform, a device, equipment and a storage medium. The verification method comprises the following steps: constructing a chip verification platform based on UVM; and verifying the design of the chip by using a verification platform. Wherein, the chip verification platform constructed based on UVM comprises: constructing a data packet; constructing a host agent for realizing host sending operation of a data packet; and constructing a slave agent for realizing the slave receiving operation of the data packet. The chip verification method, the platform, the device, the equipment and the storage medium have the characteristics of high verification efficiency, short verification period and capability of realizing reusable tests.
Description
Technical Field
The invention relates to the technical field of semiconductor design verification, in particular to a chip verification method, a platform, a device, equipment and a storage medium.
Background
Techniques for verifying the design of a chip, particularly an HDMI (High Definition Multimedia Interface) Interface chip, are known. The existing verification technology has the problems of low chip verification efficiency, long verification period and incapability of realizing reusable tests.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention are directed to providing a chip verification method, a platform, an apparatus, a device, and a storage medium, which have high verification efficiency and a short verification period and can implement a reusable test.
In one aspect, the present invention provides a chip verification method, comprising: constructing a chip Verification platform based on UVM (Universal Verification Methodology); and verifying the design of the chip by using a verification platform. Wherein, construct chip verification platform based on UVM, include: constructing a data packet; constructing a host agent for realizing host sending operation of a data packet; and constructing a slave agent for realizing the slave receiving operation of the data packet.
According to a specific embodiment of the present invention, the chip includes an HDMI interface chip.
According to a specific embodiment of the present invention, the data packets include video data packets and audio data packets.
According to a specific embodiment of the present invention, the audio data packet includes a flag bit for indicating whether the audio data packet is transmitted successively with the next audio data packet.
According to a specific embodiment of the present invention, the host agent includes a first channel for processing video data packets and a second channel for processing audio data packets.
In another aspect, the present invention provides a chip verification platform constructed based on UVM for verifying a design of a chip, including: a data packet; the host agent is used for realizing host sending operation of the data packet; and the slave agent is used for realizing the slave receiving operation of the data packet.
In another aspect, the present invention provides a chip verification apparatus, including: the building module is used for building a chip verification platform based on universal verification methodology UVM; and the verification module is used for verifying the design of the chip by utilizing the verification platform. Wherein, the construction module includes: a first constructing unit for constructing a data packet; the second constructing unit is used for constructing a host agent, and the host agent is used for realizing host sending operation of the data packet; and the third construction unit is used for constructing a slave agent, and the slave agent is used for realizing the slave receiving operation of the data packet.
In another aspect, the present invention provides a chip verification apparatus comprising: a processor; a memory; an application program stored in the memory and configured to be executed by the processor, the application program including instructions for performing the chip verification method described above.
In another aspect, the present invention provides a computer-readable storage medium storing a computer program for executing the chip verification method according to the above.
According to the chip verification method, the platform, the device, the equipment and the storage medium, the control calling interface which is very convenient to use can be provided due to the construction based on the UVM, the transplantation is convenient, the full-function test coverage of an interface protocol (such as an HDMI 1.4a protocol) can be completed through concise control calling, and therefore the purposes of improving the chip verification efficiency, shortening the verification period and realizing the reusable test can be achieved.
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The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference characters generally refer to the same or similar parts throughout the several views, and wherein:
FIG. 1 shows a schematic flow diagram of a chip verification method according to an embodiment of the invention;
FIG. 2 shows a schematic flow diagram of a chip verification method according to the embodiment of FIG. 1;
fig. 3 is a schematic diagram illustrating the structure of an HDMI transport packet according to an embodiment of the present invention;
FIG. 4 illustrates a flow diagram for a host driver (master driver) acquiring a transaction transport packet (trans) according to an embodiment of the invention;
FIG. 5 illustrates a schematic flow diagram of a driving process for video transaction transport packets (video trans) according to an embodiment of the present invention;
FIG. 6 illustrates a drive flow diagram for an audio transaction transport packet (island trans) in accordance with an embodiment of the present invention;
FIG. 7 is a diagram illustrating a UVC (Universal verification component) self-test environment according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a testbench (test file) building manner of a chip according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a chip verification platform according to an embodiment of the invention;
FIG. 10 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the invention;
fig. 11 shows a schematic structural diagram of a chip verification apparatus according to an embodiment of the present invention.
Detailed Description
The present invention is described in detail below with reference to specific embodiments in order to make the concept and idea of the present invention more clearly understood by those skilled in the art. It is to be understood that the embodiments presented herein are only a few of all embodiments that the present invention may have. Those skilled in the art who review this disclosure will readily appreciate that many modifications, variations, or alterations to the described embodiments, either in whole or in part, are possible and within the scope of the invention as claimed.
As used herein, the terms "first," "second," and the like are not intended to imply any order, quantity, or importance, but rather are used to distinguish one element from another. As used herein, the terms "a," "an," and the like are not intended to mean that there is only one of the described items, but rather that the description is directed to only one of the described items, which may have one or more. As used herein, the terms "comprises," "comprising," and other similar words are intended to refer to logical interrelationships, and are not to be construed as referring to spatial structural relationships. For example, "a includes B" is intended to mean that logically B belongs to a, and not that spatially B is located inside a. Furthermore, the terms "comprising," "including," and other similar words are to be construed as open-ended, rather than closed-ended. For example, "a includes B" is intended to mean that B belongs to a, but B does not necessarily constitute all of a, and a may also include C, D, E and other elements.
Herein, some operations are described in order. However, those skilled in the art will appreciate that these operations are not necessarily performed in the order of description, nor are they performed only once throughout the flow. In actual implementation, the execution order of these operations may be reversed, some operations may be executed at the same time or different times, and the execution times of the operations may be different from each other.
The terms "embodiment," "present embodiment," "an embodiment," "one embodiment," and "one embodiment" herein do not mean that the pertinent description applies to only one particular embodiment, but rather that the description may apply to yet another embodiment or embodiments. Those of skill in the art will understand that any of the descriptions given herein for one embodiment can be combined with, substituted for, or combined with the descriptions of one or more other embodiments to produce new embodiments, which are readily apparent to those of skill in the art and are intended to be within the scope of the present invention.
In the embodiments of the present invention, an interface (hardware transmission interface) may refer to an interface for information exchange and data transmission between hardware devices such as a computing device and a display device. The interfaces include a USB (Universal Serial Bus) Interface, an MD (Mini Disc) device Interface, an HDMI Interface, a VGA (Video Graphics Array) Interface, a DVI (Digital Visual Interface) Interface, and the like. Different interfaces may support different interface protocols. In each embodiment of the present invention, an interface protocol refers to a communication mode and a requirement to be followed between interfaces that need to exchange information, and the interface protocol needs to specify not only communication of a physical layer but also requirements of a syntax layer and a semantic layer. The interface protocol includes a pure video interface protocol, a pure audio interface protocol, a universal data interface protocol, etc. In the embodiments of the present invention, the interface chip may be a chip for supporting an interface protocol and implementing an interface function.
In each embodiment of the present invention, the chip verification may refer to verifying whether the chip design meets the requirement specification defined by the chip before the chip is produced, whether the risk is completely released, and finding and correcting all the defects by using a corresponding verification language, a verification tool, and a verification method. In the embodiments of the present invention, the chip verification may refer to an operation performed together with a chip design before tape-out, and a main purpose of the verification is to ensure correctness of a chip logic function and completeness of the function. The chip verification is divided into SOC verification and ASIC verification. The SOC verification means that a CPU core exists in a chip, and a corresponding operating system needs to be loaded and corresponding software runs after the chip is produced back in the future. The SOC verification requires building a software and hardware simulation platform, and case is compiled in a module level and a subsystem level by adopting a SystemVerilog or UVM building environment; the system level is written in the c/+ + language. ASIC verification means that a chip does not contain a CPU and is a single circuit logic, and corresponding control signals are only required to be externally supplied to the chip, such as an adder, a controller, a converter, a DDR, a FLASH, an EPROM and the like. ASIC verification typically employs a systemveilog or UVM to build a verification environment.
A chip verification method according to an embodiment of the present invention is described below with reference to fig. 1 and 2.
According to the present embodiment, the chip verification method 100 includes:
s110, constructing a chip verification platform based on UVM;
and S120, verifying the design of the chip by using a verification platform.
Wherein, S120 includes:
s121, constructing a data packet;
s122, constructing a host agent for realizing host sending operation of the data packet;
and S123, constructing a slave agent for realizing the slave receiving operation of the data packet.
According to the embodiment, the chip verification method is constructed based on the UVM, a control calling interface which is very convenient to use can be provided, the transplantation is convenient, and the full-function test coverage of an interface protocol can be completed through concise control calling, so that the aims of improving the chip verification efficiency, shortening the verification period and realizing reusable tests can be fulfilled.
In one embodiment, UVM may refer to a verification methodology for verifying a chip design. The UVM verification methodology comprises a series of methods for guaranteeing reusability, and the efficiency of establishing a verification environment is improved; meanwhile, the verification efficiency is effectively improved based on a constrained random method in UVM. The UVM methodology provides rich class library resources based on SystemVerilog (system level hardware description language) language, so that a user can conveniently and quickly realize the UVM verification method. UVC (Universal Verification Component) is important content of a UVM Verification method, and provides a quick building method of a Verification control capable of verifying a certain functional Component of a chip, so that reusability is guaranteed, and a Verification environment is conveniently built.
In an embodiment, the verification platform may refer to a software platform for chip verification, and may implement powerful, efficient, flexible, and scalable chip verification. In an embodiment, constructing a chip verification platform based on UVM may refer to constructing a functional verification environment with a standardized hierarchical structure and an interface by using reusable components based on a verification platform development framework mainly based on a systemveilog class library of UVM.
In an embodiment, verifying the design of the chip by using the verification platform may refer to that after the designer completes the RTL codes according to the design specification, the verification personnel verifies the RTL codes by using the verification platform.
In one embodiment, constructing the data packet may refer to constructing a data packet for verifying a chip transmission function, so as to simulate data transmitted by the chip. In a particular embodiment, constructing the packet may refer to constructing the HDMI transport layer packet HDMI _ trans _ item based on UVM. hdmi _ trans _ item is derived from the uvm _ sequence _ item class. According to the characteristics of the HDMI protocol that video data (coded transmission is completed by video period and ctrl period) and audio data and configuration information (coded transmission is completed by island period) are transmitted, the data packets are divided into two types, wherein one type is a video data type packet (including display data and blank data), and each data packet comprises a line of video data; the other type is audio and configuration information data packets, each data of which comprises an island packet and each data comprises a flag bit whether to be sent in connection with the next island packet or not so as to realize the combined sending of a plurality of island packets.
In an embodiment, constructing a host agent for implementing a host sending operation of a data packet may refer to constructing an agent for simulating a host function, and implementing a sending operation of a data packet through the agent, thereby verifying a data sending function of a chip. In a particular embodiment, building a host agent may refer to building an HDMI _ master _ agent (a host agent for HDMI) based on UVM. HDMI _ master _ agent is derived from UVM _ agent (UVM agent) and implements HDMI bus protocol host routing. It contains driver, sequencer and monitor. Wherein the sequence completes the transaction scheduling between the sequence of the excitation sequence and the driver. Because the invention divides the transmission layer data packet into two types, two corresponding channels are set in the sequence r to respectively complete the transmission scheduling of one type of packet. Wherein, the driver drives the HDMI bus signal of the data defined by the data packet. The invention can realize that the island packet is sent at any time of non-image data transmission. The driver estimates the time required by the island packet, and the transmission of multiple data packets does not occupy the transmission period of the image data. The monitor realizes real-time monitoring of the HDMI bus and acquisition of functional coverage rate, restores the acquired HDMI data into a data packet defined by the invention and sends the data packet through a TLM (Transmission Line Matrix) interface.
In an embodiment, constructing a slave agent for implementing a slave receiving operation of a data packet may refer to constructing an agent for simulating a slave function, and implementing a receiving operation of a data packet through the agent, thereby verifying a data receiving function of a chip. In a specific embodiment, constructing the slave agent may mean constructing HDMI _ slave _ agent (HDMI slave agent) based on UVM, which is derived from UVM _ agent, to implement HDMI protocol slave acceptance. It contains driver, monitor, and p _ cfg (component configuration information). The driver can realize the receiving and decoding of the HDMI data bus, and recover and pack the image data and the audio data. The monitor realizes the collection of bus detection and function coverage rate.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 1 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, the chip includes an HDMI interface chip.
According to the embodiment, the HDMI interface has the characteristics of being capable of simultaneously transmitting video data and audio data and having a large data flow. Practice proves that the HDMI interface chip is particularly suitable for performing function verification by using the verification method.
In one embodiment, the HDMI interface chip is an HDMI protocol-based interface chip. The HDMI protocol is a brand new digital video/Audio interface technology meeting the high-definition era standard, and the HDMI can not only meet the 1080P resolution, but also support digital Audio formats such as DVD Audio and the like, support eight-channel 96kHz or stereo 192kHz digital Audio transmission, and transmit uncompressed Audio signals and video signals. The HDMI interface can be used for set-top boxes, DVD players, personal computers, video games, digital stereos, and televisions. The HDMI interface can simultaneously transmit audio and video signals.
In one embodiment, the HDMI interface chip includes a chip including an HDMI slave interface (HDMI slave interface) and a chip including an HDMI master interface (HDMI host interface). In one embodiment, the HDMI interface chip includes chips supporting HDMI 1.1, HDMI 1.2, HDMI 1.3, HDMI 1.4a, HDMI 1.4b, HDMI 2.0, and the like.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 1 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, the packets include video packets and audio packets.
According to the embodiment, the data packet is divided into the video data packet and the audio data packet, so that the video transmission function and the audio transmission function of the chip can be tested respectively, and different data packet structures are designed according to different transmission characteristics of video and audio so as to realize testing and verification in different aspects.
In one embodiment, a video data packet may refer to a data packet containing video data. In one embodiment, an audio packet may refer to a packet containing audio data. In one embodiment, the audio data packet may contain configuration information and control information in addition to audio data.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 1 and may include one or more features of one or more of all of the embodiments described above.
According to the present embodiment, the audio data packet includes a flag bit for indicating whether the audio data packet is transmitted successively with the next audio data packet.
According to the embodiment, the flag bit is designed for the audio data packet, so that the continuous transmission of a plurality of audio data packets can be realized, the transmission speed and efficiency of the audio data packets are improved, and the system delay is reduced.
In one embodiment, the flag bit may refer to a variable used to determine the state of the whole program. In one embodiment, the audio data packet includes a flag bit, which may mean that a header in the audio data packet includes a flag bit.
The following describes another embodiment of the present invention, which is a specific example of the embodiment of fig. 1 and may include one or more features of one or more of all of the embodiments described above.
According to this embodiment, the host agent includes a first channel for processing video data packets and a second channel for processing audio data packets.
According to the embodiment, the host agent processes the video data packet and the audio data packet through two different channels respectively, so that the audio data packet can be sent at any time of non-video data transmission, the estimation of the time required by the video data packet is realized, and the sending of a plurality of audio data packets is realized without occupying the transmission period of the video data.
In an embodiment, the host agent includes a first channel and a second channel, which may refer to that two corresponding channels are set in a sequence in an hdmi _ master _ agent constructed based on UVM, and respectively complete delivery scheduling of the video data packet and the audio data packet.
A chip verification method according to an embodiment of the invention is described below with reference to fig. 3 to 7.
The verification method according to the embodiment comprises the following steps:
defining a transaction (transaction transport packet);
constructing a master _ agent;
construct the slave _ agent.
In this embodiment, the transaction is defined and includes:
firstly, defining image data packets in a row unit, and randomly constraining to realize full coverage of an HDMI protocol, wherein RGB, YCbCr4:4:4 and YCbCr4:2:2 different color depths, and the repetition times of pixel points in various image formats and sizes are all variables which can be randomly set in a constrained manner;
second, for island packets (audio and control packets), an island packet format is defined, which contains a 4-byte header, a 28-byte body, which enables automatic BCH encoding computation and error insertion. The data transmission packet as defined is shown in fig. 3.
In this embodiment, constructing a master _ agent includes:
first, as shown in fig. 4, two transaction storage queues (video _ req _ que (video request queue), and island _ req _ que (audio request queue)) are established inside the master _ driver, and after they accept the transmission transaction packet from the sequence, they are stored in their respective queues according to the type of the current transaction;
secondly, as shown in fig. 5 and fig. 6, sending a video packet and an island packet is processed and sent by two concurrent threads respectively; the remaining time of the current line control period is counted while the video packet is sent to the bus, for example, by a counter cur _ line _ ctrl _ remd (current line video synchronization information remaining period counter) in units of TMDS _ CLK (HDMI minimum transmission differential data clock (8 bits of original data are transmitted in one period)); and the driving process of the island packet is that when a packet is obtained from the island _ req _ que, whether cur _ line _ ctrl _ remd meets the transmission time of the island packet is judged firstly, if the cur _ line _ ctrl _ remd meets the transmission time of the island packet, the current packet is driven to the HDMI bus, and if the cur _ line _ ctrl _ remd does not meet the transmission time, the island packet is not driven to the bus, but the island packet is continuously waited until the cur _ line _ ctrl _ remd meets the transmission time.
In this embodiment, constructing a slave _ agent includes: and constructing a slave _ agent through the slave _ driver and the monitor. The slave _ dirver is responsible for receiving the decoded HDMI bus, recovering and packing transactions (video or island packets) that can be used by testbench (test file) and then sent to the external interface. The monitor is responsible for detecting bus signals and collecting protocol function coverage.
Based on the implementation of the master agent and the sample agent, the invention can complete the self-test of the HDMI protocol and complete the collection and analysis of the functional coverage. The development of UVC can be completed independently of HDMI hardware design, and the testbench of HDMI can be established before hardware design code design is completed, so that the verification period of the chip is shortened. Fig. 7 is a construction mode of the UVC self-testing environment.
The invention can realize the verification of two tested chips, one is a chip containing an HDMI slave interface, the other is a chip containing an HDMI master interface, and one construction mode of testbench is shown in FIG. 8.
As shown in fig. 8, the chip under test (i.e., HDMI DUT (RX), HDMI device under test) having the HDMI master interface is connected to the HDMI master agent through interface (transmission interface), and receives the data packet sent from the HDMI master agent. An LVDS monitor (low voltage differential signal monitor) monitors the operation of the HDMI DUT (RX) and sends the test result to scoreboard for recording.
A chip verification platform 900 according to an embodiment of the invention is described below in conjunction with FIG. 9.
According to the present embodiment, the chip verification platform 900 is constructed based on the universal verification methodology UVM, and is used for verifying the design of a chip, and includes:
a data packet 910;
a host agent 920 for implementing a host sending operation of the packet;
and a slave agent 930 for performing slave operation of the packet.
According to the verification platform of the embodiment, a self-testing environment is built based on UVM, a host computer and a slave computer are instantiated respectively, and the host computer and the slave computer are in butt joint through interface. Compiling a sequence capable of covering an interface protocol, completing data comparison between a sending end and a receiving end by a scoreboard, and collecting data information of a preset function coverage rate parameter; and calculating to obtain the functional coverage rate by utilizing the data information so as to ensure that the verification platform can fully cover the interface protocol.
A chip verification apparatus 1000 according to an embodiment of the present invention is described below with reference to fig. 10.
According to the present embodiment, the chip verification apparatus 1000 includes:
a building module 1010, configured to build a chip verification platform based on UVM;
a verification module 1020 for verifying the design of the chip using a verification platform;
wherein the building block 1010 includes:
a first construction unit 1011 for constructing a data packet;
a second constructing unit 1012, configured to construct a host agent, where the host agent is configured to implement a host sending operation of a data packet;
a third building unit 1013, configured to build a slave agent, where the slave agent is configured to implement a slave receiving operation of the data packet.
A chip verification apparatus 1100 according to an embodiment of the invention is described below in conjunction with fig. 11.
As shown in fig. 11, the chip verification device 1100 includes one or more processors 1110 and memory 1120.
The processor 1110 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the chip authentication device 1100 to perform desired functions.
The memory 1120 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, flash memory, and the like. One or more computer program instructions may be stored on a computer-readable storage medium and executed by processor 1110 to implement the authentication methods of the various embodiments of the present application described above and/or other desired functions.
In one example, the chip authentication device 1100 may further include: an input device 1130 and an output device 1140, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the input device 1130 may be a microphone or an array of microphones for capturing a speech input signal; may be a communications network connector for receiving the collected input signals from a cloud or other device; but may also include, for example, a keyboard, mouse, etc.
The output device 1140 may output various information including the determined distance information, direction information, etc. to the outside. Output devices 1140 may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, among others.
Of course, for simplicity, only some of the components of the chip authentication device 1100 relevant to the present application are shown in fig. 11, and components such as buses, input/output interfaces, and the like are omitted. In addition, the chip verification device 1100 may include any other suitable components depending on the particular application.
In addition to the methods, platforms, devices and apparatuses described above, embodiments of the present application may also be a computer readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps in the chip verification method according to various embodiments of the present application described above in this specification.
A computer-readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The concepts, principles and concepts of the invention have been described above in detail in connection with specific embodiments (including examples and illustrations). It will be appreciated by persons skilled in the art that embodiments of the invention are not limited to the specific forms disclosed above, and that many modifications, alterations and equivalents of the steps, methods, apparatus and components described in the above embodiments may be made by those skilled in the art after reading this specification, and that such modifications, alterations and equivalents are to be considered as falling within the scope of the invention. The scope of the invention is only limited by the claims.
Claims (13)
1. A method of chip verification, comprising:
constructing the chip verification platform based on a universal verification methodology UVM;
verifying the design of the chip by using the verification platform;
wherein the building of the chip verification platform based on the universal verification methodology UVM comprises:
constructing a data packet;
constructing a host agent for realizing host sending operation of the data packet;
and constructing a slave agent for realizing the slave receiving operation of the data packet.
2. A verification method according to claim 1 wherein said chip comprises a high definition multimedia interface, HDMI, interface chip.
3. The authentication method of claim 1 wherein the packets comprise video packets and audio packets.
4. A verification method according to claim 3, wherein said audio data packet includes a flag bit for indicating whether said audio data packet is transmitted successively with a next audio data packet.
5. An authentication method according to claim 3 or 4, wherein the host agent comprises a first channel for processing the video data packets and a second channel for processing the audio data packets.
6. A chip verification platform constructed based on universal verification methodology, UVM, for verifying a design of the chip, comprising:
a data packet;
the host agent is used for realizing host sending operation of the data packet;
and the slave agent is used for realizing the slave receiving operation of the data packet.
7. A verification platform as claimed in claim 6 wherein said chip comprises a High Definition Multimedia Interface (HDMI) interface chip.
8. The validation platform of claim 6, wherein the data packets comprise video data packets and audio data packets.
9. A verification platform as claimed in claim 8 wherein said audio data packet includes a flag bit to indicate whether said audio data packet is sent in succession with a next audio data packet.
10. A verification platform according to claim 8 or 9 wherein said host agent comprises a first channel for processing said video data packets and a second channel for processing said audio data packets.
11. A chip verification apparatus, comprising:
the construction module is used for constructing the chip verification platform based on a universal verification methodology UVM;
a verification module for verifying the design of the chip using the verification platform;
wherein the building block comprises:
a first constructing unit for constructing a data packet;
a second constructing unit, configured to construct a host agent, where the host agent is configured to implement a host sending operation of the data packet;
and the third construction unit is used for constructing a slave agent, and the slave agent is used for realizing the slave receiving operation of the data packet.
12. A chip verification apparatus, comprising:
a processor;
a memory;
an application program stored in the memory and configured to be executed by the processor, the application program comprising instructions for performing the chip verification method according to any one of claims 1-5.
13. A computer-readable storage medium storing a computer program for executing the chip verification method according to any one of claims 1 to 5.
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