CN116776784A - RTL code generation method and device, electronic equipment and storage medium - Google Patents
RTL code generation method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The application discloses an RTL code generation method, an RTL code generation device, electronic equipment and a storage medium, wherein the RTL code generation method comprises the following steps: obtaining a sub-module design file corresponding to each of a plurality of sub-modules, wherein each sub-module is obtained by decomposing a target module; respectively converting each submodule design file into submodule RTL codes through high-level synthesis; acquiring the connection relation corresponding to each interface to be connected in each sub-module; and generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code. The application solves the technical problem of low development efficiency of the large-scale integrated circuit design in the prior art.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a method and apparatus for generating an RTL code, an electronic device, and a storage medium.
Background
According to the research published by NEC (japan electric co.) in 2004, a chip design with 100-ten thousand logic gates typically requires 30 ten thousand lines of RTL (Register Transfer Level) code to be written. Therefore, it is not practical to design contemporary chips completely using the logic abstraction of the RTL level, and huge stresses are put on various links such as design, verification, integration, and the like. In contrast, modeling a system using a high-level language such as C, C ++, the code density can be compressed 7 to 10 times, which greatly eases design complexity. Therefore, at present, integrated circuit design is usually performed by using a high-level language, and then the high-level language is converted into RTL code through high-level synthesis.
However, the integration of large-scale integrated circuit designs by high-level integration is too long, sometimes even resulting in machine seizure due to too high resource occupation, greatly affecting development efficiency.
Disclosure of Invention
The application mainly aims to provide an RTL code generation method, an RTL code generation device, electronic equipment and a storage medium, and aims to solve the technical problem of low development efficiency of large-scale integrated circuit design in the prior art.
In order to achieve the above object, the present application provides a method for generating RTL code, including the steps of:
obtaining a sub-module design file corresponding to each of a plurality of sub-modules, wherein each sub-module is obtained by decomposing a target module;
respectively converting each submodule design file into submodule RTL codes through high-level synthesis;
acquiring the connection relation corresponding to each interface to be connected in each sub-module;
and generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
Optionally, the step of obtaining the connection relationship corresponding to each interface to be connected in each sub-module includes:
obtaining constraint rules and configuration files corresponding to the target modules;
Analyzing the RTL codes of the sub-modules based on the top information field in the configuration file, and determining interface information of interfaces to be connected in the sub-modules;
and determining the connection relation corresponding to the interfaces to be connected in each sub-module according to the constraint rule and the interface information.
Optionally, the step of generating the target module RTL code corresponding to the target module based on the connection relationship and each sub-module RTL code includes:
generating a top-level scale file based on the connection relation and the interface information;
connecting the interfaces to be connected by executing the top-level Scala file to generate a top-level module code;
and integrating the top module code and each sub-module RTL code to obtain a target module RTL code.
Optionally, the constraint rules include a synchronization constraint rule, a matching constraint rule, a loopback constraint rule, a mapping constraint rule, a configuration constraint rule, a disregard constraint rule, and an arbitration constraint rule.
Optionally, each sub-module includes at least one pair of sub-modules to be interconnected, and two sub-modules to be interconnected in the pair of sub-modules to be interconnected are subjected to data interconnection through the ping-pong operation module.
Optionally, the ping-pong operation module includes an input data selection unit, an output data selection unit, a first buffer unit and a second buffer unit, wherein,
the input data selecting unit is used for switching a first target buffer unit for input data storage, and the first target buffer unit comprises a first buffer unit and a second buffer unit;
the output data selection unit is used for switching a second target buffer unit for acquiring output data, and the second target buffer unit comprises a first buffer unit and a second buffer unit.
Optionally, the step of generating the target module RTL code corresponding to the target module based on the connection relationship and each sub-module RTL code further includes:
performing interface connection detection on the RTL code of the target module;
if the interface connection abnormality is detected, outputting connection abnormality reminding information.
The application also provides an RTL code generating device, which comprises:
the sub-module design file acquisition module is used for acquiring sub-module design files corresponding to the sub-modules respectively, wherein each sub-module is obtained by decomposing a target module;
the sub-module RTL code conversion module is used for respectively converting each sub-module design file into sub-module RTL codes through high-level synthesis;
The connection relation acquisition module is used for acquiring the connection relation corresponding to the interfaces to be connected in each sub-module;
and the target module RTL code generation module is used for generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
The application also provides an electronic device, which is entity equipment, comprising: the system comprises a memory, a processor and a program of the RTL code generating method which is stored in the memory and can be run on the processor, wherein the program of the RTL code generating method can realize the steps of the RTL code generating method when being executed by the processor.
The present application also provides a storage medium, which is a computer-readable storage medium, and the computer-readable storage medium stores thereon a program for implementing an RTL code generation method, where the program for implementing the RTL code generation method implements the steps of the RTL code generation method described above when executed by a processor.
The application provides a method, a device, electronic equipment and a storage medium for generating RTL codes, which are characterized in that sub-module design files corresponding to a plurality of sub-modules are obtained by decomposing a target module, so that the decomposition of an integrated circuit is realized, the design files of a larger integrated circuit are decomposed into sub-module design files of a plurality of smaller sub-modules, the sub-module design files are further respectively converted into the RTL codes of the sub-modules through high-level synthesis, the high-level synthesis of the sub-module design files is realized, the sub-module design files are far smaller than the design files of the whole large integrated circuit, the time and the resource occupancy rate of the high-level synthesis are effectively reduced, and the RTL codes of the target modules corresponding to the target modules are generated based on the connection relation and the RTL codes of the sub-modules, so that the RTL codes of the sub-modules after the decomposition are integrated into the RTL codes of the target modules corresponding to the larger integrated circuit, namely the RTL codes of the large integrated circuit are obtained. In this way, compared with the mode of high-level synthesis of the whole large-scale integrated circuit, the application can greatly reduce the time and the resource occupation rate of high-level synthesis by respectively carrying out high-level synthesis reconnection after modularization of the large-scale integrated circuit, overcomes the technical defects that the time for synthesizing the large-scale integrated circuit design by high-level synthesis is overlong, machine is blocked even because of overhigh resource occupation sometimes, greatly influences the development efficiency, and improves the development efficiency of the large-scale integrated circuit design.
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The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flowchart of a first embodiment of an RTL code generating method according to the present application;
fig. 2 is a schematic structural diagram of a ping-pong operation module according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a wire bonding tool according to an embodiment of the present application;
FIG. 4 is a flowchart of a second embodiment of an RTL code generating method according to the present application;
FIG. 5 is a schematic diagram illustrating an embodiment of an RTL code generating apparatus according to the present application;
FIG. 6 is a schematic diagram of a device structure of a hardware operating environment related to an RTL code generating method according to an embodiment of the present application.
The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
In order to make the above objects, features and advantages of the present application more comprehensible, the following description of the embodiments accompanied with the accompanying drawings will be given in detail. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
Example 1
An embodiment of the present application provides an RTL code generating method, in a first embodiment of the RTL code generating method of the present application, referring to fig. 1, including the steps of:
step S10, a sub-module design file corresponding to each of a plurality of sub-modules is obtained, wherein each sub-module is obtained by decomposing a target module;
the execution subject of the method of this embodiment may be an RTL code generating device, or may be an RTL code generating terminal device or a server, and this embodiment uses the RTL code generating device as an example, where the RTL code generating device may be integrated on a terminal device such as a smart phone, a tablet computer, or a computer that has a data processing function.
In this embodiment, it should be noted that, HLS for short is a process of automatically converting a logic structure described in a High-level language into a circuit model described in a low-level language; the target module refers to an integrated circuit whole which needs to be designed; the sub-module is a module obtained by decomposing the target module; the submodule design file refers to a file of a logic structure of a submodule described by a high-level language, wherein the high-level language refers to a programming language which can better meet the software development requirements, and the programming language comprises C, C ++, systemC and the like, has higher programmability, readability and maintainability, can better support the complexity of software development, uses the high-level language to model a system, can compress code density by 7 to 10 times, and greatly relieves the design complexity.
After determining an integrated circuit to be designed, a related technician may decompose the integrated circuit design into a plurality of sub-modules according to actual needs, and describe logic structures corresponding to the sub-modules by using high-level languages, so as to obtain sub-module design files corresponding to the sub-modules, where a specific decomposition rule for decomposing the integrated circuit design into the plurality of sub-modules may be determined according to actual situations, which is not limited in this embodiment; furthermore, the RTL code generating device obtains a sub-module design file corresponding to each pre-designed sub-module.
Optionally, each sub-module includes at least one pair of sub-modules to be interconnected, and two sub-modules to be interconnected in the pair of sub-modules to be interconnected are subjected to data interconnection through the ping-pong operation module.
In this embodiment, it should be noted that, since each sub-module is separately written and separately high-level synthesized in this embodiment, sub-modules described by sub-module RTL codes obtained after high-level synthesis of each sub-module design file are independent of each other, but data transmission may be required between each sub-module, and data transmission between each sub-module may be connected by using an AXI (Advanced eXtensible Interface, a bus protocol proposed by an ARM company), however, the AXI manner is not friendly to the design of a large module, a problem of excessively long high-level synthesis time often occurs, and multiple reading and multiple writing are not supported, and in case that clocks between two modules performing data transmission are not synchronous, latency may be generated, resulting in an increase of overall data stream processing time.
When each sub-module is designed and written, at least one pair of sub-modules to be interconnected, which needs to be clocked, can be determined according to actual conditions such as clock information in a data transmission process, a ping-pong operation module is arranged between two sub-modules to be interconnected in each pair of sub-modules to be interconnected, and the two sub-modules to be interconnected are subjected to data interconnection control through the ping-pong operation module, wherein the ping-pong operation module at least comprises two buffer units, the ping-pong operation module is used for switching data from one module into the two buffer units according to beats and outputting the data into the other module according to beats opposite to the storing mode, for example, to transmit a data stream of the module 1 into a module 2 which is not synchronized with the clock of the module 1, the ping-pong operation module can be arranged between the module 1 and the module 2, and the data of the module 1 is stored into a first buffer unit of the ping-pong operation module in a first buffer period; in a second buffering period, switching the buffer unit of the input data into a second buffer unit so as to switch the data of the module 1 into the second buffer unit stored in the ping-pong operation module, and synchronously outputting the data buffered in the first buffer unit into the module 2; in a third buffering period, the buffer unit of the input data is switched back to the first buffer unit to switch the data of the module 1 into the first buffer unit stored in the ping-pong operation module, and synchronously, the buffer unit of the output data is switched to the second buffer unit to output the data buffered in the second buffer unit into the module 2, and the buffer units of the input data and the buffer units of the output data are switched in the same manner as described above in the following buffering period. In this way, the data stream can be transmitted without any pause, and the input data stream and the output data stream of the ping-pong operation module can be continuously and continuously without any pause, so that the ping-pong operation module is very suitable for carrying out pipeline processing on the data stream.
Optionally, the ping-pong operation module includes an input data selection unit, an output data selection unit, a first buffer unit and a second buffer unit, wherein,
the input data selecting unit is used for switching a first target buffer unit for input data storage, and the first target buffer unit comprises a first buffer unit and a second buffer unit;
the output data selection unit is used for switching a second target buffer unit for acquiring output data, and the second target buffer unit comprises a first buffer unit and a second buffer unit.
The ping-pong operation module comprises an input data selection unit, an output data selection unit, a first buffer unit and a second buffer unit, wherein the input data selection unit is used for switching a first target buffer unit for input data storage, and the first target buffer unit comprises the first buffer unit and the second buffer unit; the output data selection unit is used for switching a second target buffer unit for acquiring output data, and the second target buffer unit comprises a first buffer unit and a second buffer unit; the first buffer unit may be a memory or a register; the second buffer unit may be a memory or a register.
In a possible embodiment, referring to fig. 2, to transmit the data stream of the module 1 to the module 2 that is not synchronized with the clock of the module 1, a ping-pong operation module may be disposed between the module 1 and the module 2, and in a first buffering period, a first target buffer unit of the input data is switched to a first buffer unit by the input data selection unit, so as to store the data of the module 1 in the first buffer unit; in a second buffering period, switching a first target buffer unit of input data into a second buffer unit through an input data selection unit so as to switch the data of the module 1 into the second buffer unit, and synchronously switching a second target buffer unit of output data into a first buffer unit through an output data selection unit so as to output the data buffered in the first buffer unit into the module 2 for data processing by the module 2; in a third buffering period, the first target buffer unit of the input data is switched back to the first buffer unit by the input data selecting unit to switch the data of the module 1 to be stored in the first buffer unit, the buffer unit of the output data is switched to the second buffer unit by the output data selecting unit to output the data buffered in the second buffer unit to the module 2 in synchronization, and the buffer units of the input data and the buffer units of the output data are switched in the same manner as described above in the subsequent buffering period. In this way, the input data selecting unit and the output data selecting unit are used for switching the first target buffer unit and the second target buffer unit according to the beat and the mutual matching, so that the buffered data stream can be sent from one module to the other module for operation and processing without pause, the ping-pong operation module is taken as a whole, the data is seen at the two ends of the module, the input data stream and the output data stream are continuous and have no pause, and therefore, the device is very suitable for carrying out pipeline processing on the data stream.
Step S20, converting each sub-module design file into a sub-module RTL code through high-level synthesis;
after a plurality of sub-module design files are acquired, respectively performing high-level synthesis on each sub-module design file, and converting each sub-module design file into a corresponding sub-module RTL code.
Step S30, obtaining the connection relation corresponding to each interface to be connected in each sub-module;
and step S40, generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
In this embodiment, it should be noted that, because each sub-module is written separately and synthesized at a high level, sub-modules described by RTL codes of sub-modules obtained after high-level synthesis of design files of each sub-module are independent of each other, and a complete connected target module can be obtained only after connecting interfaces to be connected in each sub-module, where one or more interfaces to be connected may be provided in each sub-module.
The connection relationship may be information of a target interface connected with the interfaces to be connected, or may be constraint rules of the interfaces, and the connection relationship of each interface to be connected may be determined according to actual needs, which is not limited in this embodiment; the constraint rule refers to a rule that constrains a connection mode of the signal line, and specific constraint contents and functions can be set and adjusted according to actual situations, which is not limited in this embodiment.
In a possible implementation manner, the manner of generating the target module RTL code corresponding to the target module based on the connection relationship and each sub-module RTL code may be manually writing the connection code, or may be automatically completed through a preset connection tool, where the connection tool may be developed or an existing connection tool may be used according to actual needs, which is not limited in this embodiment.
In a possible embodiment, referring to fig. 3, the wiring tool includes a preparation part, a python (a programming language) part, a Scala (a programming language) part, and a finalization part, wherein the preparation part includes setting a configuration file and constraint rules manually in advance; the python part is used for analyzing the RTL codes of the sub-modules to generate interface information and further generating a Scala file based on the interface information and constraint rules; the Scala part is used for instantiating and connecting interfaces to be connected in the sub-modules based on the Scala file to generate a top-level module code; the ending part is used for integrating the top module code and each sub-module RTL code to generate a target module RTL code, and can further perform fault detection, adjust constraint rules when faults exist, and regenerate the target module RTL code.
Optionally, the step of generating the target module RTL code corresponding to the target module based on the connection relationship and each sub-module RTL code further includes:
step S50, performing interface connection detection on the RTL code of the target module;
step S60, if the interface connection abnormality is detected, outputting connection abnormality reminding information.
In this embodiment, it should be noted that after the integrated circuit design is completed, connection conditions of each interface in the integrated circuit need to be checked to check whether the circuit design and manufacture are correct or not, whether the quality is qualified or not, so as to ensure that the integrated circuit can work normally and safely when applied, and for unqualified products, problems can be found in time through testing, unqualified reasons are found, and adjustment is performed.
For example, the interface connection detection may be performed on the RTL code of the target module by an automatic testing device or manually, for example, whether the setting of the suspension pins is correct, whether the connection between the interfaces is correct, etc.; if the interface connection abnormality is detected, outputting connection abnormality reminding information so that related personnel can timely adjust the connection condition of the interfaces or regenerate a target module RTL code corresponding to the information target module after changing the connection rule among the interfaces based on the connection abnormality reminding information.
In this embodiment, by obtaining the sub-module design files corresponding to the sub-modules, where each sub-module is obtained by decomposing the target module, decomposing the design file of the relatively large-scale integrated circuit into the sub-module design files of the relatively small-scale sub-modules, further, converting each sub-module design file into the sub-module RTL code through high-level synthesis, and implementing high-level synthesis of each sub-module design file, where the sub-module design file is far smaller than the design file of the whole large-scale integrated circuit, so that the time and resource occupation rate of high-level synthesis of each sub-module design file can be effectively reduced, and further, by obtaining the connection relation corresponding to the interface to be connected in each sub-module, generating the target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code, implementing connection of each decomposed small-module, and integrating the sub-module RTL code of each decomposed small-module into the target module RTL code corresponding to the large-scale integrated circuit. In this way, compared with the mode of high-level synthesis of the whole large-scale integrated circuit, the application can greatly reduce the time and the resource occupation rate of high-level synthesis by respectively carrying out high-level synthesis reconnection after modularization of the large-scale integrated circuit, overcomes the technical defects that the time for synthesizing the large-scale integrated circuit design by high-level synthesis is overlong, machine is blocked even because of overhigh resource occupation sometimes, greatly influences the development efficiency, and improves the development efficiency of the large-scale integrated circuit design.
Example two
Further, referring to fig. 4, in the second embodiment of the present application, the same or similar contents as those of the above embodiment may be referred to the above description, and will not be repeated. On this basis, the step of obtaining the connection relation corresponding to the interfaces to be connected in each sub-module, and generating the target module RTL code corresponding to the target module based on the connection relation and the sub-module RTL code includes:
step S31, constraint rules and configuration files corresponding to the target modules are obtained;
in this embodiment, it should be noted that, for a larger target module, the more and more complex the signals in the module, the more numerous signals are, and if a method of manually performing the connection one by one is used, the time and effort are wasted.
After determining an integrated circuit to be designed, a related technician can set constraint rules and configuration files according to actual requirements and the like of the integrated circuit, and can directly acquire constraint rules and configuration files corresponding to the target modules when connection is required, wherein the configuration files are used for configuring module names, constraint names, top-layer paths, module types, reset polarities and the like of all sub-modules in the target modules; the constraint rule refers to a rule that constrains a connection mode of the signal line, and specific constraint contents and functions can be set and adjusted according to actual situations, which is not limited in this embodiment.
Optionally, the constraint rules include a synchronization constraint rule, a matching constraint rule, a loopback constraint rule, a mapping constraint rule, a configuration constraint rule, a disregard constraint rule, and an arbitration constraint rule.
In this embodiment, the constraint rules include a synchronization constraint rule, a matching constraint rule, a loopback constraint rule, a mapping constraint rule, a configuration constraint rule, a neglect constraint rule and an arbitration constraint rule, where the synchronization constraint rule is used to connect synchronization signals between a processor and a load, and between a storage unit; the matching constraint rule is used for connecting an AXIS (AXI-Stream, one of AXI protocols) interface and a RAM (random access memory ) interface between the sub-modules; the loop-back constraint rule is used for loop-back signal connection of the sub-module; the mapping constraint rule is used for mapping the interface to the top layer; the configuration constraint rules are used to map interfaces to top layers, such as direct_i interfaces; the neglecting constraint rule is used for suspending the interface; the arbitration constraint rule is used for connecting interfaces needing arbitration.
In a possible implementation manner, the interfaces to be connected can be connected in a fuzzy matching manner, for example, wild cards can be set in the constraint rule, and fuzzy matching can be performed on signal names by applying the wild cards; the constrained signals, the signals with the same names, the related stream (streaming), the RAM, the FIFO (First Input First Output, first-in first-out) and other interfaces can be directly connected through a fuzzy matching algorithm.
Step S32, analyzing each sub-module RTL code based on the top information field in the configuration file, and determining interface information of interfaces to be connected in each sub-module;
the method includes the steps of reading a top-level information field from the configuration file, determining the interface type of each interface to be connected based on the top-level information field, analyzing the RTL code of each sub-module based on the interface type of each interface to be connected, and determining the interface information of a plurality of interfaces to be connected distributed in each sub-module.
In a possible implementation manner, the manner of analyzing the RTL code of each sub-module based on the interface type of each interface to be connected and determining the interface information of the plurality of interfaces to be connected distributed in each sub-module may be to determine the type of the interface to be searched, and determine the target search key corresponding to each type of the interface to be searched according to the mapping relationship between the preset type of the interface and the search key, thereby searching from the RTL code of each sub-module based on each search key to obtain the interface to be connected corresponding to each type of the interface to be searched and the interface information of the interface to be connected corresponding to each type of the interface to be searched. For example, the correspondence relationship of the interface type, the search key, and the output information may be referred to table 1:
TABLE 1
And step S33, determining the connection relation corresponding to the interfaces to be connected in each sub-module according to the constraint rule and the interface information.
The information matching is performed on the interface information of each to-be-connected interface according to the constraint rule, and the information of the target interface connected with each to-be-connected interface is determined, wherein the information of the target interface can be the interface name, the interface type and the like of the target interface, and the information of the target interface can represent the connection relationship corresponding to each to-be-connected interface.
Optionally, the step of generating the target module RTL code corresponding to the target module based on the connection relationship and each sub-module RTL code includes:
step S41, generating a top-level scale file based on the connection relation and the interface information;
in this embodiment, it should be noted that, because each sub-module is written separately and synthesized at a high level in this embodiment, sub-modules described by RTL codes of sub-modules obtained after high-level synthesis of design files of each sub-module are independent of each other, but signal transmission may be required between each sub-module, so that interfaces in each sub-module need to be connected to obtain a complete target module that is mutually communicated.
After the RTL code is parsed to obtain the interface information of each interface to be connected in each sub-module, a top-level scalea file corresponding to the target module is generated based on each interface information and the connection relation through a pre-written python script.
Step S42, connecting the interfaces to be connected by executing the top-layer Scala file to generate a top-layer module code;
step S43, integrating the top module code and each sub module RTL code to obtain a target module RTL code.
By way of example, through a pre-written scale grammar, the top-level scale file is automatically executed, the writing of top-level module codes for connecting the interfaces to be connected is automatically realized, and the top-level module codes and the sub-module RTL codes are integrated, so that the target module RTL codes of the target module can be obtained.
In a possible implementation manner, the step of writing the top-level module code for connecting each to-be-connected interface may include: defining clock, reset and control signals (signals representing information such as start, end, busy, idle and the like), mapping interface information into interfaces, mapping clock domains and renaming the interfaces, and further connecting the interfaces to be connected through constraint rules to connect registers.
In the embodiment, the automatic connection of each interface to be connected in the sub-module can be realized through constraint rules, and the decomposed sub-modules are communicated, so that the automatic connection efficiency is obviously improved compared with the manual writing of connection codes.
Example III
Further, an embodiment of the present application further provides an RTL code generating apparatus, referring to fig. 5, where the RTL code generating apparatus includes:
the sub-module design file acquisition module is used for acquiring sub-module design files corresponding to the sub-modules respectively, wherein each sub-module is obtained by decomposing a target module;
the sub-module RTL code conversion module is used for respectively converting each sub-module design file into sub-module RTL codes through high-level synthesis;
the connection relation acquisition module is used for acquiring the connection relation corresponding to the interfaces to be connected in each sub-module;
and the target module RTL code generation module is used for generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
Optionally, the connection relation obtaining module is further configured to:
obtaining constraint rules and configuration files corresponding to the target modules;
Analyzing the RTL codes of the sub-modules based on the top information field in the configuration file, and determining interface information of interfaces to be connected in the sub-modules;
and determining the connection relation corresponding to the interfaces to be connected in each sub-module according to the constraint rule and the interface information.
Optionally, the target module RTL code generating module is further configured to:
generating a top-level scale file based on the connection relation and the interface information;
connecting the interfaces to be connected by executing the top-level Scala file to generate a top-level module code;
and integrating the top module code and each sub-module RTL code to obtain a target module RTL code.
Optionally, after the operation of generating the target module RTL code corresponding to the target module based on the connection relationship and each of the sub-module RTL codes, the RTL code generating apparatus further includes an anomaly detection module, where the anomaly detection module is configured to:
performing interface connection detection on the RTL code of the target module;
if the interface connection abnormality is detected, outputting connection abnormality reminding information.
The RTL code generating device provided by the invention adopts the RTL code generating method in the embodiment, and solves the technical problem of lower development efficiency of the large-scale integrated circuit design in the prior art. Compared with the prior art, the beneficial effects of the RTL code generating device provided by the embodiment of the present invention are the same as those of the RTL code generating method provided by the foregoing embodiment, and other technical features of the RTL code generating device are the same as those disclosed by the foregoing embodiment method, which are not described herein in detail.
Example IV
Further, an embodiment of the present invention provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the RTL code generating method of the above embodiments.
Referring now to fig. 6, a schematic diagram of an electronic device suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as bluetooth headsets, mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), car terminals (e.g., car navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 6 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
As shown in fig. 6, the electronic device may include a processing means (e.g., a central processing unit, a graphic processor, etc.) that may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) or a program loaded from a storage means into a Random Access Memory (RAM). In the RAM, various programs and arrays required for the operation of the electronic device are also stored. The processing device, ROM and RAM are connected to each other via a bus. An input/output (I/O) interface is also connected to the bus.
In general, the following systems may be connected to the I/O interface: input devices including, for example, touch screens, touch pads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices including, for example, liquid Crystal Displays (LCDs), speakers, vibrators, etc.; storage devices including, for example, magnetic tape, hard disk, etc.; a communication device. The communication means may allow the electronic device to communicate with other devices wirelessly or by wire to exchange arrays. While electronic devices having various systems are shown in the figures, it should be understood that not all of the illustrated systems are required to be implemented or provided. More or fewer systems may alternatively be implemented or provided.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from ROM. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by a processing device.
The electronic equipment provided by the invention adopts the RTL code generation method in the embodiment, and solves the technical problem of lower development efficiency of the large-scale integrated circuit design in the prior art. Compared with the prior art, the electronic device provided by the embodiment of the invention has the same beneficial effects as the RTL code generation method provided by the embodiment, and other technical features in the electronic device are the same as the features disclosed by the method of the embodiment, and are not repeated here.
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof. In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Example five
Further, the present embodiment provides a computer-readable storage medium having computer-readable program instructions stored thereon for executing the RTL code generating method in the above-described embodiment.
The computer readable storage medium according to the embodiments of the present invention may be, for example, a usb disk, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this embodiment, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, or device. Program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The above-described computer-readable storage medium may be contained in an electronic device; or may exist alone without being assembled into an electronic device.
The computer-readable storage medium carries one or more programs that, when executed by an electronic device, cause the electronic device to: obtaining a sub-module design file corresponding to each of a plurality of sub-modules, wherein each sub-module is obtained by decomposing a target module; respectively converting each submodule design file into submodule RTL codes through high-level synthesis; acquiring the connection relation corresponding to each interface to be connected in each sub-module; and generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules described in the embodiments of the present disclosure may be implemented in software or hardware. Wherein the name of the module does not constitute a limitation of the unit itself in some cases.
The computer readable storage medium provided by the application stores the computer readable program instructions for executing the RTL code generation method, and solves the technical problem of low development efficiency of large-scale integrated circuit design in the prior art. Compared with the prior art, the beneficial effects of the computer readable storage medium provided by the embodiment of the application are the same as those of the RTL code generating method provided by the above embodiment, and are not described in detail herein.
Example six
Further, the present application also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the RTL code generating method as described above.
The computer program product provided by the application solves the technical problem of low development efficiency of large-scale integrated circuit design in the prior art. Compared with the prior art, the beneficial effects of the computer program product provided by the embodiment of the present application are the same as those of the RTL code generating method provided by the above embodiment, and are not described herein.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein, or any application, directly or indirectly, within the scope of the application.
Claims (10)
1. An RTL code generating method, characterized in that the RTL code generating method includes the steps of:
obtaining a sub-module design file corresponding to each of a plurality of sub-modules, wherein each sub-module is obtained by decomposing a target module;
respectively converting each submodule design file into submodule RTL codes through high-level synthesis;
acquiring the connection relation corresponding to each interface to be connected in each sub-module;
and generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
2. The RTL code generating method of claim 1, wherein the step of obtaining the connection relationship corresponding to each interface to be connected in each sub-module includes:
obtaining constraint rules and configuration files corresponding to the target modules;
analyzing the RTL codes of the sub-modules based on the top information field in the configuration file, and determining interface information of interfaces to be connected in the sub-modules;
and determining the connection relation corresponding to the interfaces to be connected in each sub-module according to the constraint rule and the interface information.
3. The RTL code generating method according to claim 2, wherein the step of generating the target module RTL code corresponding to the target module based on the connection relation and each of the sub-module RTL codes includes:
Generating a top-level scale file based on the connection relation and the interface information;
connecting the interfaces to be connected by executing the top-level Scala file to generate a top-level module code;
and integrating the top module code and each sub-module RTL code to obtain a target module RTL code.
4. The RTL code generation method of claim 2, wherein the constraint rules include a synchronization constraint rule, a matching constraint rule, a loopback constraint rule, a mapping constraint rule, a configuration constraint rule, a disregard constraint rule, and an arbitration constraint rule.
5. The RTL code generating method of claim 1, wherein each of the sub-modules includes at least one pair of sub-modules to be interconnected, and two sub-modules to be interconnected in the pair of sub-modules to be interconnected are data interconnected through a ping-pong operation module.
6. The RTL code generating method of claim 5, wherein the ping-pong operation module includes an input data selecting unit, an output data selecting unit, a first buffering unit, and a second buffering unit, wherein,
the input data selecting unit is used for switching a first target buffer unit for input data storage, and the first target buffer unit comprises a first buffer unit and a second buffer unit;
The output data selection unit is used for switching a second target buffer unit for acquiring output data, and the second target buffer unit comprises a first buffer unit and a second buffer unit.
7. The RTL code generating method according to any one of claims 1 to 6, wherein the step of generating the target module RTL code corresponding to the target module based on the connection relation and each of the sub-module RTL codes further comprises:
performing interface connection detection on the RTL code of the target module;
if the interface connection abnormality is detected, outputting connection abnormality reminding information.
8. An RTL code generating apparatus, characterized in that the RTL code generating apparatus includes:
the sub-module design file acquisition module is used for acquiring sub-module design files corresponding to the sub-modules respectively, wherein each sub-module is obtained by decomposing a target module;
the sub-module RTL code conversion module is used for respectively converting each sub-module design file into sub-module RTL codes through high-level synthesis;
the connection relation acquisition module is used for acquiring the connection relation corresponding to the interfaces to be connected in each sub-module;
and the target module RTL code generation module is used for generating a target module RTL code corresponding to the target module based on the connection relation and each sub-module RTL code.
9. An electronic device, the electronic device comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the steps of the RTL code generation method of any one of claims 1 to 7.
10. A storage medium, characterized in that the storage medium is a computer-readable storage medium having stored thereon a program that implements an RTL code generation method, the program that implements the RTL code generation method being executed by a processor to implement the steps of the RTL code generation method according to any one of claims 1 to 7.
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