CN102147447B - Method for controlling data transparent transfer as well as flexible label connection method and device thereof - Google Patents
Method for controlling data transparent transfer as well as flexible label connection method and device thereof Download PDFInfo
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Abstract
The embodiment of the invention discloses a method for controlling data transparent transfer as well as a flexible label connection method and a device thereof, which can be used for controlling the field transparent transfer of the data output by each module for processing data in an FPGA (field programmable gate array). The interface mode between modules is flexible label connection. The method comprises the following steps: generating a corresponding data label for each module; packaging data input into the FPGA with the data label; controlling the direction for each module to output data by changing the content of the data label carried by each output module when data are output; and finishing the transparent transfer of output data between modules. The embodiment of the invention solves the technical problem of the transparent transfer of output data between modules in the FPGA under the conditions that extra internal chip resources and an internal memory are not occupied and the original time sequence of the internal signal is not changed.
Description
Technical field
The present invention relates to the electronic design technology field, particularly a kind of method, flexible label method of attachment and device thereof of controlling data penetration transmission.
Background technology
Increasing rapidly of the scale of field programmable logic device (FPGA) and integration density can be realized increasing system or subsystem function in FPGA, FPGA has become the first-selected solution of more and more complication systems.
In the commissioning test process of large-scale F PGA chip, the state indication of interworking of the hardware and software of the key that betides in a large number FPGA inside is arranged, must be by the specific output pin output of FPGA, state and the correctness of the operation of indication FPGA built-in function.
But, because the area of single FPGA chip is limited, available pin sum can not synchronously increase with the raising of integrated level, therefore be specifically designed to the pin number wretched insufficiency of monitoring FPGA internal operation state, therefore, how effectively and all sidedly to observe and monitor difficult point and the key point that FPGA internal operation state becomes FPGA debugging.
At present, measure FPGA internal state method and have two kinds:
A kind ofly be, the tested node in inside is linked external terminal, then pop one's head in by logic analysis and be connected to the respective channel of outside logic analyser, according to pin positions and the title of measured signal, the logic analysis passage is named.But this measuring method can only realize connection and the measurement of 1 pair 1; And each FPGA debugging pin can only corresponding internal signal node; In addition, because internal signal node is fixed, change new measured node, must redistribute pin, recompilate design document, not only waste time and energy but also can change thus original sequential of signal.
Another kind is, utilizes the kernel that is used for on-chip debug of the commercial version that FPGA manufacturer provides, and this kernel adopts JTAG as communication interface, and this kernel uses the internal resource of FPGA, can read online, in real time any signal of FPGA internal logic.Its ultimate principle is to utilize untapped Block Ram in FPGA, the signal (register or netting twine) that needs are observed is deposited in these Block Ram in real time, then, the trigger condition of setting according to the user generates specific address decoding selection data reading, and the data of reading are delivered to the JTAG mouth, and then, the computing machine that is connected with this JTAG mouth, can draw timing waveform according to the Data Dynamic ground of JTAG mouth output, so that people's analysis.But the timing waveform that this measuring method obtains is not the timing waveform of True Data, but satisfies the timing waveform of storing data when setting trigger condition in storer, can only regularly provide state analysis for the user, can not provide state analysis for the user in real time; In addition, debugging kernel itself has taken chip internal resource and inner storer, and is larger if the FPGA design takies resource, the debugging kernel will with design contention for resources own, affect the development and Design of FPGA; If remove this kernel after debugging, the FPGA design needs to recompilate, and will change the sequential of internal circuit this moment.
Summary of the invention
In order to solve the problems of the technologies described above, the embodiment of the present invention provides a kind of method, flexible label method of attachment and device thereof of controlling data penetration transmission, additionally do not taking chip internal resource and internal storage to solve, and do not change in the front situation of the original sequential of internal signal, complete the technical matters of the transparent transmission of inner each intermodule output data of FPGA.
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of method of controlling data penetration transmission, be used for controlling the inner transparent transmission that is used for the modules output data of data processing of field programmable logic device FPGA, described method comprises: the interface mode that arranges between described modules is the interface mode that flexible label connects; Described method also comprises:
For modules generates corresponding data label;
The data and the described data label that are input to FPGA inside are packaged together;
By changing the content of carrying described data label when modules is exported data, control the direction of described modules output data, complete the transparent transmission of intermodule output data.
Preferably, described data label for modules generation correspondence comprises:
Control module in described programmable logic device (PLD) FPGA is that modules generates corresponding data label; Perhaps
The outer computing machine of described programmable logic device (PLD) FPGA is that modules generates corresponding data label.
Preferably, described data label comprises: frame effectively identifies, transparent transmission is processed sign and session field number.
Preferably, the described interface mode that arranges between described modules is that the interface mode that flexible label connects specifically comprises:
For the input interface of each module arranges tag decoder, output interface arranges code tag, and according to the formatted output data of the flexible label of setting.
Preferably, described method also comprises:
In the time need to testing the output data of each module, generate the label substance of these module output data of transparent transmission, and control this module and add the content of described label in the output after processing, so that the output data of this module to the FPGA test interface, are convenient to test.
Accordingly, the embodiment of the present invention also provides a kind of flexible label method of attachment, is applied to field programmable logic device FPGA inner for the connection between the modules of data processing, and described method comprises:
Reception is input to the data of FPGA inside, and described data are the data of encapsulation of data label;
Described data are carried out decapsulation, and the data after decapsulation are carried out respective handling;
Receive change described module output stream to label substance;
Adding described label substance to described processing exports in the data label of data afterwards;
Output data according to the interface mode of the flexible label of setting after to described interpolation label substance encapsulate, and the data after encapsulate output to the module of described label substance sensing.
Preferably, the interface mode of described flexible label according to setting is:
Export outside data layout to according to FPGA and set the interface mode that the flexible label between the inner modules of FPGA connects.
Preferably, described method also comprises: the data way of output of controlling between described modules is the way of output of first in first out.
Accordingly, the embodiment of the present invention provides a kind of device of controlling data penetration transmission, is used for controlling the inner transparent transmission that is used for the modules output data of data processing of field programmable logic device FPGA, and described device comprises
Setting unit, the interface mode that is used for arranging between described modules is the interface mode that flexible label connects;
The data label generation unit is used to modules to generate corresponding data label;
Encapsulation unit, the data and the described data label that are used for being input to FPGA inside are packaged together;
Control module, the content of carrying described data label when being used for by change modules output data is controlled the direction that described modules is exported data, completes the transparent transmission of intermodule output data.
Preferably, also comprise:
The label substance generation unit is used for generating the label substance of these module output data of transparent transmission in the time need to testing the output data of a module of described modules;
Described control module also is used for controlling this module and adds the content of described label in the output after processing, so that the output data of this module to the FPGA test interface, are convenient to test.
The embodiment of the present invention also provides a kind of flexible label coupling arrangement, is applied to field programmable logic device FPGA inner for the connection between the modules of data processing, and described device comprises:
The first receiving element is used for receiving the data that are input to FPGA inside, and described data are the data of encapsulation of data label;
Decapsulation unit is used for described data are carried out decapsulation;
Processing unit is used for the data after described decapsulation unit decapsulation are carried out respective handling;
The second receiving element, be used for receiving change described module output stream to label substance;
Adding device is used for adding described label substance to data label that data are exported in described processing afterwards;
Encapsulation unit is used for interface mode according to the flexible label of the setting output data after to described interpolation label substance and encapsulates;
Transmitting element is used for the data after described encapsulation unit encapsulation are outputed to the module that described label substance points to.
Preferably, also comprise:
The first in first out module is used for the connection between described modules, and the data of processing according to the order buffer memory modules of first in first out.
Can be found out by such scheme, be first the data label corresponding to modules generation of FPGA inside; Data and the described data label that will be input to FPGA inside are packaged together again, and the content of carrying described data label when changing modules output data is controlled the direction of described modules output data, completes the transparent transmission that intermodule is exported data.Realized the state of each functional module of FPGA content is tested, this technical scheme in the situation that flexibly connect technology and data tag technology combines, is completed the intermodular data transparent transmission and to the test of any functional module of FPGA inside with module.Realized additionally not taking chip internal resource and internal storage, do not changed under the original sequential prerequisite of internal signal, reached flexible, the efficient test to the FPGA inner function module.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
A kind of process flow diagram of controlling the method for data penetration transmission that Fig. 1 provides for the embodiment of the present invention;
The schematic diagram of the module of the FPGA content that Fig. 2 provides for the embodiment of the present invention;
The process flow diagram of a kind of flexible label method of attachment that Fig. 3 provides for the embodiment of the present invention;
A kind of structural representation of controlling the device of data penetration transmission that Fig. 4 provides for the embodiment of the present invention;
The structural representation of a kind of flexible label coupling arrangement that Fig. 5 provides for the embodiment of the present invention;
The structural representation of the Speaker Identification FPGA built-in function that Fig. 6 provides for the embodiment of the present invention;
FPGA inner structure schematic diagram after the interpolation FIFO that Fig. 7 provides for the embodiment of the present invention;
The structural representation that Fig. 8 tests for the FPGA internal signal that the embodiment of the present invention provides;
The structural representation of the FPGA data penetration transmission that Fig. 9 provides for the embodiment of the present invention.
Embodiment
In the embodiment of the present invention, the interface mode that connects based on flexible label is set between the FPGA inner function module first; Secondly, according to unified rule, for each functional module arranges corresponding data label, complete flexibly connecting between modules; At last, when needs are tested certain module, by changing the content of the corresponding data label of this module, make the output data of this module directly be sent to the FPGA test interface, complete test, that is to say, module in the situation that flexibly connect technology and data tag technology combines, is completed the intermodular data transparent transmission and to the test of any functional module of FPGA inside.This implementation procedure is not additionally taking chip internal resource and internal storage, does not change under the original sequential prerequisite of internal signal, can test flexibly each functional module of FPGA inside.
In embodiments of the present invention, the Signal Transparent Transmission Technology of intermodular data refers to that former notebook data will be through transferring to next module after the processing of a certain module again, takes now certain control technology to make data see through a certain module and does not add to process and transfer to next module.
Data label refers to additional one section excessive data section between originally continuous data segment, to indicate the attribute of this segment data.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.
See also Fig. 1, it is a kind of process flow diagram of controlling the method for data penetration transmission provided by the invention, and the method is used for controlling the inner transparent transmission that is used for the modules output data of data processing of field programmable logic device FPGA, and described method comprises step:
Step 101: the interface mode that arranges between described modules is the interface mode that flexible label connects; This step is optional mode, after arranging, and follow-up can directly the use.
A kind of mode is: on the input interface for each module, tag decoder is set, output interface arranges code tag, and the formatted output data that connect according to the flexible label of setting.Wherein, the structural drawing that the increase flexible label connects between each functional module of former FPGA inside as shown in Figure 2.In the present embodiment, the functional module in FPGA is take 3 modules as example, and namely module 1.Module 2 and module 3.
As shown in Figure 2, each functional module outbound course arranges encoding function, thereby can unify according to the flexible label formatted output data of setting; The module input interface of each function arranges decoding function, the flexible label data layout that can decode and set.
Step 102: for described modules generates corresponding data label; That is to say, according to unified rule, for described modules generates corresponding data label.Wherein, described data label can be the data label of some bits, can comprise: frame effectively identifies, transparent transmission is processed sign and session field number, can also comprise reserved field etc.
A kind of embodiment that generates corresponding data label is, can be that modules generates corresponding data label by the control module of described programmable logic device (PLD) FPGA inside;
The another kind of embodiment that generates corresponding data label is: can be that modules generates corresponding data label by the computing machine of described programmable logic device (PLD) FPGA outside.
Certainly, can be also that modules generates corresponding data label by operating personnel, but be not limited to this.
Step 103: data and the described data label that will be input to FPGA inside are packaged together;
Such as, described data label is the data label of some bits, can be together with some data encapsulation, and encapsulation process can externally be carried out, and also can carry out in inside by the control module of FPGA inside.
Suppose, the data (D) of former input FPGA inside are: D1, D2, D3 ..., Dn ..., after encapsulation of data label (F) be: F1, D1, D2 ..., Di, F2, Di+1, Di+2 ..., Dj, F3, Dj+1, Dj+2 ..., Dk ...But be not limited to this.
Step 104: by changing the content of carrying described data label when modules is exported data, control the direction of described modules output data, complete the transparent transmission of intermodule output data.
By changing the entrained data label content of modules output data, can control flexibly the direction of the output data of inner each module of FPGA, realize flexibly connecting of FPGA internal module; Such as, it is 3 bits that label (F) length is set, the first bit respective modules 1, the second bit respective modules 2, the three bit respective modules 3, and corresponding bit position these module normal process data of bit representation, zero clearing represents this module transparent data.Suppose that the F1 content is ' 111 ', representation module 1, module 2, module 3 be the normal process data successively; Suppose that the F2 content is ' 010 ', representation module 1, module 3 transparent data, module 2 normal process data; Suppose that the F3 content is ' 011 ', representation module 1 transparent data, module 2, module 3 normal process data; So by data label (F) content is set, can complete intermodule and flexibly connect.
Preferably, described method can also comprise: in the time need to testing the output data of each module, generate the label substance of these module output data of transparent transmission, and control this module and add the content of described label in the output after processing, so that the output data of this module to the FPGA test interface, are convenient to test.
That is to say, in the time need to testing certain module of FPGA inside, its corresponding data label only need be set, and (this belongs to the test data generation, can be rewritten or be write by the staff wage reform by the outer computer software control according to tag format, is perhaps completed by internal control module.) make these module output data directly deliver to the FPGA test interface, thereby additionally do not taking under the prerequisite of FPGA internal resource, realize conveniently test.As shown in Figure 2, suppose that the F2 content is ' 010 ', representation module 1, module 3 transparent data, module 2 normal process data can realize that data directly are pass-through to module 2, then directly transparent transmission output, direct test module 2 so easily.
Also see also Fig. 3, the process flow diagram of a kind of flexible label method of attachment that provides for the embodiment of the present invention is applied to the inner connection that is used between modules that data process of field programmable logic device FPGA, and described method comprises:
Step 301: receive the data that are input to FPGA inside, described data are the data of encapsulation of data label;
Step 302: described data are carried out decapsulation, and the data after decapsulation are carried out respective handling;
Step 303: receive change described module output stream to label substance;
Step 304: add described label substance to described processing and export afterwards in the data label of data;
Step 305: the output data according to the interface mode of the flexible label of setting after to described interpolation label substance encapsulate, and the data after encapsulate output to the module of described label substance sensing.
Wherein, the interface mode of described flexible label according to setting is: export outside data layout to according to FPGA and set the interface mode that the flexible label between the inner modules of FPGA connects.
Preferably, described method can also comprise: the data way of output of controlling between described modules is the way of output of first in first out.
The embodiment of the present invention provides a kind of method and flexible label method of attachment of controlling data penetration transmission, can realize the transparent transmission of the output data of field programmable logic device FPGA internal module, and each state of modules output data is tested.The method is not additionally taking chip internal resource and internal storage, does not change under the original sequential prerequisite of internal signal, can carry out transparent transmission, test to each functional module of FPGA inside.That is to say, the embodiment of the present invention is by the intermodular data Signal Transparent Transmission Technology, completes flexibly connecting of module, and the combination tag technology, reaches flexible, the efficient test to the FPGA inner function module.
Implementation procedure based on said method, a kind of device of controlling data penetration transmission that the embodiment of the present invention provides, its structural representation sees Fig. 4 for details, this installs and is used for controlling the inner transparent transmission that is used for the modules output data of data processing of field programmable logic device FPGA, comprise: setting unit 41, data label generation unit 42, encapsulation unit 43 and control module 44, wherein
Described setting unit 41, the interface mode that is used for arranging between described modules is the interface mode that flexible label connects; After the interface mode between modules arranges, follow-up direct use.Described data label generation unit 42 is used to modules to generate corresponding data label; Described encapsulation unit 43, the data and the described data label that are used for being input to FPGA inside are packaged together; Described control module 44, the content of carrying described data label when being used for by change modules output data is controlled the direction that described modules is exported data, completes the transparent transmission of intermodule output data.
Preferably, described device can also comprise: the label substance generation unit is used for generating the label substance of these module output data of transparent transmission in the time need to testing the output data of a module of described modules; Described control module also is used for controlling this module and adds the content of described label in the output after processing, so that the output data of this module to the FPGA test interface, are convenient to test.
Also see also Fig. 5, the structural representation of a kind of flexible label coupling arrangement that provides for the embodiment of the present invention, the connection of described application of installation between the inner modules of processing for data of field programmable logic device FPGA comprises: the first receiving element 51, decapsulation unit 52, processing unit 53, the second receiving element 54, adding device 55, encapsulation unit 56 and transmitting element 57, wherein
Described the first receiving element 51 is used for receiving the data that are input to FPGA inside, and described data are the data of encapsulation of data label; Described decapsulation unit 52 is used for described data are carried out decapsulation; Described processing unit 53 is used for the data after described decapsulation unit decapsulation are carried out respective handling; Described the second receiving element 54, be used for receiving change described module output stream to label substance; Described adding device 55 is used for adding described label substance to data label that data are exported in described processing afterwards; Described encapsulation unit 56 is used for interface mode according to the flexible label of the setting output data after to described interpolation label substance and encapsulates; Described transmitting element 57 is used for the data after described encapsulation unit encapsulation are outputed to the module that described label substance points to.
Preferably, described device can also comprise: the first in first out module, be used for the connection between described modules, and the data of processing according to the order buffer memory modules of first in first out.
in the embodiment of the present invention, first export according to FPGA the interface mode that outside data layout determines that the flexible label between inner each submodule of FPGA connects to, then to sending into the data of FPGA inside, encapsulate according to described interface mode, after data enter into the module of FPGA inside, according to each module, deblocking is carried out in the requirement of data, after the internal module processing finishes, control module generates the content of corresponding data label, and control the content that corresponding module is added this data label, according to described interface mode, the data of adding the data label content are encapsulated again, deliver to corresponding module according to the difference of label substance, complete different functions.
Further, when the state of each module of FPGA inside is tested, according to testing requirement, by the data label (can realize by software or hardware etc.) that each module is set, export the test interface of FPGA with the data of controlling the module that needs test to, test.
For the ease of those skilled in the art's understanding, the below illustrates with the FPGA design example in conjunction with voice (being the speaker) recognizer.
In Speaker Identification algorithm calculating process, after speech data frame entered FPGA inside, through Output rusults after five resume module such as pre-service, power spectrum computation, mel wave filter, logarithm operation and discrete cosine transform, its functional block diagram was seen accompanying drawing 6.
The form of discrete cosine transform Output rusults is 1*32Bit speech channel label+12*32Bit MFCC supplemental characteristic, and the standard interface between inner each functional module of FPGA transmits with the form of 32 buses.For data cached when the inside modules deal with data, can add corresponding FIFO between each functional module.FPGA inner structure after interpolation FIFO is seen accompanying drawing 7.
To sending into the voice data of Speaker Identification FPGA inside, at first the speech channel that distributes according to this road speech number, and the sequence number of the frame that marks off produce the data label of 32 bits by control module for it, also can generate other data label, the present embodiment is take 32 as example.The structure of its data label is as shown in table 1.
Table 1
Wherein, the coded format of this data label is as follows:
Bit31:En_Flag (frame effectively identifies)-' 1 ' valid frame; ' 0 ' invalid frame;
Bit30-24: transparent transmission is processed sign
0000001 carries out pretreatment module, other modules of transparent transmission;
0000010 carries out power spectrum module, other modules of transparent transmission;
0000100 carries out mel bank of filters, other modules of transparent transmission;
0001000 carries out logarithm operation unit, other modules of transparent transmission;
0010000 carries out discrete cosine transform unit, other modules of transparent transmission;
0011111 carries out whole modules.
Bit23-20: keep 2 fields, be defaulted as complete zero;
Bit19-0:Channel_Flag (speech channel field)-can identify the 1M speech channel;
When each resume module, can judge whether current data wants transparent transmission according to data label.For example, want the result of measured power spectrum module whether correct, can Bit30-24 in its data label be rewritten as ' 0000011 ' by control module, the input data will by with the processing of processing module and power spectrum module after, Output rusults will be sent by exporting FIFO.This moment, the built-in function of FPGA changed to shown in accompanying drawing 8, and wherein each functional module in the slash square frame all is in the transparent transmission state.
Equally, based on label and flexibly connect technology, also can be by the data penetration transmission between label practical function module be set.Do not need in current application to suppose mel bank of filters module, the label when only needing power spectrum is exported is made as ' 0011011 ', and the Output rusults of power spectrum will directly enter the logarithm operation unit.At this moment, the inner function module of Speaker Identification FPGA connects as accompanying drawing 9.
By above-described embodiment as can be known, the purpose of the embodiment of the present invention is to provide a kind of method, flexible label method of attachment and device thereof of controlling data penetration transmission, realization is tested the state of each functional module of FPGA content, this technical scheme in the situation that flexibly connect technology and data tag technology combines, is completed the intermodular data transparent transmission and to the test of any functional module of FPGA inside with module.Realized additionally not taking chip internal resource and internal storage, do not changed under the original sequential prerequisite of internal signal, reached flexible, the efficient test to the FPGA inner function module.
Need to prove, one of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, to come the relevant hardware of instruction to complete by computer program, described program can be stored in a computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random store-memory body (Random AccessMemory, RAM) etc.
Above manner of execution and device to a kind of response message provided by the present invention is described in detail, used specific embodiment herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (11)
1. method of controlling data penetration transmission, be used for controlling the inner transparent transmission that is used for the modules output data of data processing of field programmable logic device FPGA, it is characterized in that, the interface mode that arranges between described modules is the interface mode that flexible label connects; The described interface mode that arranges between described modules is that the interface mode that flexible label connects specifically comprises: for the input interface of each module arranges tag decoder, output interface arranges code tag, and according to the formatted output data of the flexible label of setting;
Described method:
For modules generates corresponding data label;
The data and the described data label that are input to FPGA inside are packaged together;
By changing the content of carrying described data label when modules is exported data, control the direction of described modules output data, complete the transparent transmission of intermodule output data; Described transparent transmission is in the module of described output data transmission process, and the module that the content of described data label is pointed to is processed described output data, and the module that the content of described data label is not pointed to is not processed described output data.
2. method according to claim 1, is characterized in that, described data label for modules generation correspondence comprises:
Control module in described programmable logic device (PLD) FPGA is that modules generates corresponding data label; Perhaps
The outer computing machine of described programmable logic device (PLD) FPGA is that modules generates corresponding data label.
3. method according to claim 1, is characterized in that, described data label comprises: frame effectively identifies, transparent transmission is processed sign and session field number.
4. method according to claim 1, is characterized in that, described method also comprises:
In the time need to testing the output data of the module in described FPGA, generate the label substance of these module output data of transparent transmission, and control this module and add the content of described label in the output after processing, so that the output data of this module to the FPGA test interface, are convenient to test.
5. flexible label method of attachment is applied to the inner connection that is used between modules that data process of field programmable logic device FPGA, it is characterized in that, comprising:
Reception is input to the data of FPGA inside, and described data are the data of encapsulation of data label;
Described data are carried out decapsulation, and the data after decapsulation are carried out respective handling;
Receive change described module output stream to label substance;
Adding described label substance to described processing exports in the data label of data afterwards;
Output data according to the form of the flexible label of setting after to described interpolation label substance encapsulate, and the data after encapsulate output to the module of described label substance sensing.
6. method according to claim 5, is characterized in that, the form of described flexible label according to setting is:
Export according to FPGA the form that outside data layout is set the flexible label between the inner modules of FPGA to.
7. according to claim 5 or 6 described methods, is characterized in that, described method also comprises: the data way of output of controlling between described modules is the way of output of first in first out.
8. a device of controlling data penetration transmission, be used for controlling the inner transparent transmission that is used for the modules output data of data processing of field programmable logic device FPGA, it is characterized in that, comprises
Setting unit, the interface mode that is used for arranging between described modules is the interface mode that flexible label connects, specifically be used to the input interface of each module that tag decoder is set, output interface arranges code tag, and according to the formatted output data of the flexible label of setting;
The data label generation unit is used to modules to generate corresponding data label;
Encapsulation unit, the data and the described data label that are used for being input to FPGA inside are packaged together;
Control module, the content of carrying described data label when being used for by change modules output data is controlled the direction that described modules is exported data, completes the transparent transmission of intermodule output data; Described transparent transmission is in the module of described output data transmission process, and the module that the content of described data label is pointed to is processed described output data, and the module that the content of described data label is not pointed to is not processed described output data.
9. device according to claim 8, is characterized in that, also comprises:
The label substance generation unit is used for generating the label substance of these module output data of transparent transmission in the time need to testing the output data of a module of described modules;
Described control module also is used for controlling this module and adds the content of described label in the output after processing, so that the output data of this module to the FPGA test interface, are convenient to test.
10. flexible label coupling arrangement is applied to the inner connection that is used between modules that data process of field programmable logic device FPGA, it is characterized in that, comprising:
The first receiving element is used for receiving the data that are input to FPGA inside, and described data are the data of encapsulation of data label;
Decapsulation unit is used for described data are carried out decapsulation;
Processing unit is used for the data after described decapsulation unit decapsulation are carried out respective handling;
The second receiving element, be used for receiving change described module output stream to label substance;
Adding device is used for adding described label substance to data label that data are exported in described processing afterwards;
Encapsulation unit is used for form according to the flexible label of the setting output data after to described interpolation label substance and encapsulates;
Transmitting element is used for the data after described encapsulation unit encapsulation are outputed to the module that described label substance points to.
11. device according to claim 10 is characterized in that, also comprises:
The first in first out module is used for the connection between described modules, and the data of processing according to the order buffer memory modules of first in first out.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101153892A (en) * | 2007-10-12 | 2008-04-02 | 成都华微电子系统有限公司 | Verification method for field programmable gate array input/output module |
| US7446679B1 (en) * | 2007-07-17 | 2008-11-04 | Lattice Semiconductor Corporation | Compression and decompression of configuration data for programmable logic devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7446679B1 (en) * | 2007-07-17 | 2008-11-04 | Lattice Semiconductor Corporation | Compression and decompression of configuration data for programmable logic devices |
| CN101153892A (en) * | 2007-10-12 | 2008-04-02 | 成都华微电子系统有限公司 | Verification method for field programmable gate array input/output module |
Non-Patent Citations (4)
| Title |
|---|
| FPGA片上调试方法;刘华珠;《东莞理工学院学报》;20050630;第12卷(第3期);34-38 * |
| 以太网透传技术及应用研究;李馥娟;《微计算机应用》;20090731;第30卷(第7期);8-13 * |
| 刘华珠.FPGA片上调试方法.《东莞理工学院学报》.2005,第12卷(第3期),34-38. |
| 李馥娟.以太网透传技术及应用研究.《微计算机应用》.2009,第30卷(第7期), |
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