CN112035391B

CN112035391B - Interface device and method for serial communication and electronic equipment

Info

Publication number: CN112035391B
Application number: CN202011206356.2A
Authority: CN
Inventors: 赵贵权
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2020-11-03
Filing date: 2020-11-03
Publication date: 2021-01-19
Anticipated expiration: 2040-11-03
Also published as: CN112035391A

Abstract

The disclosure provides an interface device, a method and an electronic device for serial communication. The interface device includes: a transmitting unit configured to transmit communication data to an opposite interface device corresponding to the interface device, wherein the opposite interface device includes a storage unit configured to store the communication data; and a receiving unit electrically coupled with the transmitting unit, for receiving input information from the counter interface device, wherein the input information includes storage state information of a storage unit of the counter interface device, wherein the transmitting unit is configured to: an expected data amount of the communication data transmitted to the counter interface device is determined based on the data amount of the communication data transmitted and the storage state information of the storage unit of the counter interface device.

Description

Interface device and method for serial communication and electronic equipment

Technical Field

The present disclosure relates to the field of circuit technologies, and in particular, to an interface device, a method, and an electronic device for serial communication.

Background

In high-speed serial communication, it is generally necessary for the receiving end to report the status of the receiving end to the transmitting end. For example, the storage space of the memory of the receiving end is about to be exhausted, and the receiving end needs to inform the sending end in time. If the state of the receiving end cannot be timely transmitted to the transmitting end, the data in the process cannot be cached due to the excessively high transmission rate, and packet loss may be caused.

Disclosure of Invention

In view of the above, the present disclosure provides an interface apparatus, a method, and an electronic device for serial communication.

In a first aspect of the disclosure, a first interface device for serial communication is provided. The first interface device includes: a transmitting unit configured to transmit communication data to an opposite interface device corresponding to the interface device, wherein the opposite interface device includes a storage unit configured to store the communication data; and a receiving unit electrically coupled to the transmitting unit, for receiving input information from the counter interface device, wherein the input information includes storage state information of a storage unit of the counter interface device, wherein the transmitting unit includes: a first counting unit configured to generate a first count value indicating an accumulated transmission data amount of the first interface apparatus, in accordance with a data amount of communication data transmitted to the counter interface apparatus by the transmission unit; and a second counting unit configured to generate a second count value indicating an amount of data that has been read from the storage unit of the counter interface device, according to the received storage state information, wherein the transmitting unit is further configured to: calculating an available storage space of a storage unit of the opposite interface device based on a difference value of the first count value and the second count value; and determining an expected amount of data for communication data to be sent to the subtended interface device based on the available memory space.

In a second aspect of the disclosure, a method for serial communication is provided. The method comprises the following steps: determining the data volume of communication data which is transmitted by a first interface device to a corresponding opposite interface device, wherein the opposite interface device comprises a storage unit for storing the communication data; receiving input information from the opposite interface device, wherein the input information comprises storage state information of a storage unit of the opposite interface device; generating a first count value indicating the accumulated transmission data amount of the first interface device according to the data amount of the communication data transmitted by the first interface device to the corresponding opposite interface device; generating a second count value indicating an amount of data that a storage unit of the counter interface device has been read, according to the received storage state information; calculating an available storage space of a storage unit of the opposite interface device based on a difference value of the first count value and the second count value; and determining an expected amount of data for communication data to be sent to the subtended interface device based on the available storage space.

In a third aspect of the present disclosure, an electronic device is provided, which includes the first interface apparatus described in the first aspect.

The first interface device, the method and the electronic equipment for serial communication provided by the disclosure determine the expected data volume of communication data transmitted to a counter interface device corresponding to the first interface device according to the data volume of the transmitted communication data and the storage state information of a storage unit of the counter interface device by recording the data volume of the communication data and the storage state information of the storage unit of the counter interface device. The predicted data volume can be calculated by recording the data volume of the transmitted communication data and the received storage state information of the storage unit of the opposite interface device, and since the data volume of the transmitted communication data comprises the data volume of the in-transit data and the received storage state information of the storage unit of the opposite interface device reflects the storage state information before an in-transit process (i.e. transmission delay), the data overflow of the storage unit of the opposite interface device cannot be caused by the determined predicted data volume according to the data volume of the transmitted communication data and the received storage state information of the storage unit of the opposite interface device, and the occurrence of a packet loss situation is avoided. Further, the first interface device is provided with a counter, and calculates the remaining capacity of the storage unit of the opposite interface device based on the count of the counter, so that the on-the-way instruction information sent by the opposite interface device is not completely relied on. Therefore, the minimum capacity of the storage unit can be designed to be the maximum in-transit data amount, and data overflow is not caused, so that the consumption of the storage space is reduced.

Drawings

In order to more clearly illustrate the present disclosure or the technical solutions in the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

FIG. 1 shows a schematic structural diagram of an exemplary simulation system according to an embodiment of the present disclosure.

Fig. 2A illustrates a circuit configuration schematic of an exemplary interface device according to an embodiment of the present disclosure.

Fig. 2B illustrates a circuit configuration schematic of an exemplary transmitter according to an embodiment of the present disclosure.

Fig. 3 shows a schematic diagram of data volume recording of a transmitter according to an embodiment of the present disclosure.

Fig. 4 illustrates a flow diagram of an exemplary method for serial communication in accordance with an embodiment of the present disclosure.

Fig. 5 shows a hardware structure diagram of an exemplary electronic device of an embodiment of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

In high-speed serial communication, in order to solve the problem of packet loss caused by a fast transmission rate, it is a common practice to provide a memory with a larger capacity. It is assumed that 1 unit of data can be transmitted in a serial communication within one clock cycle, and 4 clock cycles are required for data to be transmitted from a transmitting end to a receiving end, that is, the transmission delay of data is 4 clock cycles. Therefore, when the storage space of the receiver memory is nearly exhausted, in order to avoid the packet loss of the in-transit data, the receiver memory must issue a corresponding instruction to the sender so that the sender can determine the expected sending data amount. However, this communication method relying on the feedback of the remaining capacity from the receiving side has a drawback that a space needs to be reserved for the data in transit due to the transmission delay of the data.

For example, when the storage space of the memory of the receiving end is nearly exhausted, the receiving end sends an indication to the transmitting end that the storable space of the memory of the receiving end is only 4 units of data left, and the indication will be 4 clock cycles in transit (the transmission delay of the indication from the transmitting end to the receiving end), so at this time, the memory of the receiving end needs to reserve a space of 4 units of data to store new data received in transit of the indication from the transmitting end. Therefore, in the process of indicating, the maximum data in transit is 4 units, and the indication is that the storable space is left with only 4 units of data, so that in order to avoid packet loss, the minimum capacity of the memory of the receiving end should be 2 × 4 units of data.

At this time, it is generally necessary to provide at least one memory with a capacity of 8 units of data, and when the usage rate of the memory reaches a predetermined ratio (for example, when 4 units of memory remain), a message that the memory is about to be exhausted is sent from the receiving end to the transmitting end, so that the transmitting end stops data transmission. It follows that the capacity of the memory is related to the transmission delay and the size of the unit data.

Since the high-speed data transmission rate is very fast, the size of the data transmitted in a unit time is very large, and the memory must have enough capacity to ensure that the data packets in transit can still be cached by the memory, which results in a large amount of memory resources occupied by the memory.

Furthermore, for Time Division Multiplexing (TDM) high speed transmission, the clock frequency is high, resulting in multiple clock cycles being included in the Time-in-transit of the transmitted data. This prevents the handshake signals from returning in one clock cycle. Therefore, the transmitting end may not obtain the remaining capacity information of the receiving end in time, which is likely to cause packet loss and repeated transmission, thereby reducing the efficiency of high-speed transmission. In view of this, how to timely deliver the remaining capacity information of the receiving party in the TDM high-speed transmission process is a problem to be solved.

In some scenarios, an Emulator (Emulator) may prototype and debug a logic system design that includes one or more modules. The logic System design may be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a Specific Application. The logic System design may be designed from a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). The logic system Design being tested in the simulator may also be referred to as a Design Under Test (DUT). The simulator may simulate the DUT via one or more configurable components, such as a Field Programmable Gate Array (FPGA), including performing various operations of the DUT to test and verify the functionality of various modules of the DUT prior to manufacturing.

In prototyping logic system designs using FPGAs, control of high-speed serial communications is typically accomplished by the FPGA. The storage resource of the FPGA is very precious, so how to reduce the consumption of the storage space of the FPGA while ensuring the high-speed serial communication performance is an urgent problem to be solved.

The interface device, the method and the electronic equipment for serial communication provided by the disclosure determine the expected data volume of the communication data transmitted to the opposite interface device according to the data volume of the transmitted communication data and the storage state information of the storage unit of the opposite interface device by recording the data volume of the communication data transmitted to the opposite interface device corresponding to the interface device and the storage state information of the storage unit of the opposite interface device. The predicted data volume can be calculated by recording the data volume of the transmitted communication data and the received storage state information of the storage unit of the opposite interface device, and since the data volume of the transmitted communication data comprises the data volume of the in-transit data and the received storage state information of the storage unit of the opposite interface device reflects the storage state information before an in-transit process (i.e. transmission delay), the data overflow of the storage unit of the opposite interface device cannot be caused by the determined predicted data volume according to the data volume of the transmitted communication data and the received storage state information of the storage unit of the opposite interface device, and the occurrence of a packet loss situation is avoided. Further, the interface device is provided with a counter, and calculates the remaining capacity of the storage unit of the counter interface device based on the count of the counter, so that the on-the-way instruction information sent by the counter interface device is not completely relied on. Therefore, the minimum capacity of the storage unit can be designed to be the maximum in-transit data amount, and data overflow is not caused, so that the consumption of the storage space is reduced.

FIG. 1 shows a schematic diagram of a simulation system 100 according to an embodiment of the present disclosure.

As shown in FIG. 1, the emulation system 100 can include an emulator 102 and a daughter board 104.

Simulator 102 is a hardware system that simulates a Design Under Test (DUT). A DUT may include one or more modules. The DUT may be combinational logic circuitry, sequential logic circuitry, or a combination of both. Simulator 102 may include one or more configurable circuits (e.g., FPGAs) for simulating a DUT.

The emulation system 100 can include an interface system 1022, consisting of an interface device 1022a and an interface device 1022b, for communicatively coupling the emulator 102 and the daughter board 104. The daughter board 104 is generally used to provide extensibility to the emulator 102 and further connects to external devices (e.g., a host). The emulator 102 and the daughter board 104 may communicate serially through an interface system 1022, and in some embodiments, the emulator 102 and the daughter board 104 may communicate serially at high speed through the interface system 1022. In some embodiments, the serial communication may be in a time division multiplexed manner.

In some embodiments, the interface system 1022 may include one or more interface devices (e.g., interface device 1022a or interface device 1022 b) having electrical connection capabilities. For example, interface device 1022a or interface device 1022b may be a high-speed serial communication interface that employs TDM.

Fig. 2A illustrates a circuit configuration schematic of an exemplary interface device 200 according to an embodiment of the present disclosure. The serial communication interface 200 may include an interface device 220 and an interface device 240 corresponding to the interface device 220. Data may be transferred between the interface device 220 and the interface device 240 to enable communication between, for example, the emulator 102 and the daughter board 104 of FIG. 1.

Interface device 220 may further include a transmitter 2202, a receiver 2204, a memory 2206, a data flow controller 2208, and a selector 2210. In some embodiments, the interface device 220 may be implemented by an FPGA or by a central processor (e.g., by configurable circuitry in the emulator 102 of fig. 1). For example, the functions of the interface device 220 may be implemented by writing the portions implementing the interface device 220 in a logic system design and writing to an FPGA for execution.

The memory 2206 may be implemented using memory onboard the FPGA. In some embodiments, memory 2206 includes permanent and non-permanent, removable and non-removable media and may be implemented in any method or technology for storage of information. The memory 2206 may be used to store data that may be accessed by the computing device, where the stored data may be computer-readable instructions, data structures, modules of a program, or other data. Examples of memory 2206 include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), flash memory, or other memory technologies.

Similarly, the interface device 240 may further include a transmitter 2402, a receiver 2404, a memory 2406, a data flow controller 2408, and a selector 2410. In some embodiments, the interface device 240 may be implemented by an FPGA, a central processing unit, or a dedicated control circuit (e.g., by a configurable circuit or CPU in the sub-board 104 of fig. 1, or by a host electrically coupled to the sub-board 104). When the interface device 240 is implemented by using an FPGA, for example, the function of the interface device 240 may be implemented by writing a part for implementing the interface device 240 in a logic system design and writing the part into the FPGA for execution. When the interface device 240 is implemented by a central processing unit, for example, the function of the interface device 240 may be implemented by a dedicated control circuit (e.g., a dedicated chip).

Serial communication interface 200 may also include interfaces 2212a and 2412a for transmitting data and interfaces 2212b and 2412b for receiving data.

Interfaces

2212a, 2412a, 2212b, or 2412b may each include one or more pins. In some embodiments,

interface

2212a, 2412a, 2212b, or 2412b may be a fiber optic interface. A set of inter-coupled interfaces (e.g., interfaces 2212a and 2412b, or interfaces 2212b and 2412 a) may employ a wired (e.g., employing a cable or fiber optic connection) or wireless connection therebetween. Therefore, the electrical coupling referred to in the present disclosure includes a method of coupling by converting an optical signal, a wireless signal, or the like to finally generate an electrical signal.

In some embodiments, interface device 220 and interface device 240 have substantially the same structure and function and may implement high-speed serial communication for TDM when interfacing with each other.

As shown in fig. 2A, transmitter 2202 can be electrically coupled to receiver 2204 and selector 2210, and configured to transmit communication data 2216 that needs to be transmitted to subtended interface device 240 via selector 2210 and interfaces 2212A, 2412 b.

In some embodiments, the transmitter 2202 may include 2 counters. Fig. 2B is a circuit configuration schematic of a transmitter 2202 according to an embodiment of the disclosure. In some embodiments, the counter may be implemented with an adder and a register. For example, as shown in fig. 2B, the transmitter 2202 may include a first counter 22022 and a second counter 22024. The first counter 22022 may be configured as a first counter 22022 for recording the amount of data of the transmitted communication data 2216 (e.g., the cumulative amount of transmitted data 22026), while the second counter 22024 may be configured as a second counter 22024 for recording the amount of data 22028 taken from the memory 2406. The transmitter 2202 may also be configured to calculate the amount of data net received to the interface device 240 based on the difference in the count values of the first and second counters 22022, 22024, which may in turn determine the expected amount of data for the communication data 2216. Specific methods are described in more detail below.

As shown in fig. 2A, receiver 2204 may be electrically coupled to transmitter 2202 and memory 2206, respectively, and configured to receive data 2414 from subtending interface device 240 via interface 2212 b. The data 2414 may include communication data 2416 sent to the transmitter 2402 of the opposing interface device 240 or stored state information 2420 of the memory 2406 sent by the data flow controller 2408. In some embodiments, the data 2414 may comprise a plurality of cells, each cell comprising a header and a payload, wherein the header is to indicate the payload as either stored state information 2420 of the memory 2406 of the subtended interface apparatus 240 or communication data 2416 transmitted by the transmitter 2402 of the subtended interface apparatus 240.

Based on the information indicated by the header, the receiver 2204 may distribute the received data 2414 to the transmitter 2202 or to the memory 2206. For example, when the header indicates that the payload of the data 2414 is storage status information 2420 for the memory 2406 of the interface device 240, the receiver 2204 transmits the data 2414 (i.e., the storage status information 2420) to the transmitter 2202. This data 2414 may be parsed by the transmitter 2202 and used to update the count value of the second counter 22024. For another example, when the header indicates that the payload of the data 2414 is communication data 2416 transmitted by the transmitter 2402 of the opposing interface device 240, the receiver 2204 transmits the data 2414 (i.e., the communication data 2416) to the memory 2206.

The memory 2206 is used to cache communication data (e.g., communication data 2416) from the subtended interface device 240. The memory 2206 may also be connected to an external device (not shown) that may read data cached in the memory 2206. The external device may be, for example, an emulator 102, a daughter board 104, or other electronic device. The size of the memory 2206 may be provided according to the actual needs of the design. In one example, the memory 2206 may store 16MB (megabyte) of data.

Data flow controller 2208 may be electrically coupled to memory 2206 and selector 2210, and may be configured to monitor a storage state 2218 of memory 2206. Data flow controller 2208 may be implemented by an FPGA, a dedicated control circuit, or a central processor (e.g., by configurable circuitry in simulator 102 of fig. 1). For example, the functionality of data flow controller 2208 may be implemented by writing the portions implementing data flow controller 2208 in a logic system design and writing to an FPGA for execution.

In some embodiments, data stream controller 2208 is configured to generate and transmit storage state information 2220 for memory 2206 in response to a change in storage state 2218 of memory 2206. More specifically, when data of the memory 2206 is taken by an external device, thereby freeing up storage space, the data flow controller 2208 may generate and transmit a data amount of the taken data (e.g., the taken data 2222 of fig. 2A) in response to the data of the memory 2206 being taken. The storage status information 2220 indicating the amount of data taken may be further sent to the subtended interface device 240 for recording and counting thereof.

Selector 2210 may include a first input port electrically coupled to transmitter 2202, a second input port electrically coupled to data flow controller 2208, and an output port (e.g., interface 2212 a) communicatively coupled to opposing interface device 240. Since the transmitter 2202 and the data stream controller 2208 share the interface 2212a, a selector 2210 is provided. The selector 2210 may be configured to select an output between the output signal of the transmitter 2202 and the output signal of the data stream controller 2208 to be output to the interface 2212a, the selected output signal being received as data 2214 by the receiver 2404. Wherein, when the selector 2210 receives the output signal of the transmitter 2202 and the output signal of the data stream controller 2208 at the same time, the selector 2210 may be configured to transmit the output signal of the data stream controller 2208 (i.e., the size of the fetched data with respect to the memory 2206) to the interface 2212a and further to the receiver 2404. In some embodiments, selector 2210, for example, may be a data selector (MUX).

It is to be understood that the transmitter 2402, the receiver 2404, the memory 2406, the data stream controller 2408 and the selector 2410 of the interface device 240 may have functions and structures corresponding to those of the transmitter 2202, the receiver 2204, the memory 2206, the data stream controller 2208 and the selector 2210 described above, and a detailed description thereof is omitted here for the sake of brevity.

FIG. 3 shows a schematic diagram of a data volume record 300 of a transmitter 2202 in accordance with an embodiment of the disclosure.

In some embodiments, as shown in fig. 3, during the initialization phase 300a of the data transfer, the memory 2406 is initialized and an indication is sent to the transmitter 2202 such that the second count value 304 of the second counter 22024 of the transmitter 2202 is 16MB (assuming the memory 2406 can store 16MB of data). Meanwhile, the first count value 302 of the first counter 22022 is initialized to 0, indicating that the transmitter 2202 does not transmit data. At this time, the maximum receivable data amount 306 of the opposite interface device 240 known to the interface device 220 is 16MB, that is, the transmitter 2202 can transmit 16MB at most.

In data transfer phase 300b, for example, transmitter 2202 of interface device 220 transmits the 4MB of communication data to receiver 2404 of subtending interface device 240. At this time, the first counter 22022 of the transmitter 2202 updates the first count value 302 of its first counter 22022 to 4MB in response to the transmitter 2202 transmitting 4MB of communication data. The transmitter 2202 calculates the amount of data that can be currently transmitted based on the difference between the count values of the second counter 22024 and the first counter 22022. In this example, at this time, the maximum amount of receivable data 306 for interface device 240 that interface device 220 knows is 16MB-4MB =12 MB.

When the receiver 2404 of the counter interface device 240 receives the 4MB communication data transmitted by the transmitter 2202, the communication data is buffered in the memory 2406. At this time, the memory 2406 stores 4MB of data.

In the data read phase 300c, the data of the memory 2406 may be further read. When the data in the memory 2406 is read, the storage status of the memory 2406 is updated, and the data flow controller 2408 sends information (e.g., the storage status information 2420 in fig. 2A) related to the storage space of the memory 2406 to the transmitter 2202 according to the updated storage status (e.g., the storage status 2418 in fig. 2A) of the memory 2406. For example, referring to FIG. 2A, when the memory 2406 is taken 2MB of data (e.g., taken data 2422), the memory 2406 updates its memory status 2418, and the data flow controller 2408 sends memory status information 2420 to the transmitter 2202 indicating that 2MB of data is taken from the memory 2406 based on the updated memory status 2418 of the memory 2406. This information is received by the transmitter 2202 via the interface 2412a, the interface 2212b, and the receiver 2204 and causes the second count value 304 of the second counter 22024 of the transmitter 2202 to be updated to 16MB +2MB =18 MB. In this way, the transmitter 2202 can calculate the maximum amount of data that can be currently transmitted, i.e., the maximum receivable data amount 306 of the opposite interface device 240 known to the interface device 220 is 18MB to 4MB =14MB, from the difference between the count values of the second counter 22024 and the first counter 22022.

It can be seen that the transmitter 2202 considers the memory 2406 to have only 12MB of remaining space until it receives information indicating that 2MB of data in the memory 2406 has been taken away. Therefore, although the memory 2406 of the counter interface device 240 has a memory space of 14MB at this time, the transmitter 2202 of the interface device 220 can transmit only 12MB of data at most (the maximum amount of data that can be currently transmitted, which is calculated from the count difference of its counter). Therefore, even if the interface device 220 transmits data in accordance with the maximum capacity (12 MB in this example) that it can transmit by itself, no overflow phenomenon occurs at the opposite interface device 240.

In some embodiments, the first and second counters 22022, 22024 are configured to count accumulatively to record the amount of data sent and the amount of data taken to the memory of the interface device. Based on the above example, when the transmitter 2202 of the interface device 220, for example, further transmits 8MB of data to the receiver 2404 of the opposing interface device 240 (stage 300 d), the transmitter 2202, in response to the data transmission, updates the first counter value 302 of the first counter 22022 to 4MB +8MB =12 MB. Meanwhile, the transmitter 2202 may also calculate the maximum capacity that can be currently transmitted, that is, the maximum receivable data amount 306 of the opposite interface device 240 known to the interface device 220 is 18MB-12MB =6MB, according to the latest first count value 302 and the second count value (currently 18 MB) of the second counter 304.

It can thus be seen that because the transmitter 2202 of interface device 220 is self-contained with a counter and calculates the remaining capacity of memory 2406 to interface device 240, it is no longer completely dependent on memory space indication information issued at memory 2406. Therefore, the minimum capacity of the memory 2406 of the counter interface device 240 can be designed to be the maximum amount of data in transit, thereby reducing the consumption of the memory space.

Referring to fig. 2A, the present disclosure provides an interface apparatus 220 for serial communication, including:

a transmitting unit (e.g., transmitter 2202 of fig. 2A) for transmitting communication data (e.g., communication data 2216 of fig. 2A) to a counter interface device (e.g., interface device 240 of fig. 2A) corresponding to the interface device 220, wherein the counter interface device (e.g., interface device 240 of fig. 2A) includes a storage unit (e.g., memory 2406 of fig. 2A) for storing the communication data; and

a receiving unit (e.g., receiver 2204 of FIG. 2A) electrically coupled to the transmitting unit, for receiving input information (e.g., data 2414 of FIG. 2A) from the counter interface device (e.g., interface device 240 of FIG. 2A), wherein the input information includes storage state information (e.g., storage state information 2420 of FIG. 2A) of a storage unit of the counter interface device;

wherein the transmitting unit is configured to:

an expected data amount of communication data (e.g., communication data 2216 of fig. 2A) transmitted to the counter interface device is determined from a data amount of the transmitted communication data (e.g., accumulated transmission data amount 22026 of fig. 2B) and storage state information of a storage unit of the counter interface device (e.g., storage state information 2420 of fig. 2A).

In some embodiments, the sending unit further comprises:

a first counting unit (e.g., a first counter 22022 of fig. 2B) configured to generate a first count value (e.g., a first count value 302 in fig. 3) indicating an accumulated transmission data amount (e.g., an accumulated transmission data amount 22026 of fig. 2B) of the interface apparatus, according to a data amount of communication data (e.g., communication data 2216 of fig. 2B) transmitted by the transmission unit to the counter interface apparatus;

a second counting unit (e.g., the second counter 22024 of fig. 2B) configured to generate a second count value (e.g., the second count value 304 of fig. 3) indicating an amount of data (e.g., the amount of data 22028 of fig. 2B taken from the memory) that has been read to the memory unit of the counter interface device according to the received storage status information (e.g., the storage status information 2420 of fig. 2A).

In some embodiments, in determining the expected amount of data for the communication data to transmit to the counter interface device, the transmitting unit is further configured to:

calculating an available storage space (e.g., a maximum receivable data amount 306 of fig. 3) of a storage unit of the subtended interface apparatus based on a difference between a first count value (e.g., a first count value 302 of fig. 3) and a second count value (e.g., a second count value 304 of fig. 3); and is

An expected amount of communication data (e.g., communication data 2216 of fig. 2B) to send to the subtended interface device is determined based on the available storage space.

In some embodiments, the expected amount of data of the communication data (e.g., communication data 2216 of fig. 2B) sent to the counter interface device (e.g., interface device 240 of fig. 2A) is less than or equal to the available storage space (e.g., maximum acceptable data amount 306 of fig. 3) of the counter interface device's storage unit (e.g., memory 2406 of fig. 2A).

In some embodiments, the input information (e.g., data 2414 of fig. 2A) further includes communication data (e.g., communication data 2416 of fig. 2A) transmitted by the subtended interface device, and the interface device 220 further includes:

a storage unit (e.g., the memory 2206 of fig. 2A) electrically coupled with the receiving unit (e.g., the receiver 2204 of fig. 2A), the storage unit configured to store communication data (e.g., the communication data 2416 of fig. 2A) transmitted by the subtended interface device.

In some embodiments, the input information (e.g., the data 2414 of fig. 2A) includes a plurality of cells including a header and a payload, wherein the header is used to indicate that the payload is storage status information of a memory location of the subtended interface apparatus (e.g., the storage status information 2420 of fig. 2A) or communication data transmitted by the subtended interface apparatus (e.g., the communication data 2416 of fig. 2A).

In some embodiments, the receiving unit is further configured to:

in response to the header indicating that the payload is storage status information (e.g., storage status information 2420 of fig. 2A) for a storage unit of the counter interface device, sending the payload to the sending unit; and

in response to the header indicating that the payload is communication data (e.g., communication data 2416 of fig. 2A) sent by the counter interface device, sending the payload to the storage unit.

In some embodiments, the interface device 220 further comprises: a data flow control unit (e.g., the data flow controller 2208 of fig. 2A) electrically coupled to the memory unit, the data flow control unit configured to monitor a memory state (e.g., the memory state 2218 of fig. 2A) of the memory unit (e.g., the memory 2206 of fig. 2A) of the interface device 220 and send memory state information (e.g., the memory state information 2220 of fig. 2A) corresponding to the memory state to the opposing interface device (e.g., the interface device 240 of fig. 2A) when the memory unit of the interface device 220 is read.

In some embodiments, the interface device 220 further includes: a data selection unit (e.g., selector 2210 of fig. 2A) comprising:

a first input port electrically coupled to the transmitting unit (e.g., transmitter 2202 of fig. 2A) for receiving communication data (e.g., communication data 2216 of fig. 2A) transmitted by the transmitting unit;

a second input port electrically coupled to the data flow control unit (e.g., data flow controller 2208 of FIG. 2A) for receiving memory state information (e.g., memory state information 2220 of FIG. 2A) transmitted by the data flow control unit; and

an output port (e.g., interface 2212A of fig. 2A) communicatively coupled with the counter interface device (e.g., interface device 240 of fig. 2A) for alternatively outputting the communication data or the storage status information, wherein,

when the data selection unit receives the communication data and the storage state information at the same time, the data selection unit preferentially transmits the storage state information.

In some embodiments, the serial communication between the interface device 220 and the subtended interface device 240 is performed in a time division multiplex manner.

For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the various modules may be implemented in the same one or more software and/or hardware implementations of the present disclosure.

Fig. 4 illustrates a flowchart of an example method 400 for serial communication, in accordance with an embodiment of the present disclosure. The method 400 may be implemented, for example, by the interface device 220 or the interface device 240 of fig. 2A. The method 400 may include the following steps.

At step 402, a data amount of communication data that a first interface device (e.g., interface device 220 of fig. 2A) has transmitted to its corresponding counter interface device (e.g., interface device 240 of fig. 2A) may be determined, where the counter interface device includes a storage unit (e.g., memory 2406 of fig. 2A) for storing the communication data.

At step 404, input information (e.g., data 2414 of FIG. 2A) from the subtended interface device may be received, wherein the input information includes storage state information (e.g., storage state information 2420 of FIG. 2A) of a storage unit of the subtended interface device.

In some embodiments, the input information further includes communication data (e.g., communication data 2416 of fig. 2A) sent by the counter interface device.

At step 406, an expected data amount of communication data (e.g., communication data 2216 of fig. 2A) transmitted to the counter interface device may be determined based on a data amount of the transmitted communication data (e.g., accumulated transmitted data amount 22026 of fig. 2B) and storage status information of the storage unit of the counter interface device (e.g., storage status information 2420 of fig. 2A).

In some embodiments, the method 400 further comprises:

generating a first count value (e.g., a first count value 302 in fig. 3) indicating an accumulated transmission data amount (e.g., an accumulated transmission data amount 22026 in fig. 2B) of the first interface device (e.g., the interface device 220 in fig. 2A) according to a data amount of communication data (e.g., the communication data 2216 in fig. 2B) that the first interface device has transmitted to a counterpart interface device (e.g., the interface device 240 in fig. 2A) corresponding thereto;

in accordance with the received storage status information (e.g., storage status information 2420 of FIG. 2A), a second count value (e.g., second count value 304 of FIG. 3) is generated that indicates an amount of data (e.g., amount of data taken 22028 from memory of FIG. 2B) that has been read by a storage unit (e.g., memory 2406 of FIG. 2A) of the counter interface device (e.g., interface device 240 of FIG. 2A).

In some embodiments, determining the expected amount of data for the communication data sent to the counter interface device further comprises:

In some embodiments, the expected amount of data of the communication data (e.g., communication data 2216 of fig. 2A) sent to the counter interface device (e.g., interface device 240 of fig. 2A) is less than or equal to the available storage space (e.g., maximum acceptable data amount 306 of fig. 3) of the counter interface device's storage unit (e.g., memory 2406 of fig. 2A).

The method of the foregoing embodiment is used to implement the corresponding apparatus in the foregoing embodiment, and has the beneficial effects of the corresponding apparatus embodiment, which are not described herein again.

Fig. 5 is a schematic diagram illustrating a more specific hardware structure of an electronic device 500 provided in this embodiment, where the electronic device 500 may include: a processor 502, a memory 504, an input/output interface 506, a communication interface 508, and a bus 510. Wherein the processor 502, memory 504, input/output interface 506, and communication interface 508 are communicatively coupled to each other within the device via bus 510.

The processor 502 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present disclosure.

The Memory 504 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, or the like. The memory 504 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present disclosure is implemented by software or firmware, the relevant program codes are stored in the memory 504 and called to be executed by the processor 502.

The input/output interface 506 is used for connecting an input/output module to realize information input and output. The input/output interface may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.

The communication interface 508 is used for connecting a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).

In some embodiments, the communication interface 508 may include an interface device (e.g., the interface device 220 or the interface device 240 of FIG. 2A) and may be utilized to enable serial communication.

Bus 510 includes a path that transfers information between the various components of the device, such as processor 502, memory 504, input/output interface 506, and communication interface 508.

It should be noted that although the above-described device only shows the processor 502, the memory 504, the input/output interface 506, the communication interface 508, and the bus 510, in a specific implementation, the device may also include other components necessary for normal operation. Moreover, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement the embodiments of the present disclosure, and need not include all of the components shown in the figures.

The foregoing description of specific embodiments of the present disclosure has been described. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A first interface device for serial communication, comprising:

a transmitting unit configured to transmit communication data to an opposite interface device corresponding to the first interface device, wherein the opposite interface device includes a storage unit configured to store the communication data; and

a receiving unit electrically coupled to the transmitting unit, for receiving input information from the counter interface device, wherein the input information includes storage state information of a storage unit of the counter interface device,

wherein the transmitting unit includes:

a first counting unit configured to generate a first count value indicating an accumulated transmission data amount of the first interface apparatus, in accordance with a data amount of communication data transmitted to the counter interface apparatus by the transmission unit; and

a second counting unit configured to generate a second count value indicating an amount of data that has been read to a storage unit of the counter interface device, in accordance with the received storage state information,

wherein the transmitting unit is further configured to:

calculating an available storage space of a storage unit of the opposite interface device based on a difference value of the first count value and the second count value; and is

An expected amount of data for communication data sent to the subtended interface device is determined based on the available storage space.

2. The first interface device of claim 1, wherein the expected data amount of communication data sent to the subtended interface device is less than or equal to an available storage space of a storage unit of the subtended interface device.

3. The first interface device of claim 1, wherein the input information further includes communication data transmitted by the subtended interface device, and the first interface device further comprises:

a storage unit electrically coupled with the receiving unit, the storage unit configured to store communication data transmitted by the counter interface device.

4. The first interface device of claim 3, wherein the input information comprises a plurality of cells including a header and a payload, wherein the header is used to indicate that the payload is storage status information of a storage unit of the subtended interface device or communication data transmitted by the subtended interface device.

5. The first interface apparatus of claim 4, wherein the receiving unit is further configured to:

in response to the header indicating that the payload is storage status information of a storage unit of the counter interface device, sending the payload to the sending unit; and

in response to the header indicating that the payload is communication data sent by the counter interface device, sending the payload to the storage unit.

6. The first interface device of claim 3, further comprising: a data flow control unit electrically coupled to the memory unit, the data flow control unit configured to monitor a memory state of the memory unit of the first interface device and to transmit memory state information corresponding to the memory state to the counter interface device when the memory unit of the first interface device is read.

7. The first interface device of claim 6, further comprising: a data selection unit for selecting a data from the plurality of data blocks,

the data selection unit includes:

a first input port electrically coupled to the transmitting unit for receiving communication data transmitted by the transmitting unit;

a second input port electrically coupled to the data flow control unit for receiving memory status information sent by the data flow control unit; and

an output port communicatively coupled to the counter interface device for alternatively outputting the communication data or the storage status information, wherein,

8. The first interface device of claim 1, wherein serial communication between the first interface device and the subtended interface device is performed in a time division multiplexed manner.

9. A method for serial communication, comprising:

determining the data volume of communication data which is transmitted by a first interface device to a corresponding opposite interface device, wherein the opposite interface device comprises a storage unit for storing the communication data;

receiving input information from the opposite interface device, wherein the input information comprises storage state information of a storage unit of the opposite interface device;

generating a first count value indicating the accumulated transmission data amount of the first interface device according to the data amount of the communication data transmitted by the first interface device to the corresponding opposite interface device;

generating a second count value indicating an amount of data that a storage unit of the counter interface device has been read, according to the received storage state information;

calculating an available storage space of a storage unit of the opposite interface device based on a difference value of the first count value and the second count value; and

10. The method of claim 9, wherein the expected data amount of communication data transmitted to the subtended interface device is less than or equal to an available storage space of a storage unit of the subtended interface device.

11. The method of claim 9, wherein the input information further comprises communication data transmitted by the subtended interface device.

12. The method of claim 11, wherein the incoming information comprises a plurality of cells, a cell comprising a header and a payload, wherein the header is used to indicate that the payload is storage status information of a storage unit of the subtended interface apparatus or communication data transmitted by the subtended interface apparatus.

13. An electronic device comprising a first interface arrangement as claimed in any one of claims 1-8.