CN102436840A - Digital radio frequency memory board - Google Patents
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- CN102436840A CN102436840A CN2011104099313A CN201110409931A CN102436840A CN 102436840 A CN102436840 A CN 102436840A CN 2011104099313 A CN2011104099313 A CN 2011104099313A CN 201110409931 A CN201110409931 A CN 201110409931A CN 102436840 A CN102436840 A CN 102436840A
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Abstract
The invention provides a digital radio frequency memory board. An analog/digital converter module for the digital radio frequency memory board is used for acquiring an external analog signal at a high speed, converting the external analog signal into a digital signal and transmitting the digital signal to a first field programmable gate array (FPGA) module, wherein the first FPGA module is used for performing primary programmable processing on the digital signal and transmitting the digital signal to a second FPGA module; the second FPGA module is used for performing secondary programmable processing on data and finally transmitting the data to a digital/analog converter module; the digital/analog converter module is used for converting the digital signal into an analog signal at a high speed and outputting the analog signal; a first static random access memory (SRAM) module is connected with the first FPGA module and is used for caching data of the first FPGA module; and a second SRAM module is connected with the second FPGA module and is used for caching data of the second FPGA module. The digital radio frequency memory board has high-speed data acquisition and playback capacity, and the functions of data acquisition, storage, transmission and playback can be flexibly realized.
Description
Technical field
The present invention relates to technical field of data storage, be specifically related to a kind of digital radio-frequency memory board.
Background technology
The digital RF memory technology is the basis with high-speed sampling technology and digital storage technique, has storage and reproduction to the frequency higher signal, is widely used in field of radar.
At present; Digital RF memory technology commonly used realizes function of radar and performance test in the radar signal testing apparatus; The sampling rate of requirement digital radio-frequency memory board and playback rate are more than 1GSPS; The analog/digital converter module need be lacked to the delay of the simulating signal of digital/analog converter module as far as possible simultaneously, uses general digital signal processor (DSP, Digital Signal Processer) to be difficult to satisfy harsh like this requirement.
Summary of the invention
The invention provides a kind of digital radio-frequency memory board, have HSDA and playback capability, can realize functions such as data acquisition, storage, transmission and playback flexibly.
A kind of digital radio-frequency memory board comprises:
Analog/digital converter module, digital/analog converter module, primary scene programmable gate array (FPGA; Field-Programmable Gate Array) module, the 2nd FPGA module, first static memory (SRAM, Static RAM) module, the 2nd SRAM module and clock chip; A said SRAM module and the 2nd SRAM module comprise two synchronous sram chips respectively;
Said clock chip is used to said analog/digital converter module, digital/analog converter module, a FPGA module and the 2nd FPGA module clock and synchronous signal impulse is provided;
Said analog/digital converter module is used for the analog signal conversion of outside input is become digital signal and it is outputed to a FPGA module through Low Voltage Differential Signal technical interface (LVDS, Low Voltage Differential Signaling) signal wire;
A said FPGA module is connected with said the 2nd a FPGA module and a said SRAM module respectively; Being used for that the digital signal of analog/digital converter module input is carried out the one-level programmable delay handles; Data after the processing are written to a said SRAM module; A said SRAM module is used for data are carried out behind the buffer memory the data said FPGA module of reading back again, and a said FPGA module is used for data are transferred to the 2nd FPGA module through the data channel between a FPGA module and the 2nd FPGA module; Data channel between a said FPGA module and the 2nd FPGA module be more than two pairs LVDS signal wire or high speed serialization transceiver more than two pairs (Ser-Des, SERializer-DESerializer);
Said the 2nd FPGA module is connected with a said FPGA module, said the 2nd SRAM module and said digital/analog converter module respectively; Be used to receive the data of said FPGA module transmission; Carrying out the secondary programmable delay handles; Data after the processing are written to said the 2nd SRAM module; Said the 2nd SRAM module is used for data are carried out data being read back to said the 2nd FPGA module behind the buffer memory again, and said the 2nd FPGA module is used for data are arrived the digital/analog converter module through the LVDS signal wire transmits between said the 2nd FPGA module and the said digital/analog converter module;
Said digital/analog converter module is used for converting the digital signal of the 2nd FPGA module input to simulating signal and simulating signal output is outside.
Optional, said digital radio-frequency memory board also comprises:
The 3rd FPGA module and peripheral component interconnection (PCI, Peripheral Component Interconnect) interface module; Said the 3rd FPGA module is connected with pci interface module, a FPGA module, the 2nd FPGA module respectively, is used for receiving outside integrated circuit board through said pci interface module and transmits the data of coming in and give a said FPGA module, the 2nd FPGA module with data transmission; Said the 3rd FPGA module is used to receive a said FPGA module, the 2nd FPGA module and transmits the data of coming in, and through said pci interface module with data transmission to outside integrated circuit board; Said the 3rd FPGA module also is used for through outside direct memory access (DMA, Direct Memory Access) engine data in buffer in host computer transmits from a said SRAM module and said the 2nd SRAM module.
Optional, said digital radio-frequency memory board also comprises NOR FLASH (a kind of non-volatile flash memory device) chip; Said NOR FLASH chip is connected with said the 3rd FPGA module, is used to store the configuration data of host computer to a said FPGA module and said the 2nd FPGA module loading;
Said the 3rd FPGA module also is used for reading the configuration data of said NOR FLASH chip-stored and is written into a said FPGA module and said the 2nd FPGA module, so that a said FPGA module and said the 2nd FPGA module are configured the logic loading;
Said the 3rd FPGA module also is used for through outside ROM (read-only memory) (PROM, programmable read-only memory) device self being loaded configuration logic.
Optional, said digital radio-frequency memory board also comprises: the J1 connector of compact PCI (CPCI, Compact Peripheral Component Interconnect);
The J1 connector of said CPCI is connected with said pci interface module, is used for through data transmission to the three FPGA modules of said pci interface module with outside integrated circuit board; Also be used for giving outside integrated circuit board through the data transmission of said pci interface module transmission with the 3rd FPGA module.
Optional, said digital radio-frequency memory board also comprises the J3 connector of CPCI;
The J3 connector of said CPCI is connected with a said FPGA module through the LVDS signal wire more than two pairs, is used for giving a said FPGA module with the data transmission of outside integrated circuit board, also is used for giving outside integrated circuit board with the data transmission of a said FPGA module.
Optional, said digital radio-frequency memory board also comprises: the J5 connector of CPCI;
The J5 connector of said CPCI is connected with said the 2nd FPGA module through the LVDS signal wire more than two pairs, is used for giving said the 2nd FPGA module with the data transmission of outside integrated circuit board, also is used for giving outside integrated circuit board with the data transmission of said the 2nd FPGA module.
Optional, said digital radio-frequency memory board also comprises: the high-speed-differential connector;
The high-speed-differential connector can be selected the ERmet ZD connector of ERNI company for use, and said high speed connector is connected with a said FPGA module through the Ser-Des of a plurality of passages; Said high-speed-differential connects device and also is connected with a said FPGA module through a plurality of passage Ser-Des; Said high-speed-differential connector is used for the data high-speed of a said FPGA module and the 2nd FPGA module is transferred to outside integrated circuit board, also is used for the data transmission of outside integrated circuit board is arrived a said FPGA module and the 2nd FPGA module.
Can find out that from above technical scheme the embodiment of the invention has the following advantages:
The simulating signal that the analog/digital converter module high speed acquisition of digital radio-frequency memory board provided by the invention is outside; Its high-speed transitions is digital signal and is transferred to a FPGA module; The one FPGA module carries out the digital signal of said analog/digital converter module input to be transferred to the 2nd FPGA module after the one-level processing able to programme; Said the 2nd FPGA module is carried out secondary processing able to programme with data again; Giving the digital/analog converter module with data transmission at last, is simulating signal and output with the digital signal high-speed transitions.Wherein, a SRAM module is connected with a FPGA module, is used for the data of buffer memory the one FPGA module; The 2nd SRAM module is connected with the 2nd FPGA module, is used for the data of buffer memory the 2nd FPGA module.Digital radio-frequency memory board of the present invention has HSDA and playback capability, can realize functions such as data acquisition, storage, transmission and playback flexibly.
Description of drawings
Fig. 1 is the functional module principle assumption diagram of a kind of digital radio-frequency memory board provided by the invention;
Fig. 2 is the data delay process basic principle figure of a kind of digital radio-frequency memory board provided by the invention.
Embodiment
To combine the accompanying drawing among the present invention below, the technical scheme among the present invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The embodiment of the invention provides a kind of digital radio-frequency memory board, is used to realize functions such as data acquisition, storage, transmission and playback.Have HSDA and playback capability.
See also Fig. 1, Fig. 2, Fig. 1 is the functional module principle assumption diagram of a kind of digital radio-frequency memory board provided by the invention; Fig. 2 is the data delay process basic principle figure of a kind of digital radio-frequency memory board provided by the invention.A kind of digital radio-frequency memory board comprises:
Analog/digital converter module, digital/analog converter module, a FPGA module, the 2nd FPGA module, a SRAM module, the 2nd SRAM module and clock chip; A said SRAM module and the 2nd SRAM module comprise two synchronous sram chips respectively;
Said clock chip is used to said analog/digital converter module, digital/analog converter module, a FPGA module and the 2nd FPGA module clock and synchronous signal impulse is provided;
Wherein, said clock and synchronous signal impulse both can be provided by external clock reference, also can be produced by the inner voltage-controlled oscillator (VCO, voltage-controlled oscillator) of said clock chip.
Said analog/digital converter module is used for the analog signal conversion of outside input is become digital signal and it is outputed to a FPGA module through the LVDS signal wire;
A said FPGA module is connected with said the 2nd a FPGA module and a said SRAM module respectively; Being used for that the digital signal of analog/digital converter module input is carried out the one-level programmable delay handles; Data after the processing are written to a said SRAM module; A said SRAM module is used for data are carried out behind the buffer memory the data said FPGA module of reading back again, and a said FPGA module is used for data are transferred to the 2nd FPGA module through the data channel between a FPGA module and the 2nd FPGA module; Data channel between a said FPGA module and the 2nd FPGA module is LVDS signal wire or the Ser-Des transceiver more than two pairs more than two pairs;
Wherein, as a preferred embodiment, the data channel between a said FPGA module and the 2nd FPGA module can be 80 pairs of LVDS signal wires or 16 pairs of Ser-Des transceivers.The present invention does not limit the quantity of the Ser-Des transceiver of the quantity of the LVDS signal wire that uses and use.
Said the 2nd FPGA module is connected with a said FPGA module, said the 2nd SRAM module and said digital/analog converter module respectively; Be used to receive the data of said FPGA module transmission; Carrying out the secondary programmable delay handles; Data after the processing are written to said the 2nd SRAM module; Said the 2nd SRAM module is used for data are carried out data being read back to said the 2nd FPGA module behind the buffer memory again, and said the 2nd FPGA module is used for data are arrived the digital/analog converter module through the LVDS signal wire transmits between said the 2nd FPGA module and the said digital/analog converter module;
Said digital/analog converter module is used for the digital signal of the 2nd FPGA module input is converted to simulating signal and simulating signal is outputed to the outside.
Wherein, the invention provides the digital radio-frequency memory board of a kind of 6U CPCI.The one FPGA module and the 2nd FPGA module all adopt the fpga chip of Xilinx company or altera corp.The interface mode of a FPGA module and analog/digital converter module and the interface mode of the 2nd FPGA module and digital/analog converter module are considered in the selection of fpga chip, are main with LVDS generally.Also to consider BRAM (Block RAM), DSP, Ser-Des, LUT (Look-Up-Table) and a SRAM module that is connected respectively with a FPGA module, the 2nd FPGA module or the interface type and the clock resource of the 2nd SRAM module in the fpga chip.
The chip of said analog/digital converter module and said digital/analog converter module all will be selected according to bandwidth, signal sampling rate and the dynamic range of radiofrequency signal.Adopt the LVDS signal wire to be connected between said analog/digital converter module and the FPGA module, data transmission employing source Synchronous Transfer Mode.Adopt the LVDS signal wire to be connected between said digital/analog converter module and the 2nd FPGA module, data transmission employing source Synchronous Transfer Mode.
Wherein, as a preferred embodiment, can adopt two kinds of data transfer modes between a FPGA module and the 2nd FPGA module.A kind of can be interconnected with 80 pairs of LVDS signal wires; Adopt the Hi-Link interface to carry out high speed data transfer between the one FPGA module and the 2nd FPGA module, the one-way data bandwidth reaches 8GByte/s.Another kind can be to adopt the high speed serialization transceiver to connect, and adopts 16 couples of two-way Ser-Des interconnected between a FPGA module and the 2nd FPGA module, and the bi-directional data rate reaches 10GByte/s.Adopt first kind of mode for postponing less demanding data communication.Big for data volume, require time delay short as far as possible data communication to adopt the second way.Certainly, both also can combine use.
A said SRAM module and the 2nd SRAM module comprise two synchronous sram chips respectively.The quadruple of sram chip employing synchronously Cypress, GSI or Samsung company is according to multiplying power (QDR SRAM; Quad Data Rate) SRAM or double data multiplying power (DDR SRAM; Double Data Rate), its capacity was confirmed according to the time of radio frequency storage.QDR SRAM can effectively improve the transmission bandwidth of data owing to adopt independently reading-writing port, and these characteristics are effective especially to the realization of the delay algorithm in the digital RF memory technology.The IO resource of the FPGA that DDR SRAM takies is more.It is fast that these two kinds of storeies all have storage speed, the characteristics that data access delay is fixing, and postponing fixing these characteristics is that common SDRAM is not available.
As a kind of optional embodiment, said digital radio-frequency memory board also comprises:
The 3rd FPGA module and pci interface module; Said the 3rd FPGA module is connected with pci interface module, a FPGA module, the 2nd FPGA module respectively, is used for receiving outside integrated circuit board through said pci interface module and transmits the data of coming in and give a said FPGA module, the 2nd FPGA module with data transmission; Said the 3rd FPGA module is used to receive a said FPGA module, the 2nd FPGA module and transmits the data of coming in, and through said pci interface module with data transmission to outside integrated circuit board; Said the 3rd FPGA module also is used for transmitting from a said SRAM module and said the 2nd SRAM module data in buffer to host computer through the DMA engine.
Wherein, can adopt the function of the pci interface chip realization pci interface module of PLX company, also can use the 3rd FPGA directly to realize the function of pci interface module.The bit wide and the clock of pci bus mainly considered in the realization of pci interface module.Need use the DMA engine when transmitting data in enormous quantities, consider the interface voltage of CPCI simultaneously.When using the 3rd FPGA module to realize the pci interface functions of modules, consider PCI bridging chip or level transferring chip.The interface slot position that digital radio-frequency memory board need be inserted in the CPCI cabinet is configured and manages through host computer.
Wherein, the shared bus controller of a FPGA module and the 2nd FPGA module adopts the 3rd FPGA to realize.When adopting pci interface chip to realize the function of pci interface module, the 3rd FPGA one side joint is on pci interface chip, and opposite side adopts the mode of shared bus to connect a FPGA module and the 2nd FPGA module.When using the 3rd FPGA module directly to realize the function of pci interface module, the 3rd FPGA one side directly is connected on the pci bus, and opposite side adopts the mode of shared bus to connect a FPGA module and the 2nd FPGA module.Host computer can be visited the various spaces on a FPGA module and the 2nd FPGA module through shared bus.The 3rd FPGA module can also be through the DMA engine to the various test datas of a large amount of transmission of host computer.
As a kind of optional embodiment, said digital radio-frequency memory board also comprises NOR FLASH chip; Said NOR FLASH chip is connected with said the 3rd FPGA module, is used to store the configuration data of host computer to a said FPGA module and said the 2nd FPGA module loading;
Said the 3rd FPGA module also is used for reading the configuration data of said NOR FLASH chip-stored and is written into a said FPGA module and said the 2nd FPGA module, so that a said FPGA module and said the 2nd FPGA module are configured the logic loading;
Said the 3rd FPGA module also is used for through outside ROM (read-only memory) (PROM, programmable read-only memory) device self being loaded configuration logic.
Wherein, the 3rd FPGA modules configured adopts the PROM configuration mode, can load configuration logic voluntarily after digital radio-frequency memory board powers on.After having loaded, the 3rd FPGA module adopts two kinds of configuration modes to dispose two FPGA as a FPGA module and the 2nd FPGA modules configured main control unit.A kind of is to load configuration logic through host computer, and host computer is written to configuration data respectively in the one FPGA module and the 2nd FPGA module and the NOR FLASH chip through the pci interface module.Another kind is that the 3rd FPGA module reads the configuration data in the NOR FLASH chip, and configuration data is written in a FPGA module and the 2nd FPGA module.Simultaneously, a FPGA module, the 2nd FPGA module and the 3rd FPGA module can be passed through joint test behavior tissue (JTAG, Joint Test Action Group) interface and be configured respectively.
As a kind of optional embodiment, said digital radio-frequency memory board also comprises: the J1 connector of CPCI;
The J1 connector of said CPCI is connected with said pci interface module, is used for through data transmission to the three FPGA modules of said pci interface module with outside integrated circuit board; Also be used for giving outside integrated circuit board through the data transmission of said pci interface module transmission with the 3rd FPGA module.
As a kind of optional embodiment, said digital radio-frequency memory board also comprises the J3 connector of CPCI; The J3 connector of said CPCI is connected with a said FPGA module through the LVDS signal wire more than two pairs, is used for giving a said FPGA module with the data transmission of outside integrated circuit board, also is used for giving outside integrated circuit board with the data transmission of a said FPGA module.
As a kind of preferred embodiment, the J3 connector of said CPCI can be connected with a said FPGA module through 20 pairs of LVDS signal wires.The present invention does not limit the LVDS signal wire quantity that is adopted.
As a kind of optional embodiment, said digital radio-frequency memory board also comprises: the J5 connector of CPCI; The J5 connector of said CPCI is connected with said the 2nd FPGA module through the LVDS signal wire more than two pairs, is used for giving said the 2nd FPGA module with the data transmission of outside integrated circuit board, also is used for giving outside integrated circuit board with the data transmission of said the 2nd FPGA module.
Wherein, as a kind of preferred embodiment, the J5 connector of CPCI can be connected with said the 2nd FPGA module through 20 pairs of LVDS signal wires.The present invention does not limit the quantity of the LVDS signal wire of employing.
As a kind of optional embodiment, said digital radio-frequency memory board also comprises: high-speed-differential connector (being designated as ZD in the accompanying drawing 1);
The high-speed-differential connector can be selected the ERmet ZD connector of ERNI company for use, and said high speed connector is connected with a said FPGA module through the Ser-Des of a plurality of passages; Said high-speed-differential connects device and also is connected with a said FPGA module through a plurality of passage Ser-Des; Said high-speed-differential connector is used for the data high-speed of a said FPGA module and the 2nd FPGA module is transferred to outside integrated circuit board, also is used for the data transmission of outside integrated circuit board is arrived a said FPGA module and the 2nd FPGA module.
As preferred embodiment a kind of, high speed connector can be connected with a said FPGA module through the Ser-Des of 8 passages; Said high-speed-differential connects device and can also be connected with a said FPGA module through 8 passage Ser-Des.The present invention does not do concrete qualification to the number of channels that the Ser-Des transceiver comprises.
The simulating signal that the analog/digital converter module high speed acquisition of digital radio-frequency memory board provided by the invention is outside; Its high-speed transitions is digital signal and is transferred to a FPGA module; The one FPGA module carries out the digital signal of said analog/digital converter module input to be transferred to the 2nd FPGA module after the one-level processing able to programme; Said the 2nd FPGA module is carried out secondary processing able to programme with data again; Giving the digital/analog converter module with data transmission at last, is simulating signal and output with the digital signal high-speed transitions.Wherein, a SRAM module is connected with a FPGA module, is used for the data of buffer memory the one FPGA module; The 2nd SRAM module is connected with the 2nd FPGA module, is used for the data of buffer memory the 2nd FPGA module.The one SRAM module and the 2nd SRAM module comprise two synchronous sram chips respectively.Digital radio-frequency memory board of the present invention has HSDA and playback capability, can realize functions such as data acquisition, storage, transmission and playback flexibly.
More than a kind of digital radio-frequency memory board provided by the present invention has been carried out detailed introduction; For one of ordinary skill in the art; Thought according to the embodiment of the invention; The part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (7)
1. a digital radio-frequency memory board is characterized in that, comprising:
Analog/digital converter module, digital/analog converter module, a FPGA module, the 2nd FPGA module, a SRAM module, the 2nd SRAM module and clock chip; A said SRAM module and the 2nd SRAM module comprise two synchronous sram chips respectively;
Said clock chip is used to said analog/digital converter module, digital/analog converter module, a FPGA module and the 2nd FPGA module clock and synchronous signal impulse is provided;
Said analog/digital converter module is used for the analog signal conversion of outside input is become digital signal and it is outputed to a FPGA module through the LVDS signal wire;
A said FPGA module is connected with said the 2nd a FPGA module and a said SRAM module respectively; Being used for that the digital signal of analog/digital converter module input is carried out the one-level programmable delay handles; Data after the processing are written to a said SRAM module; A said SRAM module is used for data are carried out behind the buffer memory the data said FPGA module of reading back again, and a said FPGA module is used for data are transferred to the 2nd FPGA module through the data channel between a FPGA module and the 2nd FPGA module; Data channel between a said FPGA module and the 2nd FPGA module is LVDS signal wire or the Ser-Des transceiver more than two pairs more than two pairs;
Said the 2nd FPGA module is connected with a said FPGA module, said the 2nd SRAM module and said digital/analog converter module respectively; Be used to receive the data of said FPGA module transmission; Carrying out the secondary programmable delay handles; Data after the processing are written to said the 2nd SRAM module; Said the 2nd SRAM module is used for data are carried out data being read back to said the 2nd FPGA module behind the buffer memory again, and said the 2nd FPGA module is used for data are arrived the digital/analog converter module through the LVDS signal wire transmits between said the 2nd FPGA module and the said digital/analog converter module;
Said digital/analog converter module is used for that digital signal with the 2nd FPGA module input converts simulating signal to and with the simulating signal output system.
2. digital radio-frequency memory board according to claim 1 is characterized in that, also comprises:
The 3rd FPGA module and pci interface module;
Said the 3rd FPGA module is connected with pci interface module, a FPGA module, the 2nd FPGA module respectively, is used for receiving outside integrated circuit board through said pci interface module and transmits the data of coming in and give a said FPGA module, the 2nd FPGA module with data transmission; Said the 3rd FPGA module is used to receive a said FPGA module, the 2nd FPGA module and transmits the data of coming in, and through said pci interface module with data transmission to outside integrated circuit board; Said the 3rd FPGA module also is used for transmitting from a said SRAM module and said the 2nd SRAM module data in buffer to host computer through outside DMA engine.
3. digital radio-frequency memory board according to claim 2 is characterized in that, also comprises:
NOR FLASH chip; Said NOR FLASH chip is connected with said the 3rd FPGA module, is used to store the configuration data of host computer to a said FPGA module and said the 2nd FPGA module loading;
Said the 3rd FPGA module also is used for reading the configuration data of said NOR FLASH chip-stored and is written into a said FPGA module and said the 2nd FPGA module, so that a said FPGA module and said the 2nd FPGA module are configured the logic loading;
Said the 3rd FPGA module also is used for through outside PROM device self being loaded configuration logic.
4. digital radio-frequency memory board according to claim 3 is characterized in that, also comprises: the J1 connector of CPCI;
The J1 connector of said CPCI is connected with said pci interface module, is used for through data transmission to the three FPGA modules of said pci interface module with outside integrated circuit board; Also be used for giving outside integrated circuit board through the data transmission of said pci interface module transmission with the 3rd FPGA module.
5. digital radio-frequency memory board according to claim 4 is characterized in that, also comprises: the J3 connector of CPCI;
The J3 connector of said CPCI is connected with a said FPGA module through the LVDS signal wire more than two pairs, is used for giving a said FPGA module with the data transmission of outside integrated circuit board, also is used for giving outside integrated circuit board with the data transmission of a said FPGA module.
6. digital radio-frequency memory board according to claim 5 is characterized in that, also comprises: the J5 connector of CPCI;
The J5 connector of said CPCI is connected with said the 2nd FPGA module through the LVDS signal wire more than two pairs, is used for giving said the 2nd FPGA module with the data transmission of outside integrated circuit board, also is used for giving other integrated circuit boards with the data transmission of said the 2nd FPGA module.
7. digital radio-frequency memory board according to claim 6 is characterized in that, also comprises: the high-speed-differential connector;
Said high speed connector is connected with a said FPGA module through the above Ser-Des of two passages; Said high-speed-differential connects device and also is connected with a said FPGA module through the above Ser-Des of two passages; Said high-speed-differential connector is used for the data transmission of a said FPGA module and the 2nd FPGA module is arrived outside integrated circuit board, also is used for the data transmission of outside integrated circuit board is arrived a said FPGA module and the 2nd FPGA module.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| CN105912487A (en) * | 2016-04-07 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | Data timing sequence equalizing method and system |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| US10169264B1 (en) * | 2017-06-30 | 2019-01-01 | Xilinx, Inc. | Implementing robust readback capture in a programmable integrated circuit |
| CN109656853A (en) * | 2017-10-11 | 2019-04-19 | 阿里巴巴集团控股有限公司 | A kind of data transmission system and method |
| CN114281737A (en) * | 2021-12-29 | 2022-04-05 | 天津光电通信技术有限公司 | Signal processing platform based on CPCI framework and FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604541A (en) * | 2009-06-24 | 2009-12-16 | 北京理工大学 | Two-channel digital radio-frequency memory board |
| CN101819556A (en) * | 2010-03-26 | 2010-09-01 | 北京经纬恒润科技有限公司 | Signal-processing board |
| KR101007269B1 (en) * | 2010-06-01 | 2011-01-13 | 삼성탈레스 주식회사 | Digital radio frequency memory with phase dithering |
-
2011
- 2011-12-09 CN CN2011104099313A patent/CN102436840A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604541A (en) * | 2009-06-24 | 2009-12-16 | 北京理工大学 | Two-channel digital radio-frequency memory board |
| CN101819556A (en) * | 2010-03-26 | 2010-09-01 | 北京经纬恒润科技有限公司 | Signal-processing board |
| KR101007269B1 (en) * | 2010-06-01 | 2011-01-13 | 삼성탈레스 주식회사 | Digital radio frequency memory with phase dithering |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| CN105912487A (en) * | 2016-04-07 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | Data timing sequence equalizing method and system |
| US10169264B1 (en) * | 2017-06-30 | 2019-01-01 | Xilinx, Inc. | Implementing robust readback capture in a programmable integrated circuit |
| CN109656853A (en) * | 2017-10-11 | 2019-04-19 | 阿里巴巴集团控股有限公司 | A kind of data transmission system and method |
| CN114281737A (en) * | 2021-12-29 | 2022-04-05 | 天津光电通信技术有限公司 | Signal processing platform based on CPCI framework and FPGA |
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