CN204390227U - Computing equipment expanding unit and extendible computing system - Google Patents
Computing equipment expanding unit and extendible computing system Download PDFInfo
- Publication number
- CN204390227U CN204390227U CN201520075699.8U CN201520075699U CN204390227U CN 204390227 U CN204390227 U CN 204390227U CN 201520075699 U CN201520075699 U CN 201520075699U CN 204390227 U CN204390227 U CN 204390227U
- Authority
- CN
- China
- Prior art keywords
- port
- signal
- data
- extension device
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
Disclose a kind of computing equipment expanding unit and extendible computing system.Described device extension device comprises: the first port, for being connected with the computing equipment of outside via rambus; Second port, for being connected with the storer of outside via rambus; And the 3rd port, for being connected with the expanded function unit of outside via User Defined bus, wherein, described device extension device produces according to the rambus signal transmitted from computing equipment and selects signal, any one port in first to the 3rd port is connected with a port in all the other two ports in the first to the 3rd port, thus the routing function of rambus is provided, described rambus signal comprises data-signal and address and control signal.Because device extension device can use rambus and the memory bank of standard, therefore can compatible original computing system, and provide what's new at low cost.
Description
Technical field
The utility model belongs to computing equipment expansion technique, particularly, relates to computing equipment expanding unit and extendible computing system.
Background technology
Along with the development of embedded computer technology, the integrated level of computing equipment is more and more higher, and from strength to strength, its complexity also improves constantly for performance and function.
Computing equipment not only comprises the general processor used in computing machine, also comprises the SOC (system on a chip) (referred to as SoC) processor and peripheral electronic system are integrated in a chip.SOC (system on a chip) is customization or the standardized product towards special-purpose, can reduce manufacturing cost although it is so, but there is the problem of extendability difference.Existing computing equipment (especially SoC) also exists the contradiction being difficult to be in harmonious proportion in versatility and economy.System developer attempts to design the single-chip computing equipment that can meet various user's request, but is in fact difficult to meet the customized demand of different user in different application.
Fig. 1 illustrates the schematic block diagram of existing computing system.Computing system 100 comprises computing equipment 101 (such as SoC) and external memory storage 102 (such as RAM).External memory storage 102 is the peripherals of computing equipment 101.Via rambus transmission of data signals and address and control signal between computing equipment 101 and external memory storage 102.
For the customized demand of user, the extended mode of computing system 100 comprises: utilize software simulating or utilize plate level resource to add New function.When utilizing software simulating New function, will the computing power of computing equipment 101 be taken, thus cause the hydraulic performance decline of computing system 100.When utilizing plate level resource to add New function, hardware and interface resource will be taken, such as High Speed I/O, ADC, DAC etc.
Computing equipment 101 for SoC and peripherals is field programmable gate array (FPGA) when, wish the communication interconnect that high bandwidth is provided between.Existing plate level resource is difficult to meet described bandwidth demand.If the not reserved hardware of board level system and interface resource, then can not add New function.In addition, utilize plate level resource add New function also will cause hardware design and software administration complicated.
Utility model content
The purpose of this utility model is to provide a kind of computing equipment expanding unit and extendible computing system.
According to the one side of the utility model embodiment, a kind of device extension device is provided, comprises: the first port, for being connected with the computing equipment of outside via rambus; Second port, for being connected with the storer of outside via rambus; And the 3rd port, for being connected with the expanded function unit of outside via User Defined bus, wherein, described device extension device produces according to the rambus signal transmitted from computing equipment and selects signal, any one port in first to the 3rd port is connected with a port in all the other two ports in the first to the 3rd port, thus the routing function of rambus is provided, described rambus signal comprises data-signal and address and control signal.
Preferably, described device extension device also comprises: the first data buffer, for the data-signal that buffer memory send via first end oral instructions; Second data buffer, for the data-signal that buffer memory transmits via the second port; 3rd data buffer, for the data-signal that buffer memory transmits via the 3rd port; Code translator, for according to the address sent via first end oral instructions and control signal, produces described selection signal; And data-reusing module, for according to selection signal, at least two data buffers in the first to the 3rd data buffer are connected.
Preferably, data-reusing module comprises at least one multiplexer.
Preferably, described device extension device also comprises by-pass switch array, and the second port, according to selection signal, is optionally delivered to from first end oral instructions in address and control signal by described by-pass switch array.
Preferably, at least two data buffer gatings in the first to the 3rd data buffer.
Preferably, described code translator produces according to the chip selection signal in address and control signal and/or address signal and selects signal.
Preferably, described address signal comprises address date and retains data, and described reservation data instruction stores operation or expanding communication operation.
According to the another aspect of the utility model embodiment, a kind of extendible computing system is provided, comprises: above-mentioned device extension device; Computing equipment, is connected with the first port of device extension device via rambus; Storer, is connected with the second port of device extension device via rambus; And expanded function unit, be connected with the 3rd port of device extension device via User Defined bus.
Preferably, described computing equipment is be selected from the one in general processor and SOC (system on a chip).
Preferably, the function of described expanded function unit is configurable.
Preferably, described expanded function unit is field programmable gate array.
Preferably, the data-signal of described device extension device the first port and second port when storage operates and address and control signal are symmetrical.
Preferably, described computing system also comprises the mainboard with the first memory bank, first port of device extension device provides pin, for being connected with the first memory bank, second port of device extension device provides the second memory bank, for being connected with storer, the 3rd port of device extension device provides expansion interface, for being connected with expanded function unit.
The complicacy of computing equipment design greatly can be reduced according to computing system of the present utility model, computing equipment is made only to need to be absorbed in computing function, USB interface, printing interface, high-speed communication and parallel computation etc. are realized by expanded function unit, also just reduce the requirement of the specification to special module, the versatility of computing equipment can be kept.Utilize expanded function unit to provide customization function, thus still keep economy.Because device extension device can use rambus and the memory bank of standard, therefore, this computing equipment expansion scheme can compatible original computing system, and provides what's new at low cost.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the utility model embodiment, above-mentioned and other objects of the present utility model, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 illustrates the schematic block diagram of existing computing system;
Fig. 2 illustrates the schematic block diagram of the extendible computing system according to embodiment of the present utility model;
Fig. 3 illustrates the schematic block diagram of the device extension device according to an embodiment of the present utility model;
Fig. 4 illustrates the schematic block diagram of the device extension device according to another embodiment of the present utility model; And
Fig. 5 is the process flow diagram of the extended method of extendible computing system according to embodiment of the present utility model.
Embodiment
Hereinafter with reference to accompanying drawing, various embodiment of the present utility model is described in more detail.In various figures, identical element adopts same or similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
The utility model can present in a variety of manners, below will describe some of them example.
Fig. 2 illustrates the schematic block diagram of the extendible computing system according to embodiment of the present utility model.Computing system 200 comprises computing equipment 201, and via the external memory storage 202 that rambus is connected with computing equipment 201.External memory storage 202 is peripheral components of computing equipment 201.
In a preferred embodiment, computing equipment 201 is SOC (system on a chip) (SoC), and external memory storage 202 is synchronous DRAM (SDRAM).Correspondingly, rambus is SDRAM bus.
In a preferred embodiment, external memory storage 202 comprises primary memory and secondary store.Secondary store is additional storer in order to expanding system bandwidth.
Via rambus transmission of data signals and address and control signal between computing equipment 201 and external memory storage 202.Correspondingly, rambus comprises address bus, data bus and control bus.Control bus is used for externally storer 202 provides read-write, and address bus is used to specify the selected cell address in external memory storage 202.Data bus is two-way, for from computing equipment 201 externally storer 202 transmit data to be written, or for transmitting to computing equipment 201 data read from external memory storage 202.
Different according to the computing system of prior art from shown in Fig. 1, in computing system 200 of the present utility model, computing equipment 201 does not have directly to be connected with external memory storage 202.Alternatively, computing system 200 of the present utility model also comprises device extension device 203 and expanded function unit 204, and device extension device 203 is between computing equipment 201 and external memory storage 202.
Device extension device 203 provides the routing function of rambus, makes computing equipment 201 or is connected with external memory storage 202 via device extension device 203, or being connected with expanded function unit 204 via device extension device 203.Therefore, computing equipment 201 not only via rambus access external memory 202, can also can communicate with expanded function unit 204 via rambus.
Expanded function unit 204 is the newly-increased hardware resources expanding out by device extension device 203.The application does not limit type, form, the implementation of expanded function unit 204, does not suppose the hardware environment at its place or the applied environment of more top yet.Expanded function unit 204 represents hardware resource newly-increased in computing system 200 under the support of device extension device 203.
Bidirectional connecting lines in Fig. 2 represents rambus and User Defined bus, and data flow is wherein two-way.Rambus is the bus that external memory storage 202 (such as, SDRAM, DDR-SDRAM, LPDDR-SDRAM etc.) uses.User Defined bus is the bus between expanded function unit 204 and device extension device 203.
In a preferred embodiment, device extension device 203 allows expanded function unit 204 access external memory 202.Therefore, computing equipment 201 and expanded function unit 204 can share external memory storage 202.
In a preferred embodiment, expanded function unit 204 is various logic functional units that FPGA realizes.Due to the configurability of FPGA itself, the function of expanded function unit 204 can flexible configuration, to meet different application demands, such as, can realize various possible parallel computation, issued transaction or realize various peripheral interface.The configurability of expanded function unit 204 makes computing system 200 can meet the functional requirement of different application.
Adopt the computing system 200 of this framework both can make full use of the computing ability of computing equipment 201, expanded function unit 204 can be utilized again to provide high-speed communication, parallel computation and peripheral interface, thus expand peripheral computing device easily, form a performance and all more powerful system of function.Therefore, the system of the present embodiment can reduce the complicacy of computing equipment 201 design greatly, makes computing equipment 201 only to need to be absorbed in computing function.The versatility of computing equipment 201 can be kept according to computing system 200 of the present utility model, and utilize expanded function unit 204 to provide customization function, thus still keep economy.Because expanded function unit 204 can use rambus and the memory bank of standard, therefore, this computing equipment expansion scheme can compatible original computing system, and provides what's new at low cost.
Fig. 3 illustrates the schematic block diagram of the device extension device according to an embodiment of the present utility model.See Fig. 2, device extension device 203 is actually the route device on the rambus that is connected between computing equipment 201 and external memory storage 202.
In a preferred embodiment, device extension device 203 is such as the expansion card comprising three ports.First port is used for providing pin, combines with the memory bank on mainboard, thus provides the connection between computing equipment 201 and device extension device 203.Second port is used for providing memory bank, combines with external memory storage 202, thus provides the connection between device extension device 203 and external memory storage 202.3rd port is used for providing expansion interface, such as USB port, thus provides the connection between device extension device 203 and expanded function unit 204.
Device extension device 203 comprises the data buffer 2031,2035 and 2037 corresponding respectively with the first to the 3rd port.Data buffer 2031, via rambus, obtains data-signal from computing equipment 201 or provides data-signal to computing equipment 201.Data buffer 2035 via rambus, from external memory storage 202 obtain data-signal or externally storer 202 data-signal is provided.Data buffer 2037, via User Defined bus, communicates with expanded function unit 204.
In a preferred embodiment, data buffer 2031,2035 and 2037 is respectively three-state buffer.When the enable output terminal of three-state buffer is effective, three-state buffer realizes normal logic and exports, and namely logical value is 0 or 1.When the enable output terminal of three-state buffer is invalid, the input end of three-state buffer can receive data, but output terminal is high-impedance state.
Code translator 2032 and by-pass switch array 2033, via rambus, obtain address and control signal from computing equipment 201.Code translator 2032 produces according to address and control signal and selects signal.
In one example, code translator 2032 produces according to the storer chip selection signal in address and control signal and selects signal.If storer chip selection signal is high level, then signal designation is selected to store operation.If storer chip selection signal is low level, then select the operation of signal designation expanding communication.
In another example, code translator 2032 produces according to the address signal in address and control signal and selects signal.Such as, address signal comprises address date and retains data.Presumptive address data are N position, such as 32, so using M position (such as 1) wherein as reservation position, can be used to indicate the action type that computing equipment 201 is expected.If reservation position is high level, then signal designation is selected to store operation.If reservation position is low level, then select the operation of signal designation expanding communication.
Selection signal is provided to data buffer 2031,2035 and 2037, by-pass switch array 2033, data-reusing module 2034 and subscriber bus controller 2036 by code translator 2032 respectively.
Data-reusing module 2034 comprises a multiplexer 2034a.According to selection signal, data buffer 2031 is connected with in data buffer 2035 and 2037 by multiplexer 2034a.Meanwhile, according to selection signal, one in data buffer 2031 and data buffer 2035 and 2037 is in strobe state, and another in data buffer 2035 and 2037 is in non-strobe state.
Therefore, device extension device 203, according to selection signal, provides the connection between computing equipment 201 and external memory storage 202, or provides the connection between computing equipment 201 and expanded function unit 204, thus realize routing function.
Further, if select signal designation to store operation, then by-pass switch array 2033 conducting, makes address and control signal directly be sent to external memory unit 202 via device extension device 203.In the rambus of device extension device 203 both sides, data-signal and address and control signal are full symmetrics.If select the operation of signal designation expanding communication, then by-pass switch array 2033 disconnects, and subscriber bus controller 2036 produces bus control signal according to selection signal.This expansion scheme can compatible existing rambus, thus need not carry out hardware modifications to computing equipment 201 and external memory storage 202.
Fig. 4 illustrates the schematic block diagram of the device extension device according to another embodiment of the present utility model.See Fig. 2, device extension device 203 is actually the route device on the rambus that is connected between computing equipment 201 and external memory storage 202.
Code translator 3032 and by-pass switch array 3033, via rambus, obtain address and control signal from computing equipment 201.Code translator 3032 produces according to address and control signal and selects signal.
Selection signal is provided to data buffer 3031,3035 and 3037, by-pass switch array 3033, data-reusing module 3034 and subscriber bus controller 3036 by code translator 3032 respectively.
Device extension device 304 according to this embodiment is with the difference of the device extension device 203 shown in Fig. 3: data-reusing module 3034 comprises three multiplexers 3034a, 3034b and 3034c.According to selection signal, data buffer 3031 is connected with in data buffer 3035 and 3037 with 3034c by three multiplexers 3034a, 3034b.Meanwhile, according to selection signal, at least two in data buffer 3031, data buffer 3035 and 3037 are in strobe state.
Therefore, device extension device 203 is according to selection signal, connection between computing equipment 201 and external memory storage 202 is provided, or the connection between computing equipment 201 and expanded function unit 204 is provided, or the connection between expanded function unit 204 and external memory storage 202 is provided, thus realizes routing function.
Further, if select signal designation to store operation, then by-pass switch array 3033 conducting, makes address and control signal directly be sent to external memory unit 202 via device extension device 203.In the rambus of device extension device 203 both sides, data-signal and address and control signal are full symmetrics.If select the operation of signal designation expanding communication, then by-pass switch array 3033 disconnects, and subscriber bus controller 3036 produces bus control signal according to selection signal.This expansion scheme can compatible existing rambus, thus need not carry out hardware modifications to computing equipment 201 and external memory storage 202.
Fig. 5 is the process flow diagram of the extended method of extendible computing system according to embodiment of the present utility model.Described extended method comprises:
In step sl, computing equipment transmits rambus signal via rambus to device extension device;
In step s 2, device extension device receives described rambus signal, and produces selection signal according to described rambus signal;
In step s3, described device extension device provides computing equipment, access path between outside expanded function unit and external memory storage according to described selection signal.
In the present embodiment, rambus signal comprises data-signal and address and control signal.
In a preferred embodiment, computing equipment is SOC (system on a chip) (SoC), and external memory storage is synchronous DRAM (SDRAM).Correspondingly, rambus is SDRAM bus.
Via rambus transmission of data signals and address and control signal between computing equipment and external memory storage.Correspondingly, rambus comprises address bus, data bus and control bus.Control bus is used for externally storer provides control signal, and address bus is used to specify the selected cell address in external memory storage.Data bus is two-way, for from the computing equipment data that externally memory transfer is to be written, or for transmitting the data read from external memory storage to computing equipment.
Via rambus and User Defined bus transfer data signal and address and control signal between computing equipment and expanded function unit, the code translator in device extension device produces according to the chip selection signal in address and control signal and/or address signal and selects signal.In one example, address signal comprises address date and retains data, and described reservation data instruction stores operation or expanding communication operation.
Described extended method provide in following access path one of at least: computing equipment directly accesses device extension device, outside expanded function unit directly accesses device extension device, computing equipment is via device extension device access external memory, outside expanded function unit is via device extension device access external memory, and computing equipment accesses outside expanded function unit via device extension device.Preferably, computing equipment extended method performs one or more operations following: computing equipment is via device extension device access external memory, computing equipment accesses outside expanded function unit via device extension device, and outside expanded function unit is via device extension device access external memory.
Described device extension device comprises: the first port, for being connected with the computing equipment of outside via rambus; Second port, for being connected with the storer of outside via rambus; 3rd port, for being connected with the expanded function unit of outside via User Defined bus; First data buffer, for the data-signal that buffer memory send via first end oral instructions; Second data buffer, for the data-signal that buffer memory transmits via the second port; 3rd data buffer, for the data-signal that buffer memory transmits via the 3rd port; Code translator, for according to the address sent via first end oral instructions and control signal, produces described selection signal; At least two data buffers in first to the 3rd data buffer, for according to selection signal, are connected by data-reusing module; And by-pass switch array, the second port, according to selection signal, is optionally delivered to from first end oral instructions in address and control signal by described by-pass switch array.
Described computing equipment comprises via device extension device access external memory: in read operation, computing equipment sends address and control signal to code translator and by-pass switch array, code translator carries out decoding to address and control signal, parsing the instruction that computing equipment sends is the read operation of computing equipment to external memory storage, by-pass switch array is opened, and address and control signal are delivered to external memory storage through by-pass switch array; External memory storage is according to after the address received and control signal, and the corresponding data signal of storer is supplied to the second data buffer, data-reusing model choice, the first data buffer successively, and computing equipment reads the data of the first data buffer buffer memory; In write operation, computing equipment sends address and control signal to code translator and by-pass switch array, code translator carries out decoding to address and control signal, parsing the instruction that computing equipment sends is the write operation of computing equipment to external memory storage, by-pass switch array is opened, and address and control signal are delivered to external memory storage through by-pass switch array; Computing equipment sends data-signal, data-signal is successively through the first data buffer, data-reusing module, the second data buffer, and the data of the second data buffer are written to storer appropriate address according to the address received and control signal by external memory storage.
Described computing equipment is accessed outside expanded function unit via device extension device and is comprised: in read operation, computing equipment sends address and control signal to code translator and by-pass switch array, code translator carries out decoding to address and control signal, parsing the instruction that computing equipment sends is the read operation of computing equipment to expanded function unit, by-pass switch array is closed, and address and control signal send address and control signal to expanded function unit by subscriber bus controller after decoder for decoding; Expanded function unit is according to connecing the address and control signal that subscriber bus controller sends, the corresponding data signal of expanded function unit is supplied to the 3rd data buffer, data-reusing model choice, the first data buffer successively, and computing equipment reads the data of the first data buffer buffer memory; In write operation, computing equipment sends address and control signal to code translator and by-pass switch array, code translator carries out decoding to address and control signal, parsing the instruction that computing equipment sends is the write operation of computing equipment to expanded function unit, by-pass switch array is closed, and address and control signal send address and control signal to expanded function unit by subscriber bus controller after decoder for decoding; Computing equipment sends data-signal, data-signal is successively through the first data buffer, data-reusing module, the 3rd data buffer, and the data of the 3rd data buffer are written to expanded function unit appropriate address by the address that expanded function unit sends according to subscriber bus controller and control signal.
Described outside expanded function unit comprises via device extension device access external memory: in read operation, computing equipment sends address and control signal to code translator and by-pass switch array, code translator carries out decoding to address and control signal, parsing the instruction that computing equipment sends is the read operation of expanded function unit to external memory storage, by-pass switch array is opened, and simultaneously address and control signal send address and control signal to expanded function unit by subscriber bus controller after decoder for decoding; External memory storage is according to after the address received and control signal, the corresponding data signal of storer is supplied to the second data buffer, data-reusing model choice, the 3rd data buffer successively, and expanded function unit reads the data of the 3rd data buffer buffer memory; In write operation, computing equipment sends address and control signal to code translator and by-pass switch array, code translator carries out decoding to address and control signal, parsing the instruction that computing equipment sends is the write operation of expanded function unit to external memory storage, by-pass switch array is opened, and simultaneously address and control signal send address and control signal to expanded function unit by subscriber bus controller after decoder for decoding; Data are supplied to the 3rd data buffer, data-reusing module, the second data buffer by the address that expanded function unit sends according to subscriber bus and control signal successively, thus by the data of expanded function unit write external memory storage appropriate address.
According to embodiment of the present utility model as described above, these embodiments do not have all details of detailed descriptionthe, do not limit the specific embodiment that this utility model is only described yet.Obviously, according to above description, can make many modifications and variations.This instructions is chosen and is specifically described these embodiments, is to explain principle of the present utility model and practical application better, thus makes art technician that the utility model and the amendment on the utility model basis can be utilized well to use.The scope that protection domain of the present utility model should define with the utility model claim is as the criterion.
Claims (13)
1. a device extension device, is characterized in that, comprising:
First port, for being connected with the computing equipment of outside via rambus;
Second port, for being connected with the storer of outside via rambus; And
3rd port, for being connected with the expanded function unit of outside via User Defined bus,
Wherein, described device extension device produces according to the rambus signal transmitted from computing equipment and selects signal, any one port in first to the 3rd port is connected with a port in all the other two ports in the first to the 3rd port, thus the routing function of rambus is provided, described rambus signal comprises data-signal and address and control signal.
2. device extension device according to claim 1, is characterized in that, also comprise:
First data buffer, for the data-signal that buffer memory send via first end oral instructions;
Second data buffer, for the data-signal that buffer memory transmits via the second port;
3rd data buffer, for the data-signal that buffer memory transmits via the 3rd port;
Code translator, for according to the address sent via first end oral instructions and control signal, produces described selection signal; And
At least two data buffers in first to the 3rd data buffer, for according to selection signal, are connected by data-reusing module.
3. device extension device according to claim 2, is characterized in that, data-reusing module comprises at least one multiplexer.
4. device extension device according to claim 2, is characterized in that, also comprises by-pass switch array, and the second port, according to selection signal, is optionally delivered to from first end oral instructions in address and control signal by described by-pass switch array.
5. device extension device according to claim 2, is characterized in that, at least two data buffer gatings in the first to the 3rd data buffer.
6. device extension device according to claim 2, is characterized in that, described code translator produces according to the chip selection signal in address and control signal and/or address signal and selects signal.
7. device extension device according to claim 6, is characterized in that, described address signal comprises address date and retains data, and described reservation data instruction stores operation or expanding communication operation.
8. an extendible computing system, is characterized in that, comprising:
Device extension device according to any one of claim 1 to 7;
Computing equipment, is connected with the first port of device extension device via rambus;
Storer, is connected with the second port of device extension device via rambus; And
Expanded function unit, is connected with the 3rd port of device extension device via User Defined bus.
9. computing system according to claim 8, is characterized in that, described computing equipment is be selected from the one in general processor and SOC (system on a chip).
10. computing system according to claim 8, is characterized in that, the function of described expanded function unit is configurable.
11. computing systems according to claim 10, is characterized in that, described expanded function unit is field programmable gate array.
12. computing systems according to claim 8, is characterized in that, the data-signal of described device extension device the first port and second port when storage operates and address and control signal are symmetrical.
13. computing systems according to claim 8, it is characterized in that, also comprise the mainboard with the first memory bank, first port of device extension device provides pin, for being connected with the first memory bank, the second port of device extension device provides the second memory bank, for being connected with storer, 3rd port of device extension device provides expansion interface, for being connected with expanded function unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520075699.8U CN204390227U (en) | 2015-02-03 | 2015-02-03 | Computing equipment expanding unit and extendible computing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520075699.8U CN204390227U (en) | 2015-02-03 | 2015-02-03 | Computing equipment expanding unit and extendible computing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204390227U true CN204390227U (en) | 2015-06-10 |
Family
ID=53362929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520075699.8U Expired - Fee Related CN204390227U (en) | 2015-02-03 | 2015-02-03 | Computing equipment expanding unit and extendible computing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204390227U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104598404A (en) * | 2015-02-03 | 2015-05-06 | 杭州士兰控股有限公司 | Computing equipment extending method and device as well as extensible computing system |
| CN106326168A (en) * | 2015-07-02 | 2017-01-11 | 纬创资通股份有限公司 | Connecting circuit and computer system with same |
| CN107301151A (en) * | 2017-07-28 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of mainboard and server |
| CN114328301A (en) * | 2021-12-22 | 2022-04-12 | 山东航天电子技术研究所 | Peripheral control method and system based on triple modular redundancy |
-
2015
- 2015-02-03 CN CN201520075699.8U patent/CN204390227U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104598404A (en) * | 2015-02-03 | 2015-05-06 | 杭州士兰控股有限公司 | Computing equipment extending method and device as well as extensible computing system |
| CN104598404B (en) * | 2015-02-03 | 2018-09-04 | 杭州士兰控股有限公司 | Computing device extended method and device and expansible computing system |
| CN106326168A (en) * | 2015-07-02 | 2017-01-11 | 纬创资通股份有限公司 | Connecting circuit and computer system with same |
| CN106326168B (en) * | 2015-07-02 | 2019-06-07 | 纬创资通股份有限公司 | Connecting circuit and computer system with same |
| CN107301151A (en) * | 2017-07-28 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of mainboard and server |
| CN107301151B (en) * | 2017-07-28 | 2020-07-21 | 苏州浪潮智能科技有限公司 | Mainboard and server |
| CN114328301A (en) * | 2021-12-22 | 2022-04-12 | 山东航天电子技术研究所 | Peripheral control method and system based on triple modular redundancy |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7680968B2 (en) | Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) | |
| CN104598405B (en) | Extended chip and expansible chip system and control method | |
| CN105335326A (en) | PCIE-SATA interface array device based on FPGA | |
| CN204390227U (en) | Computing equipment expanding unit and extendible computing system | |
| CN110781117A (en) | SPI expansion bus interface and system on chip based on FPGA | |
| CN101436171B (en) | Modular communication control system | |
| CN104598404A (en) | Computing equipment extending method and device as well as extensible computing system | |
| CN104657297A (en) | Computing equipment expanding system and expanding method | |
| KR20120038282A (en) | Bus system having id converter and coverting method thereof | |
| CN106844263B (en) | Configurable multiprocessor-based computer system and implementation method | |
| CN104598406A (en) | Expansion function unit and computing equipment expansion system and expansion method | |
| CN110765066B (en) | System on chip | |
| CN105677609A (en) | Bus structure of SoC system | |
| CN100557584C (en) | Be used for Memory Controller and method that network and storer are coupled | |
| CN204515761U (en) | SOC (system on a chip) | |
| CN106528462A (en) | Data readback device for high-capacity data recorder | |
| CN204496486U (en) | Expanded function unit and computing equipment expanding system | |
| US20190286606A1 (en) | Network-on-chip and computer system including the same | |
| CN204390228U (en) | Computing equipment expanding system | |
| CN109616149A (en) | A kind of eMMC host controller, eMMC control system and control method | |
| CN204496487U (en) | Extended chip and extendible chip system | |
| CN112835834B (en) | Data transmission system | |
| CN209249081U (en) | A kind of eMMC host controller and eMMC control system | |
| CN114168503A (en) | Interface IP core control method, interface IP core, device and medium | |
| CN106326172A (en) | APB bus slave interface expansion circuit and use method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150610 Termination date: 20210203 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |