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PCIE-SATA interface array device based on FPGA

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Publication number
CN105335326A
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CN
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Prior art keywords
interface
sata
pcie
fpga
array
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CN 201510652395
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Chinese (zh)
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王将
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广州慧睿思通信息科技有限公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F13/4072Drivers or receivers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002Serial port, e.g. RS232C
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024Peripheral component interconnect [PCI]

Abstract

The invention discloses a PCIE-SATA interface array device based on FPGA; the PCIE-SATA interface array device comprises a FPGA chip and a hard disk array; a PCIE interface, a SATA interface, and a DDR memory interface are logically realized in the FPGA chip; the FPGA chip and the outer side can carry out data exchange through the PCIE interface; the SATA interface is connected with the hard disk array so as to realize a first data buffer mode; the DDR memory interface is connected with a DDR memory so as to realize a second data buffer mode. The PCIE-SATA interface array device based on FPGA can realize PCIE interface-SATA interface conversion through the FPGA chip, and can realize SATA interface expansion functions.

Description

_种基于FPGA的PC IE转SATA接口阵列的装置 _ Species to SATA device interfaces based PC IE FPGA array of

技术领域 FIELD

[0001] 本发明涉及计算机总线接口转换领域,特别涉及一种基于FPGA的PCIE转SATA接口阵列的装置。 [0001] The present invention relates to a computer bus interface converters, and more particularly relates to apparatus based on FPGA PCIE SATA interface switch array.

背景技术 Background technique

[0002] 计算机网络技术迅猛发展,建立了多种多样的网络系统,带来了各种网络之间如何互连的问题,而且网络技术在不断发展,在进行标准化的同时产生了多样化,因此考虑异构网络的互连通信是不可避免的。 [0002] The rapid development of computer network technology, the establishment of a wide variety of network systems, brought the issue of how the various interconnection between networks, and network technology continues to develop, making standardization while producing a diverse, so consider a heterogeneous network of interconnected communication is inevitable. 在这个基础上提出了协议转换器。 On this basis, the proposed protocol converter.

[0003] 实际应用中许多设备采用的通信接口各不相同,由于各种通信结构的协议不兼容,使得异构网络之间的操作和信息交换难以进行。 [0003] In many practical applications using the communications interface devices vary, due to various communication protocols compatible structures, so that the operation and information exchange between heterogeneous networks is difficult. 常用的协议转换器只能完成点对点的转换,协议之间的相互转换、一对多的接口扩展也是一个研究热点。 Common protocol converter can only point to complete the conversion, protocol conversion between, many interface extension is a hot topic.

[0004] PCIE (Peripheral Component Interconnect Express)是新一代的总线接口。 [0004] PCIE (Peripheral Component Interconnect Express) is the next generation bus interface. 早在2001年的春季,英特尔公司就提出了要用新一代的技术取代PCI总线和多种芯片的内部连接,并称之为第三代I/O总线技术。 As early as the spring of 2001, Intel proposed the use of next-generation technology to replace the internal PCI bus connections and a variety of chips, and called the third generation I / O bus technology. 随后在2001年底,包括Intel、AMD、DELL、IBM在内的20多家业界主导公司开始起草新技术的规范,并在2002年完成,对其正式命名为PCIE。 Then at the end of 2001, including Intel, AMD, DELL, IBM, including more than 20 industry-leading companies to begin drafting a new code technology, and completed in 2002, its official name PCIE. 它采用了目前业内流行的点对点串行连接,比起PCI以及更早期的计算机总线的共享并行架构,PCIE每个设备都有自己的专用连接,不需要向整个总线请求带宽,而且可以把数据传输率提高到一个很高的频率,达到PCI所不能提供的高带宽。 It adopts the serial connection point of the popular industry, and compared to earlier shared PCI bus parallel architecture computer, the PCIE each device has its own dedicated connection, it does not need to request the entire bus bandwidth, but also the data transmission rate is raised to a very high frequency, to achieve high bandwidth PCI can not provide. PCIE总线技术在当今新一代的存储系统已经普遍的应用。 PCIE bus technology has been widely used in today's new generation of storage systems. PCIE总线能够提供极高的带宽,来满足系统的需求。 PCIE bus can provide very high bandwidth to meet system requirements. PCIE 3.0规范也已经确定,其编码数据速率,比同等情况下的PCIE 2.0规范提高了一倍,x32端口的双向速率高达32Gbps。 PCIE 3.0 specification has also been determined that the encoded data rate than doubling the PCIE 2.0 specification under the same circumstances, two-way x32 port rate up to 32Gbps.

[0005] SATA (Serial Advanced Technology Attachment)即串行高级技术附件。 [0005] SATA (Serial Advanced Technology Attachment), Serial Advanced Technology Attachment. 它是一种计算机总线,主要功能是用作主板和大量存储设备(如硬盘及光盘驱动器)之间的数据传输之用。 It is a computer bus, the main function is used in data transmission motherboard and mass storage devices (such as hard drives and CD-ROM) with between. 这是一种完全不同于并行PATA(Parallel Advanced Technology Attachment)的新型硬盘接口类型,由于采用串行方式传输数据而得名。 This is a completely different type of hard drive interface parallel PATA (Parallel Advanced Technology Attachment), since the serial transmission of data is named. SATA总线使用嵌入式时钟信号,具备了更强的纠错能力,与以往相比其最大的区别在于能对传输指令(不仅仅是数据)进行检查,如果发现错误会自动矫正,这在很大程度上提高了数据传输的可靠性。 SATA bus using the embedded clock signal, with a stronger error correction capability, the biggest difference is that compared with the conventional transfer instructions can be examined (not just data), an error is detected if the automatic correction, which greatly improve the reliability of data transmission extent. 串行接口还具有结构简单、支持热插拔的优点,目前,SATA分别有SATA 1.0速率为1.5Gbit/s、SATA2.0速率为3Gbit/s和SATA3.0速率为6Gbit/s三种规格。 Serial interface also has a simple structure, the advantages of hot-plug support, at present, SATA respectively SATA 1.0 rate of 1.5Gbit / s, SATA2.0 rate 3Gbit / s rate and SATA3.0 6Gbit / s three sizes. 未来将有更快速的SATA Express规格。 There'll be faster SATA Express specification.

发明内容 SUMMARY

[0006] 本发明的目的在于克服现有技术的缺点与不足,提供一种基于FPGA的PCIE转SATA接口阵列的装置。 [0006] The object of the present invention is to overcome the disadvantages and deficiencies of the prior art, there is provided an apparatus to SATA interfaces of the array-based PCIE FPGA.

[0007] 本发明的目的通过以下的技术方案实现: [0007] The object of the present invention is achieved by the following technical solution:

[0008] 一种基于FPGA的PCIE转SATA接口阵列的装置,包括FPGA芯片、硬盘阵列,其中FPGA芯片内部逻辑实现PCIE接口、SATA接口、DDR(DoubIe Data Rate)存储器接口,FPGA芯片通过PCIE接口与外部进行数据交互,通过SATA接口与硬盘阵列相连从而实现第一种数据缓存方式,通过DDR存储器接口与DDR存储器相连从而实现第二种数据缓存方式。 [0008] FPGA-based switch device PCIE SATA interface array including FPGA chip, disk array, wherein the FPGA chip internal logic implemented PCIE interface, a SATA interface, DDR (DoubIe Data Rate) memory interface, FPGA chip via interface PCIE external exchange data via the SATA interface is connected to the hard disk array data cache in order to achieve a first embodiment, the DDR memory interface to the DDR memory connected to the data cache in order to achieve the second embodiment.

[0009] 所述的FPGA芯片包括PCIE控制器、硬盘阵列控制器、接口转换控制器和DDR控制器,各个控制器通过内部互联自定义MBUS (Master Bus)总线连接。 [0009] PCIE the FPGA chip comprising a controller, a hard disk array controller, and the controller interface conversion DDR controller, each controller custom MBUS (Master Bus) connected by an internal bus interconnect.

[0010] 所述的PCIE控制器提供PCIE接口与外部进行数据交互,采用PCIE总线实现高速数据的传输,提供收发器、时钟同步、复位逻辑和标准的工业数据总线接口;PCIE总线支持xl、x2、x4、x8、xl6通道,具体根据所挂的SATA接口数量所需的带宽和所选的FPGA芯片支持的PCIE通道数决定。 [0010] PCIE controller provides the interface with external PCIE exchange data using high-speed data transmission PCIE bus, there is provided a transceiver, clock synchronization, and reset logic industry standard data bus interface; PCIE bus supports xl, x2 , x4, x8, xl6 channel, as determined according to the number of supported bandwidth FPGA chip and the selected required number of SATA interface linked to the PCIE channel. 每个PCIE通道的工作方式为全双工,传输速率最高可达128Gb/s,能达到系统对速率的要求。 PCIE how each channel is full duplex, the transmission rate up to 128Gb / s, can meet the system requirements for the rate. 根据收发器的动态配置功能,可以实现对PCIE 1.0、PCIE 2.0和PCIE 3.0协议的支持,提高系统的灵活性。 The dynamic configuration of the transceiver function, can implement support for PCIE 1.0, PCIE 2.0 PCIE 3.0 protocols and improve flexibility of the system.

[0011] 所述的硬盘阵列控制器由多个的SATA控制单元组成,一个SATA控制单元对应硬盘阵列的一个硬盘,SATA控制单元的SATA协议分四层实现:应用层(Applicat1n Layer)、传输层(Transport Layer)、链路层(Link Layer)和物理层(Physical Layer) ;SATA 控制单元支持SATA命令解析,包括对命令块寄存器的访问和控制,SATA接口根据硬盘接口的标准,速率自协商支持SATA1.0标准、SATA2.0标准和SATA3.0标准。 [0011] The SATA disk array controller by the control unit composed of a plurality of, SATA protocol control unit a SATA hard disk, SATA disk array control unit corresponding to the four sub-implemented: the application layer (Applicat1n Layer), the transport layer (Transport layer), the link layer (link layer) and a physical layer (physical layer); SATA support SATA command parsing control unit, comprising a block access command and control registers, hard disk interface SATA interfaces according to the standard, the rate of auto-negotiation support SATA1.0 standards, SATA2.0 and SATA3.0 standard criteria. 硬盘阵列控制器最多支持16个SATA接口,由于每个SATA接口的最大访问地址为48位,则最大的访问地址空间为52位,高4位用来表示16个硬盘空间,能实现海量的数据存储。 Disk array controller supports up to 16 SATA interface, since the maximum address of each access SATA interface is 48, the maximum access address space 52, the upper 4 bits used to represent the 16 disk space, vast amounts of data can be achieved storage. 阵列控制器的每个接口独立控制,以提高系统的工作效率。 Each interface independent control array controller, in order to improve the working efficiency of the system.

[0012] 所述的接口转换控制器外接MBUS接口实现与PCIE控制器、硬盘阵列控制器、DDR控制器之间的数据交互,内部实现PCIE侧的读写管理,并根据读写控制将数据读出和写入DDR存储器;由PCIE侧的读写命令,产生SATA的管理指令,从而实现SATA侧的读写管理,同时实现PCIE、SATA的地址管理和两个接口的地址映射功能。 [0012] The external interface switching controller MBUS interface PCIE and data exchange between a controller, a hard disk array controller, DDR controller, read and write the internal management PCIE side, and data is read in accordance with read-write control and writing the DDR memory; read and write commands from the PCIE side, generating management SATA commands to read and write management SATA side, while achieving address mapping function PCIE, SATA and two address management interfaces.

[0013] 所述的DDR控制器实现PCIE接口和SATA接口的数据缓存,DDR控制器采FPGA逻辑实现,模块引入ECC(Error Correcting Code)纠错机制。 [0013] DDR controller implements the interface and the data cache PCIE SATA interface, the DDR controller FPGA logic implementation adopted, the module is introduced ECC (Error Correcting Code) error correction mechanism. 纠错机制的引入能够提高DDR控制器的稳定性。 Introduction of the error correction mechanism can improve the stability of the DDR controller.

[0014] 本发明与现有技术相比,具有如下优点和有益效果: [0014] Compared with the prior art the present invention has the following advantages and benefits:

[0015] 本发明基于FPGA硬件控制技术可以实现同时对多个硬盘进行高速存取;基于SATA接口的磁盘阵列可实现数据的海量、高速存储;基于DDR的高速缓存管理可以充分保证采集数据的稳定可靠;高速PCIE接口技术可以很方便的实现与用户的直接物理对接。 [0015] The present invention is based on FPGA hardware control techniques may be implemented for simultaneously accessing a plurality of high-speed hard disk; based on the mass of data can be achieved SATA interface disk array, the cache; DDR-based cache management can fully guarantee the stability of the data collection reliable; PCIE interface high-speed technique can easily achieve the direct physical interface with the user. 本发明硬件集成度高,可靠性好。 The present invention is an integrated hardware and high reliability is good. 该方法具有实时性好、可靠性高的特点,可以实现PCIE接口对硬盘阵列的控制,方便用户对硬盘阵列的读写控制。 The method has good real-time, high reliability can be realized control of the disk array PCIE interface to facilitate the user to read and write to a disk array control.

附图说明 BRIEF DESCRIPTION

[0016] 图1为本发明所述的一种基于FPGA的PCIE转SATA接口阵列的装置的结构框图。 The present invention is a [0016] FIG. 1 is a block diagram SATA interface apparatus based PCIE FPGA array in turn.

[0017] 图2为图1所述装置的硬盘阵列控制器的逻辑组成框图。 Logic block diagram [0017] Figure 2 is the device of FIG. 1 is a hard disk array controller.

[0018] 图3为图1所述装置的PCIE控制器的逻辑组成框图。 [0018] FIG. 3 is a block diagram of the apparatus of FIG. 1 PCIE logic controller.

[0019] 图4为图1所述装置的自定义MBUS写接口的时序图。 A timing chart of the interface [0019] FIG. 4 is the apparatus of Figure 1 to write a custom MBUS.

[0020] 图5为图1所述装置的自定义MBUS读接口的时序图。 Timing diagram of read custom interface MBUS [0020] FIG. 5 is the device of Fig.

具体实施方式 detailed description

[0021] 下面结合实施例及附图对本发明作进一步详细的描述,但本发明的实施方式不限于此。 [0021] and the following description in conjunction with the accompanying drawings of the embodiments of the present invention will be further detailed embodiment, the embodiment of the present invention is not limited thereto.

[0022] 如图1,一种基于FPGA的PCIE转SATA接口阵列的装置,包括FPGA芯片、硬盘阵列,其中FPGA芯片内部逻辑实现PCIE接口、SATA接口、DDR(DoubIe Data Rate)存储器接口,FPGA芯片通过PCIE接口与外部进行数据交互,通过SATA接口与硬盘阵列相连从而实现第一种数据缓存方式,通过DDR存储器接口与DDR存储器相连从而实现第二种数据缓存方式。 [0022] As shown, FPGA-based switch device. 1 PCIE SATA interface array including FPGA chip, disk array, wherein the FPGA chip internal logic implemented PCIE interface, a SATA interface, DDR (DoubIe Data Rate) memory interface, FPGA chip PCIE exchanges data through an external interface, through the SATA interface and is connected to the hard disk array data cache in order to achieve a first embodiment, the DDR memory interface to the DDR memory connected to the data cache in order to achieve the second embodiment.

[0023] 如图1,所述的FPGA芯片包括PCIE控制器、硬盘阵列控制器、接口转换控制器和DDR控制器,各个控制器通过内部互联自定义MBUS (Master Bus)总线连接。 [0023] As shown in FIG 1, the PCIE FPGA chip comprising a controller, a hard disk array controller, and the controller interface conversion DDR controller, each controller custom MBUS (Master Bus) connected by an internal bus interconnect.

[0024] 为了方便数据接口的统一和实现高效的数据转输,内部互连总线采用了自定义的MBUS接口,时序图如图4、图5所示,为提高总线的带宽和提高传输效率,防止总线读写冲突,简化总线操作,MBUS总线采用了读写总线独立操作的方法,在进行写入操作时,由主端发出写请求信号,总线空闲时进行应答,并在此时总线读入请求的起始地址和数据长度,延时一拍后进行数据读入,Be信号为数据字节使能控制;进行读出操作时,主端发出读请求信号和请求的起始地址、数据长度,总线空闲和准备好数据后进行应答,延时一拍后总线传出数据。 [0024] In order to facilitate uniform data interface and efficient data transfusion, using the interconnection bus MBUS from the interface, defined in Figure 4 timing diagram, FIG. 5, to increase the bandwidth and improve the transmission efficiency of the bus, preventing bus read and write conflict simplified bus operation, a method of using the MBUS bus independent bus write operation, during a write operation issued by the master terminal responds to a write request signal, the bus is idle, and at that time the read bus start address and data length of the request, the delay data is read after a shot, be signal to enable control of data bytes; when a read operation, the master issues a read request signal requesting the start address and data length after the data bus is idle and ready to respond, after a delay beat outgoing data bus.

[0025] 所述的PCIE控制器提供PCIE接口与外部进行数据交互,采用PCIE总线实现高速数据的传输,提供收发器、时钟同步、复位逻辑和标准的工业数据总线接口;PCIE总线支持xl、x2、x4、x8、xl6通道,具体根据所挂的SATA接口数量所需的带宽和所选的FPGA芯片支持的PCIE通道数决定。 [0025] PCIE controller provides the interface with external PCIE exchange data using high-speed data transmission PCIE bus, there is provided a transceiver, clock synchronization, and reset logic industry standard data bus interface; PCIE bus supports xl, x2 , x4, x8, xl6 channel, as determined according to the number of supported bandwidth FPGA chip and the selected required number of SATA interface linked to the PCIE channel. 每个PCIE通道的工作方式为全双工,传输速率最高可达128Gb/s,能达到系统对速率的要求。 PCIE how each channel is full duplex, the transmission rate up to 128Gb / s, can meet the system requirements for the rate. 根据收发器的动态配置功能,可以实现对PCIE 1.0、PCIE 2.0和PCIE 3.0协议的支持,提高系统的灵活性。 The dynamic configuration of the transceiver function, can implement support for PCIE 1.0, PCIE 2.0 PCIE 3.0 protocols and improve flexibility of the system.

[0026] 在FPGA中构建PCIE (即PCI Express)控制器,如图3所示。 [0026] Construction of the PCIE (i.e., PCI Express) controller, shown in Figure 3 in the FPGA. 本实施例采用FPGA内部逻辑来设计实现PCI Express接口,能灵活配置收发器线速率来支持不同的PCIE接口标准,支持PCIE3.0协议,并能向下兼容;根据不同的速率带宽要求,可以通过配置选择需要的通道数,最多支持xl6通道,能极大地满足系统速率带宽要求。 This embodiment employs FPGA internal logic design implementation PCI Express interface, the transceiver can be flexibly configured to support different linear velocity PCIE interface standard, supports PCIE3.0 protocol, and to backward compatible; different rates according to bandwidth requirements, by configured to select a desired number of channels, channel supports up xl6, the rate can greatly satisfy the bandwidth requirements of the system. PCIE控制器外部接控制逻辑单元,用于实现PCIE的应用层管理、根据用户读写操作实现对MBUS总线的读写控制、实现与其它模块的信息交互等功能。 PCIE external controller to the control logic unit, an application layer for implementing management of PCIE, read and write control of the MBUS bus read and write operations according to a user, information exchange functions implemented with other modules.

[0027] 所述的硬盘阵列控制器由多个的SATA控制单元组成,一个SATA控制单元对应硬盘阵列的一个硬盘,SATA控制单元的SATA协议分四层实现:应用层(Applicat1n Layer)、传输层(Transport Layer)、链路层(Link Layer)和物理层(Physical Layer) ;SATA 控制单元支持SATA命令解析,包括对命令块寄存器的访问和控制,SATA接口根据硬盘接口的标准,速率自协商支持SATA1.0标准、SATA2.0标准和SATA3.0标准。 [0027] The SATA disk array controller by the control unit composed of a plurality of, SATA protocol control unit a SATA hard disk, SATA disk array control unit corresponding to the four sub-implemented: the application layer (Applicat1n Layer), the transport layer (Transport layer), the link layer (link layer) and a physical layer (physical layer); SATA support SATA command parsing control unit, comprising a block access command and control registers, hard disk interface SATA interfaces according to the standard, the rate of auto-negotiation support SATA1.0 standards, SATA2.0 and SATA3.0 standard criteria. 硬盘阵列控制器最多支持16个SATA接口,由于每个SATA接口的最大访问地址为48位,则最大的访问地址空间为52位,高4位用来表示16个硬盘空间,能实现海量的数据存储。 Disk array controller supports up to 16 SATA interface, since the maximum address of each access SATA interface is 48, the maximum access address space 52, the upper 4 bits used to represent the 16 disk space, vast amounts of data can be achieved storage. 阵列控制器的每个接口独立控制,以提高系统的工作效率。 Each interface independent control array controller, in order to improve the working efficiency of the system.

[0028] 在FPGA中构建硬盘阵列控制器,SATA协议支持到SATA3.0标准,能向下兼容,阵列最多可支持16个SATA接口,其单个SATA接口控制器框图,如附图2所示,SATA接口在高速收发器的基础上实现,时钟由外部150MHz晶振提供差分输入。 [0028] In the FPGA build the hard disk array controller, the SATA protocol supports SATA3.0 standard, downward compatibility can, the array can support up to 16 SATA interface, a SATA interface which is a block diagram of a single controller, as shown in Figure 2, SATA interface based on the realization of high-speed transceiver, a differential input clock by an external crystal 150MHz. SATA协议按应用层、传输层、链路层和物理层的四层结构实现,应用层负责所有SATA命令的解析,生成读写请求,并且可以读取和设置设备的工作性能模式,包括对控制命令模块寄存器的访问;传输层根据应用层的读写请求和来自数据链路层的应答启动数据包的传送,传输层在主机和硬盘设备之间以帧信息结构(FIS)的形式传输控制命令和数据;数据链路层通过维持数据的完整性来保证数据包可靠地传输,它包括数据的加扰和解扰,数据包的循环冗余校验(CRC32),并可在信号传送失败时自动重新尝试数据包的传送。 SATA protocol according to the application layer, transport layer, link layer and physical layer of the four-layer structure implemented, the application layer is responsible for parsing all SATA command generates read and write requests, and read performance mode and settings of the device, including control register access command module; read and write requests transmitted according to the transport layer and application layer data packet start response from the data link layer, a transport layer between the host and the hard disk device to the frame information structure (FIS) is transmitted as a control command and transactions; data link layer packets to ensure reliable transmission by maintaining the integrity of the data, which includes cyclic redundancy check data scrambling and descrambling, the data packet (the CRC32), and automatically when the transmission failure signal re-attempt to deliver the packet. 链路层发送和接收数据包,并发送来自于传输层的控制信号产生的原语字符,接收来自于物理层的原始字符并将其转化为控制信号发送给传输层;物理层包含两条高速单工通道的低压差分信号收发器,分别负责接收和发送数据。 Data link layer to send and receive packets, and transmits a control character from the primitive signal generated by the transport layer, receiving an original character from the physical layer and is converted to a control signal transmitted to the transport layer; high-speed physical layer contains two simplex channel low voltage differential signal transceiver to receive and transmit data, respectively. 物理层还包含了串行器/解串行器,8B/10B编解码,提供带外控制信号(OOB)进行上电时序控制和接口速率协商。 The physical layer further comprises a serializer / deserializer, 8B / 10B encoding and decoding, to provide a control signal band (the OOB) for timing control and power interface rate negotiation.

[0029] 所述的接口转换控制器外接MBUS接口实现与PCIE控制器、硬盘阵列控制器、、DDR控制器之间的数据交互,内部实现PCIE侧的读写管理,并根据读写控制将数据读出和写入DDR存储器;由PCIE侧的读写命令,产生SATA的管理指令,从而实现SATA侧的读写管理,同时实现PCIE、SATA的地址管理和两个接口的地址映射功能。 [0029] The external interface switching controller interface and MBUS PCIE controller, a hard disk array controller,, data exchange between the DDR controller, read and write the internal management PCIE side, and in accordance with the data write control DDR memory read and write; PCIE read and write commands from the side, generating management SATA commands to read and write management SATA side, while achieving address mapping function PCIE, SATA and two address management interfaces.

[0030] 所述的DDR控制器实现PCIE接口和SATA接口的数据缓存,DDR控制器采FPGA逻辑实现,模块引入ECC(Error Correcting Code)纠错机制。 [0030] DDR controller implements the interface and the data cache PCIE SATA interface, the DDR controller FPGA logic implementation adopted, the module is introduced ECC (Error Correcting Code) error correction mechanism. 纠错机制的引入能够提高DDR控制器的稳定性。 Introduction of the error correction mechanism can improve the stability of the DDR controller.

[0031] 对于DDR控制器,实现基于FPGA的DDR3的高速缓存控制器,考虑PCIE接口到SATA接口的速率匹配问题,以及硬盘这类的存储设备是基于突发性数据传输的特性,本实施例采用了DDR3作为高速缓存控制器,可以将DDR3存储器作为超大容量FIFO的来缓存数据流,把DDR3设计封装成一个具有异步FIFO功能的模块使用,完成两种接口的数据传输缓存。 [0031] For the DDR controller, FPGA-Based DDR3 cache controller, considering the PCIE interface SATA interface rate matching, and a hard disk storage device of this kind is based on characteristics of the burst data transfer, the present embodiment DDR3 employed as a cache controller may be a large-capacity FIFO DDR3 memory to cache data flow, the package designed as a DDR3 module having asynchronous FIFO function, data transfer is complete cache two interfaces.

[0032] 本发明基于单片FPGA芯片的信号处理平台,可实现通过PCIE接口对SATA硬盘进行高速读写。 [0032] The present invention is based on a single FPGA chip signal processing platform, enabling high-speed read and write through the PCIE interface SATA hard disk. 整个系统的功能采用硬件描述语言编写(例如=Verilog册1^、¥册1^等)。 Function of the system hardware description language (e.g., 1 ^ = Verilog Book, Volume 1 ^ ¥, etc.). 系统采用自顶向下的流程进行设计,集成度高。 The system uses a top-down design process, high integration. 整个系统可实现I〜16块硬盘阵列的控制,存储容量最高可达32TB,完成4GBytes DDR3缓存的管理,实现PCIE接口与SATA接口阵列的数据高速传输,用PCIE接口完成对SATA接口硬盘阵列的高速、海量读写。 The entire system can realize a disk array control I~16 block, a storage capacity of up to 32TB, complete 4GBytes DDR3 cache management, and high-speed data transmission interface SATA interface PCIE array, to complete a high-speed SATA interface for a disk array with PCIE interface , mass literacy.

[0033] 上述实施例为本发明较佳的实施方式,但本发明的实施方式并不受上述实施例的限制,其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化,均应为等效的置换方式,都包含在本发明的保护范围之内。 [0033] The preferred embodiment of the present invention embodiment, but the embodiment of the present invention is not limited to the above embodiments, changes made to any other without departing from the spirit and principle of the present invention, modifications, substitutions , combined, simplified, should be equivalent replacement method, it is included within the scope of the present invention.

Claims (6)

1.一种基于FPGA的PCIE转SATA接口阵列的装置,其特征在于:包括FPGA芯片、硬盘阵列,其中FPGA芯片内部逻辑实现PCIE接口、SATA接口、DDR存储器接口,FPGA芯片通过PCIE接口与外部进行数据交互,通过SATA接口与硬盘阵列相连从而实现第一种数据缓存方式,通过DDR存储器接口与DDR存储器相连从而实现第二种数据缓存方式。 An FPGA-based switch device PCIE SATA interface array, characterized by: a FPGA chip, disk array, wherein the FPGA chip internal logic implemented PCIE interface, a SATA interface, DDR memory interface, FPGA chip by an external interface PCIE data exchange, via the SATA interface is connected to the hard disk array data cache in order to achieve a first embodiment, the DDR memory interface to the DDR memory connected to the data cache in order to achieve the second embodiment.
2.根据权利要求1所述的基于FPGA的PCIE转SATA接口阵列的装置,其特征在于:所述的FPGA芯片包括PCIE控制器、硬盘阵列控制器、接口转换控制器和DDR控制器,各个控制器通过内部互联自定义MBUS总线连接。 The FPGA-based apparatus according to SATA interfaces. 1 PCIE array as claimed in claim, wherein: said controller FPGA chip comprising PCIE, a hard disk array controller, and the controller interface conversion DDR controller, each control custom network connected by an internal bus MBUS.
3.根据权利要求2所述的基于FPGA的PCIE转SATA接口阵列的装置,其特征在于:所述的PCIE控制器提供PCIE接口与外部进行数据交互,采用PCIE总线实现高速数据的传输,提供收发器、时钟同步、复位逻辑和标准的工业数据总线接口;PCIE总线支持xl、x2、x4、x8、xl6通道,具体根据所挂的SATA接口数量所需的带宽和所选的FPGA芯片支持的PCIE通道数决定。 The FPGA-based device of claim 2 PCIE SATA interface switch array as claimed in claim, wherein: the controller provides PCIE PCIE interface for data exchange with the outside, the PCIE bus using high-speed data transmission, there is provided a transceiver , clock synchronization, and reset logic industry standard data bus interface; PCIE bus supports xl, x2, x4, x8, xl6 channel, as per the required number of SATA interface linked to the FPGA chip and support the bandwidth of the selected PCIE channels decision.
4.根据权利要求2所述的基于FPGA的PCIE转SATA接口阵列的装置,其特征在于:所述的硬盘阵列控制器由多个的SATA控制单元组成,一个SATA控制单元对应硬盘阵列的一个硬盘,SATA控制单元的SATA协议分四层实现:应用层、传输层、链路层和物理层;SATA控制单元支持SATA命令解析,包括对命令块寄存器的访问和控制,SATA接口根据硬盘接口的标准,速率自协商支持SATA1.0标准、SATA2.0标准和SATA3.0标准。 4. PCIE to SATA device interfaces based on FPGA array, wherein said 2 wherein: said disk array controller of the plurality of SATA control units, a control unit corresponding to a SATA hard disk array of , SATA SATA protocol control unit to achieve four layers: the application layer, transport layer, link layer and physical layer; SATA support SATA command parsing control unit, comprising a block access command and control registers, hard disk interface SATA standard interface in accordance with the rate auto-negotiation support SATA1.0 standards, SATA2.0 and SATA3.0 standard criteria.
5.根据权利要求2所述的基于FPGA的PCIE转SATA接口阵列的装置,其特征在于:所述的接口转换控制器外接MBUS接口实现与PCIE控制器、硬盘阵列控制器、DDR控制器之间的数据交互,内部实现PCIE侧的读写管理,并根据读写控制将数据读出和写入DDR存储器;由PCIE侧的读写命令,产生SATA的管理指令,从而实现SATA侧的读写管理,同时实现PCIE、SATA的地址管理和两个接口的地址映射功能。 The FPGA-based device of claim 2 PCIE SATA interface switch array as claimed in claim, wherein: said external interface switching controller interface and MBUS PCIE controller, a hard disk array controller, DDR controller between data exchange, read and write the internal management PCIE side, and in accordance with the read and write control to write the DDR memory transactions; PCIE side by the read and write commands, the generation SATA management instructions to read and write the management-side SATA while achieving PCIE, SATA and address management address two interfaces mapping function.
6.根据权利要求2所述的基于FPGA的PCIE转SATA接口阵列的装置,其特征在于:所述的DDR控制器实现PCIE接口和SATA接口的数据缓存,DDR控制器采FPGA逻辑实现,模块引入ECC纠错机制。 FPGA-based apparatus according to claim 2 PCIE SATA interface switch array as claimed in claim, wherein: the data cache controller implements DDR PCIE and SATA interface, the DDR controller FPGA logic implementation adopted, the module is introduced ECC error correction mechanism.
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