KR101007269B1 - Digital radio frequency memory with phase dithering - Google Patents

Abstract

PURPOSE: A digital high frequency memory is provided to control a spurious wave component by applying a phase dithered pattern. CONSTITUTION: An A/D logic part(100) converts the radio frequency signal of a searching device into digital data. The A/D logic part transmits the digital data to a FPGA(Field Programmable Gate Array) memory. The D/A logic part(200) converts the data of the FPGA memory(300) into an analog signal. The FPGA memory generates a jamming digital signal by carrying disturbance data on the phase information of the A/D logic part. A phase dithered pattern generating part(400) supplies a predetermined phase dithered pattern code to the A/D logic part in order to control a spurious wave component.

Description

Digital Radio Frequency Memory with phase dithering

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital high frequency memory device using a phase shift technique, and to apply a phase shift pattern during A / D conversion and D / A conversion using phase information.

Jammers and Radars for Electronic Warfare (EA) Jammers and Electronic Radio-Counter CounterMeasure (ECCM) Digital Radio Frequency Memory (DRFM) used in beacon jammers for testing is a high-speed A / D converter (Analog). -Convert into digital signal by using Digital Converter, save it in memory, apply jamming to stored digital data, convert analog signal with high-speed D-A converter and radiate it with RF It is a key component that disrupts or neutralizes threat radars.

The A / D and D / A conversion methods mainly used in digital high frequency memory devices (DRFM) include a conversion method using amplitude information and a conversion method using phase information.

In the dual phase sampling (A / D) conversion method, when a high bit is used to improve the conversion performance of a digital signal (quantization noise suppression), a large amount of data is stored, thereby limiting a high sampling rate.

For this reason, a digital conversion method using phase information should select a high-speed A / D converter and a D / A converter that use low bits in consideration of the data capacity that can be stored and the small / light weight of hardware. Therefore, A / D converters and D / A converters with 3 to 4 bits of phase sampling that can reduce data storage capacity are mainly used.

However, if the low bit is used in A / D conversion, the memory limit can be overcome, but the quantization noise becomes large, and this quantization noise characteristic causes unwanted unwanted spurious signal components.

These unwanted components provide information that can distinguish whether a signal received from an enemy radar is a jamming signal (jamming signal) by a jammer or a correct signal reflected by a target. Therefore, the smaller the signal strength of the unwanted components included in the jamming signal, the better the jamming efficiency.

As described above, a method for solving a trade-off problem with respect to the storage memory capacity and the unwanted signal strength of the jamming signal generator is required.

An object of the present invention is to achieve high-speed phase sampling A / D conversion by performing A / D conversion using a low bit amount in a digital high frequency memory device (DRFM). In addition, by applying a phase shift pattern to minimize the unwanted signal strength of the disturbance signal, to improve the jamming efficiency. In addition, the applied phase blur pattern is removed before the RF radiation to remove the noise level caused by the phase blur pattern, thereby improving jamming efficiency.

An embodiment of the present invention provides a phase shift pattern generator for generating a phase shift pattern code having a phase shift, and generates a multiphase signal from the received RF signal and converts each of the square wave forms into digital data. An A / D logic unit for shifting a phase according to the phase shift pattern code, an FPGA memory for logic programming to store a disturbance signal in the phase information, and a digital disturbance signal from the FPGA memory It converts to an RF signal, and includes a D / A logic unit for restoring the phase shift applied by the A / D logic unit and converting the signal into an analog RF signal.

The phase shift pattern generator has a time delay until the A / D logic section passes through the FPGA memory and is input to the D / A logic section and converted into an analog RF signal, and then the phase applied by the A / D logic section. The vibration pattern is provided to the D / A logic unit.

The A / D logic unit comprises: a multiphase local oscillation generator for generating a plurality of multiphase signals from a baseband signal converted from an RF signal, and a number of the multiphase signals as a doubled number of phase shift signals. A phase shifter to convert the phase shift signal into digital data having a predetermined bit amount, and then shift the phase of the digital data according to the phase shift pattern code, and the A / D converter An encoder for encoding to reduce the bit amount of the digital data to be output, and a demux unit for converting the bit amount of the encoded digital data into the storage bit amount of each address of the FPGA memory, and then providing to the FPGA memory do.

The D / A logic unit includes a mux unit for converting the amount of data bits read from the address of the FPGA memory to the amount of data bits before conversion in the demux unit, and the original bit amount of the digital data output from the mux unit. A decoder for restoring the phase shift applied by the A / D logic unit in the decoding result, and a D / A converter for converting the digital data decoded and the phase shift pattern removed from the decoder into an analog RF signal. Frequency up-converting the output signal from the D / A converter into an I / Q frequency signal of I and Q orthogonal form and an RF signal for radio radiating the I / Q frequency signal. It includes an RF frequency converter.

According to an embodiment of the present invention, by using a small bit amount by using a phase sampling signal, it is possible to overcome the limitation of the amount of storage memory and achieve small size and light weight. In addition, the unwanted wave component can be suppressed by applying a phase blur pattern without adding bits to the unwanted wave characteristic due to the use of a small amount of bits. In addition, after applying the jamming signal, the noise level due to the phase shift pattern is removed, thereby improving the signal-to-noise ratio (SNR) of the received signal, thereby improving the jamming efficiency.

1 is a diagram illustrating a spectrum of phase information sampling.
2 is a diagram illustrating a spectrum of phase information sampling performed by applying a phase shift technique according to an exemplary embodiment of the present invention.
3 is a block diagram illustrating an operation of an A / D logic unit and a D / A logic unit in a digital high frequency memory device according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a state in which phase blur data is provided to an A / D converter and a state in which phase shake data is removed and restored to an input signal digital signal.
5 is a block diagram of a digital high frequency memory device according to an exemplary embodiment of the present invention.
6 is a phase shift diagram illustrating separation of four multiphase signals into eight signals according to an embodiment of the present invention.
7 is a diagram illustrating a state in which eight phase shifted signals are located in a complex frequency space according to an embodiment of the present invention.
8 is a diagram illustrating a state in which eight phase shifted signals are converted into 8-bit digital data according to an embodiment of the present invention.
9 is a diagram illustrating a state in a complex frequency space to which phase shift is applied according to an embodiment of the present invention.
10 is a diagram illustrating a phase shift pattern code according to an embodiment of the present invention.
FIG. 11 is a diagram illustrating an RF signal when and without an embodiment of the present invention. FIG.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

FIG. 1 is a diagram illustrating a spectral state in which phase information sampling is performed, and FIG. 2 is a diagram illustrating a spectral state in which phase information sampling is performed by applying a phase shift technique according to an embodiment of the present invention.

In general, the A / D conversion technique using phase information obtains phase information by sampling a signal at a predetermined interval, as shown in FIG. 1 (a). Similarly, unwanted components appear on the spectrum. Such a wave component is a pattern component sampled at regular intervals appears on the spectrum.

The unwanted wave component is a signal component that comes out of a predetermined band including unnecessary harmonics and low harmonics other than the desired frequency, and is used as information for identifying whether a signal received by the radar is a jamming signal (disturbed signal). The minimum unwanted component improves jamming efficiency.

In the embodiment of the present invention, in the A / D conversion using the phase information technique, a phase dithering technique is applied during the A / D conversion in order to suppress the unwanted wave components.

Referring to FIG. 2 to which the phase shift technique is applied according to an exemplary embodiment of the present invention, since each sampling interval is randomly shifted from side to side, since there is no constant interval, when the spectrum is shown as a spectrum, the unwanted component does not appear. Only the spectrum will appear.

In addition, a noise component appears as shown in FIG. 2 (b) due to the application of phase shift, and an embodiment of the present invention has a feature of removing the noise component when the signal is recovered by D / A conversion.

Hereinafter, embodiments of the present invention will be described in which a phase shift technique is applied to remove an unwanted component during A / D conversion, and to remove a noise level when performing D / A conversion.

3 is a block diagram illustrating A / D conversion and D / A conversion logic in a digital high frequency memory device according to an exemplary embodiment of the present invention.

The A / D logic unit 100 receives an RF signal transmitted from a search device such as a threat radar, converts the received RF signal into digital data, and transmits the received RF signal to a field programmable gate array (FPGA) memory. The RF signal is a signal which is converted into a baseband by an RF signal processing stage (not shown) and input to the D / A logic unit.

In the case of A / D conversion using a low number of bits in the A / D logic unit 100, the quantization noise becomes large due to the characteristics, and thus, an unwanted spurious signal component is included due to the quantization noise. Is applied to. Therefore, when the D / A logic unit 200 converts the data of the FPGA memory 300 into an analog signal and RF outputs, an unnecessary wave component is included.

Embodiment of the present invention by applying a phase dithering technique in the A / D logic unit 100 to suppress the unwanted components generated during A / D conversion using a small amount of phase information A / D conversion. To this end, the jamming signal generator includes a separate phase shake pattern generator 400 to minimize the unwanted components in the jamming signal.

The FPGA memory 300 is a memory programmed as a logic gate, and loads disturbing data on phase information input from the RF input processing A / D logic unit 100 to generate a jammed digital signal. The jammed digital signal is converted into an analog RF signal by the D / A logic unit 200 to radiate RF, thereby disturbing or disabling the threat radar.

The phase shift pattern generator 400 provides the A / D logic unit 100 with a predetermined phase shift pattern code for suppressing an undesired wave when converting into digital data through A / D conversion. The phase shift pattern code provided to the D logic unit 100 is provided to the D / A logic unit 200 after a predetermined time delay.

The D / A logic unit 200 receives a digital disturbance signal from the FPGA memory and converts it into an analog RF signal.At this time, the analog RF signal is removed after removing the noise component by removing the phase vibration pattern applied by the A / D logic unit. Convert to and output it.

The D / A logic unit 200 receives a phase blur pattern code applied to the A / D logic unit after a predetermined time delay, removes the applied phase shake pattern, and performs D / A conversion.

For reference, FIG. 2 schematically illustrates a state in which the phase shift pattern is provided to the A / D converter and a state in which the phase shift data is removed again and restored to the input signal digital signal. Referring to FIG. 4, it can be seen that the phase dithering factor k is applied to the same frequency as the fundamental frequency (ω ₀ ) of the RF input signal to provide positive (+) and negative (-) forms. have.

In front of the A / D converter, exp (ω ₀ t) is added to exp (ω ₀ k), which is a phase shift pattern, and becomes exp (ω ₀ (t + k)). In addition, the noise level can be restored as it is by removing the noise level while removing the unwanted components caused by the quantization noise.

Hereinafter, an operation of the A / D logic unit 100, the D / A logic unit 200, the phase blur pattern generator 400, and the FPGA memory 300 will be described in detail.

5 is a block diagram of a digital high frequency memory device (DRFM) to which a phase shift method is applied according to an embodiment of the present invention.

The A / D logic unit 100 includes a multiple-phase local oscillator generator 120, a low pass filter unit 130, a phase shifter 140, an A / D converter 150, and an encoder. 160, a demux 170, and a clock generator 180.

The multi-phase local oscillation generator 120 uses the local oscillator (LO) to convert the RF signal converted to the baseband into I (I 대역 0 °), I + 45 ° (I∠45 °), and Q ( Q∠0 °) and Q + 45 ° (Q∠45 °) to generate four multiphase signals that are phase shifted.

The low pass filter unit (LPF; Low Pass Filter) removes unnecessary signals by low pass filtering four phase shifted multiphase signals.

The phase shifter 140 splits the signal passing through the low pass filter into a double number, that is, eight signals. That is, I (I∠0 °), I + 22.5 ° (I∠22.5 °), I + 45 ° (I∠45 °), I + 67.5 ° (I∠67.5 °), Q (Q∠0 °) , Q + 22.5 ° (Q∠22.5 °), Q + 45 ° (Q∠45 °) and Q + 67.5 ° (Q∠67.5 °). For reference, a phase shift diagram for dividing four signals from four multiphase signals into eight signals is illustrated in FIG. 6, and a state in which eight phase shifted signals are located in a complex frequency space is illustrated in FIG. 7.

The A / D converter 150 converts the eight phase shifted signals into 8-bit digital signals through 16 steps of quantization. As shown in FIG. 6, the phase shifted signal at an interval of 22.5 ° is converted into 8-bit digital data through A / D conversion in the A / D converter 150 as shown in FIG. 8. If the phase of each sample is '+', it has a value of '1', and if it is '-', it has a value of '0' to have square wave digital data.

In addition, the A / D converter 150 suppresses unnecessary wave components by applying a phase shift pattern to the quantized square wave-shaped digital data to shift the phase. The phase shift will be described later together with the phase blur pattern generator 400 and FIGS. 9 and 10.

The encoder 160 converts the 8-bit data applied with the phase shift pattern provided from the A / D converter 150 into 4 bits and provides the demux. That is, an 8-to-4 encoder is provided to convert 8-bit data into 4 bits and provide the demux.

The demux 170 demuxes the encoded 4-bit digital signal to interoperate with the FPGA memory. 64 addresses are demuxed according to the amount of 4-bit data to the FPGA memory 300.

The clock generator 180 provides a high speed operation clock to the A / D converter 150, the encoder 160, and the demux 170. Because it handles a small bit amount, it is possible to work quickly. Therefore, a high-speed clock of 2.0GHz or more is generated and provided to each functional unit.

The phase shaking pattern generator 400 generates various phase shaking pattern codes as shown in FIGS. 10 (a), 10 (b) and 10 (c) in the phase shaking pattern source unit 410 and transmits them to the A / D logic unit 100. In addition, the phase shift pattern code provided to the A / D logic unit 100 with time delay is provided to the D / A logic unit 200.

The phase shift pattern code is a square wave form of a sampled bit size, and is provided as a code value in which, for example, eight sampling signals, a moving value of each sample is set. For example, when the phase shift pattern code is provided as a code combination value of '1' and '0', the values of '1' and '0' move each sample to a predetermined (+) phase value or Or a code value promised to shift to a negative phase value.

For example, when the phase shift pattern code provided in the eight sampling signals has a '10010110' code value as shown in FIG. 10 (a), the A / D converter selects the first sample S1 to which '1' is applied. Move the second sample (S2) with '0' applied to have a phase shifted by + 2.5 ° from the current phase, and move the third sample (S3) with '0' applied to it. Shift to have a phase shifted -2.5 ° from the current phase. The remaining five samples are each phase shifted in turn according to the corresponding code value. Thus, as shown in FIG. 9, each of the samples is shifted from the phase of FIG. 7 to the positive or negative phase.

As a result, when the eight square wave-shaped digital data shown in FIG. 8 are shaken to the left or the right by applying the phase shake pattern to each other, the phase shake effect appears in the encoding process of the encoder. Since the phase noise characteristic appears as a jitter on the time axis, if the square wave waveform is shaken from side to side in every sample by applying an arbitrary pattern (phase shaking pattern), the unwanted wave is suppressed.

On the other hand, the phase blur pattern code generated by the phase blur pattern source unit 410 is randomly generated, and various codes may be generated by a random algorithm. For example, a phase noise pattern code may be generated using a pseudo noise code. In addition, various generation methods may be applied such that the phase shift pattern source unit has a uniform distribution such that the number of '1' and '0' of the phase shift pattern code combination is the same.

As described above, when the phase shift pattern is applied to suppress the unwanted wave and provided to the FPGA memory 300, the FPGA memory 300 programs through a logic gate combination that applies a disturbance signal (jamming signal) to the input data. .

The D / A logic unit 200 converts a digital jamming signal from the FPGA memory 300 into an analog signal and outputs the analog signal.

The D / A logic unit 200 performs the function of the A / D logic unit in reverse. For this purpose, the mux unit, the decoder, the D / A converter, the low pass filter unit, the I / Q converter, and the RF frequency converter are performed. Contains wealth.

The mux 250 performs muxing for data interworking with the FPGA memory. For example, the mux 250 may include a 16: 1 mux.

The D / A converter 230 converts phase information in a data form into an analog signal through inverse quantization, and the low pass filter 220 performs low pass filtering.

The I / Q converter 210 converts an I / Q frequency signal of I and Q orthogonal form, the RF frequency converter up-converts the frequency as an RF signal for radiating, and the clock generator 260 operates at high speed. Generate a clock of 2.56GHz for

The decoder 240 decodes 4 bits of data from the FPGA memory 300 to 8 bits, and reduces the noise level due to the application of the phase shift pattern by removing the phase shift pattern applied by the A / D converter from the decoded result. Let's do it.

When the decoder 240 of the D / A logic unit decodes 4 bits of disturbance data obtained from the FPGA memory 300 into 8 bits, subtracting the added phase blur pattern by considering the delay time, thereby adding a phase blur pattern. Can reduce the noise level.

For example, when the phase shake pattern code of '10010110' shown in FIG. 10 (a) is applied in the A / D logic unit, the same phase shake pattern code of '10010110' is received from the phase shake pattern generator 400. To remove the applied pattern. At this time, in contrast to that applied in the A / D logic unit, in the case of '1', the phase shift is negative and in the case of '0', the phase shift is positive.

On the other hand, since the decoder 240 of the D / A logic unit must remove each phase shift pattern added by the A / D logic unit, the decoder 240 removes the delayed phase with time delay. That is, after A / D conversion by applying phase shift, the encoder has a time delay while passing through an encoder, a 1:16 demux part, a programming time in an FPGA memory, and a 16: 1 mux part.

To this end, the phase shift pattern generator 400 includes a time delay unit 420 to delay the phase shift pattern for a predetermined time by design and provide the phase shift pattern to the decoder 240.

FIG. 11 is a diagram illustrating an RF signal when and without an embodiment of the present invention. FIG.

Fig. 11A is a signal input to the A / D converter. FIG. 11 (b) is a case where demodulation is performed by applying a disturbance signal after applying A / D conversion and applying a disturbance signal and performing D / A conversion, and then demodulating the RF signal. It can be seen that a lot of unwanted components, which are signal components coming out of the band, are generated.

FIG. 11 (c) shows that when the phase shift technique is applied, the unwanted wave component is removed, but the noise level is increased to about 30 dB in the range of -70 dB to -40 dB.

FIG. 11 (d) is a diagram illustrating characteristics when the phase shift technique is applied according to an embodiment of the present invention and when the phase shift technique is applied with an improved phase shift technique for removing phase noise components. Also, it can be seen that the range is reduced to about 20db in the range of -70dB to -50dB.

Although the invention has been described with reference to the accompanying drawings and the preferred embodiments described above, the invention is not limited thereto, but is defined by the claims that follow. Accordingly, one of ordinary skill in the art may variously modify and modify the present invention without departing from the spirit of the following claims.

100: A / D logic section 110: baseband signal conversion section
120: multi-phase local oscillation generation unit 130: low pass filter unit
140: phase shifter 150: A / D converter
160: encoder 170: demux unit
180: clock generator 200: D / A logic unit
300: FPGA memory 400: phase oscillation pattern generator

Claims (9)

A phase jitter pattern generator for generating a phase jitter pattern code to have a phase shift;
An A / D logic unit which generates a multiphase signal from the received RF signal and converts the digital phase into digital data, and shifts the phase of the digital data according to the phase blur pattern code;
An FPGA memory for logically programming and storing a disturbance signal in the phase information; And
Receives a digital disturbance signal from the FPGA memory and converts it into an analog RF signal, and includes a D / A logic unit for converting and outputting an analog RF signal after restoring the phase shift applied by the A / D logic unit.
The A / D logic unit,
A multiphase local oscillation generator for generating a plurality of multiphase signals from baseband signals converted from RF signals;
A phase shifter for separating the number of the multiphase signals as a phase shift signal of twice the number;
An A / D converter for converting the phase shift signal into digital data having a predetermined bit amount and shifting the phase of the digital data according to the phase blur pattern code;
An encoder for performing encoding to reduce the amount of bits of digital data output from the A / D converter; And
A demux unit for converting the bit amount of the encoded digital data into the storage bit amount of each address of the FPGA memory and then providing the bit amount to the FPGA memory.
Digital high frequency memory device using a phase shift method comprising a. The digital high frequency memory device according to claim 1, wherein the phase shift is performed by applying a phase shifting technique for randomly shifting a positive (+) phase shift or a negative (-) phase for each digital data of the multiphase signal. The digital high frequency memory device according to claim 1, wherein the phase shift pattern code is generated by using a predetermined pseudo noise code. The method of claim 2, wherein the phase shift pattern generator has a time delay until the A / D logic unit passes through the FPGA memory and is input to the D / A logic unit and converted into an analog RF signal. And a phase shift pattern code applied to a logic unit to provide the D / A logic unit. delete The method according to claim 1, The A / D logic unit,
Low pass section for low pass filtering the multi-phase signal output from the multi-phase local oscillation generator for the phase shifter
Digital high frequency memory device applying a phase shake method further comprising. The phase generator according to claim 1 or 6, wherein the multiphase local oscillation generator generates four multiphase signals of I 로 0 °, I∠45 °, Q∠0 °, and Q∠45 ° from the received RF signal. Digital high frequency memory device using vibration technique. The method of claim 6, wherein the phase shifter, the four multi-phase signals I∠0 °, I∠22.5 °, I∠45 °, I∠67.5 °, Q∠0 °, Q∠22.5 °, Q∠45 Digital high frequency memory device using phase dimming method that separates into 8 °, Q∠67.5 ° signal and provides it to A / D converter. The method according to claim 1, wherein the D / A logic unit,
A mux unit for converting the amount of data bits read from the address of the FPGA memory to the amount of data bits before conversion in the demux unit;
A decoder which decodes the digital data output from the mux unit to the original bit amount, and restores the phase shift applied by the A / D logic unit in a decoding result;
A D / A converter for converting the digital data decoded and phase shift pattern removed by the decoder into an analog RF signal;
An I / Q converter converting the output signal from the D / A converter into an I / Q frequency signal of I and Q orthogonal forms;
RF frequency converter for up-converting the frequency as an RF signal for wirelessly radiating the I / Q frequency signal
Digital high frequency memory device using a phase shift method comprising a.

Images