CN102147447A - Method for controlling data transparent transfer as well as flexible label connection method and device thereof - Google Patents
Method for controlling data transparent transfer as well as flexible label connection method and device thereof Download PDFInfo
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Abstract
The embodiment of the invention discloses a method for controlling data transparent transfer as well as a flexible label connection method and a device thereof, which can be used for controlling the field transparent transfer of the data output by each module for processing data in an FPGA (field programmable gate array). The interface mode between modules is flexible label connection. The method comprises the following steps: generating a corresponding data label for each module; packaging data input into the FPGA with the data label; controlling the direction for each module to output data by changing the content of the data label carried by each output module when data are output; and finishing the transparent transfer of output data between modules. The embodiment of the invention solves the technical problem of the transparent transfer of output data between modules in the FPGA under the conditions that extra internal chip resources and an internal memory are not occupied and the original time sequence of the internal signal is not changed.
Description
Technical field
The present invention relates to the electronic design technology field, particularly a kind of method of control data transparent transmission, flexible label method of attachment and device thereof.
Background technology
Increasing rapidly of the scale of field programmable logic device (FPGA) and integration density can be realized increasing system or subsystem function in FPGA, FPGA has become the first-selected solution of more and more complication systems.
In the commissioning test process of large-scale F PGA chip, the state indication of interworking of the hardware and software of the key that betides FPGA inside is in a large number arranged, must be by the specific output pin output of FPGA, the state and the correctness of the operation of indication FPGA built-in function.
But, because the single FPGA area of chip is limited, available pin sum can not increase with the raising of integrated level synchronously, therefore be specifically designed to the pin number wretched insufficiency of monitoring FPGA internal operation state, therefore, how effectively and all sidedly to observe and monitor difficult point and the key point that FPGA internal operation state becomes FPGA debugging.
At present, measure FPGA internal state method and have two kinds:
A kind ofly be, the tested node in inside is linked external terminal, be connected to the respective channel of outside logic analyser again by the logic analysis probe, the logic analysis passage is named according to the pin positions and the title of measured signal.But this measuring method can only realize 1 pair 1 connection and measurement; And each FPGA debugging pin can only corresponding internal signal node; In addition,, change new measured node, must redistribute pin, recompilate design document, not only waste time and energy but also can change original sequential of signal thus because internal signal node fixes.
Another kind is, utilizes the kernel that is used for on-chip debug of the commercial version that FPGA manufacturer provides, and this kernel adopts JTAG as communication interface, and this kernel uses the internal resource of FPGA, can read any signal of FPGA internal logic online, in real time.Its ultimate principle is to utilize untapped Block Ram among the FPGA, the signal (register or netting twine) that needs are observed is deposited among these Block Ram in real time, then, select data to read according to the specific address decoding of trigger condition generation that the user sets, and the data of reading are delivered to the JTAG mouth, and then, the computing machine that is connected with this JTAG mouth, can be according to the Data Dynamic ground timing waveform that draws of TAG mouth output, so that people's analysis.But the timing waveform that this measuring method obtains is not the timing waveform of True Data, but satisfies the timing waveform of storing data when setting trigger condition in the storer, can only regularly provide state analysis for the user, can not provide state analysis for the user in real time; In addition, debugging kernel itself has taken chip internal resource and inner storer, and is bigger if the FPGA design takies resource, the debugging kernel will with design contention for resources own, influence the development and Design of FPGA; If remove this kernel after debugging, the FPGA design needs to recompilate, and will change the sequential of internal circuit this moment.
Summary of the invention
In order to solve the problems of the technologies described above, the embodiment of the invention provides a kind of method, flexible label method of attachment and device thereof of control data transparent transmission, additionally do not taking chip internal resource and internal storage to solve, and do not change under the preceding situation of the original sequential of internal signal, finish the technical matters of the transparent transmission of inner each the intermodule output data of FPGA.
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of method of control data transparent transmission, be used to control the transparent transmission that field programmable logic device FPGA inside is used for each module output data of data processing, described method comprises: the interface mode that described each intermodule is set is the interface mode that flexible label connects; Described method also comprises:
For each module generates corresponding data label;
The data and the described data label that are input to FPGA inside are packaged together;
The content of carrying described data label when changing each module output data is controlled the direction of described each module output data, finishes the transparent transmission of intermodule output data.
Preferably, described data label for each module generation correspondence comprises:
Control module in the described programmable logic device (PLD) FPGA generates corresponding data label for each module; Perhaps
The outer computing machine of described programmable logic device (PLD) FPGA generates corresponding data label for each module.
Preferably, described data label comprises: frame effectively identifies, transparent transmission is handled sign and session field number.
Preferably, the described interface mode that described each intermodule is set is that the interface mode that flexible label connects specifically comprises:
For the input interface of each module is provided with tag decoder, output interface is provided with code tag, and according to the form output data of the flexible label of setting.
Preferably, described method also comprises:
In the time need testing to the output data of each module, generate the label substance of this module output data of transparent transmission, and control this module is added described label in the output after the processing content, so that the output data of this module, is convenient to test to the FPGA test interface.
Accordingly, the embodiment of the invention also provides a kind of flexible label method of attachment, is applied to the connection that field programmable logic device FPGA inside is used for each intermodule of data processing, and described method comprises:
Reception is input to the data of FPGA inside, and described data are the data of encapsulation of data label;
Described data are carried out decapsulation, and the data after the decapsulation are carried out respective handling;
Receive and change the label substance that described module output data flows to;
Described label substance is added in the data label of described processing back output data;
Encapsulate according to the interface mode of the flexible label of the setting output data after to described interpolation label substance, and the data after will encapsulate output to the module of described label substance sensing.
Preferably, described interface mode according to the flexible label of setting is:
Export outside data layout to according to FPGA and set the interface mode that the flexible label of inner each intermodule of FPGA connects.
Preferably, described method also comprises: the data way of output of described each intermodule of control is the way of output of first in first out.
Accordingly, the embodiment of the invention provides a kind of device of control data transparent transmission, is used to control the transparent transmission that field programmable logic device FPGA inside is used for each module output data of data processing, and described device comprises
The unit is set, and the interface mode that is used to be provided with described each intermodule is the interface mode that flexible label connects;
The data label generation unit is used to each module to generate corresponding data label;
Encapsulation unit, the data and the described data label that are used for being input to FPGA inside are packaged together;
Control module is used for the content of carrying described data label when changing each module output data, controls the direction of described each module output data, finishes the transparent transmission of intermodule output data.
Preferably, also comprise:
The label substance generation unit is used for generating the label substance of this module output data of transparent transmission in the time need testing the output data of a module of described each module;
Described control module also is used to control this module is added described label in the output after the processing content, so that the output data of this module, is convenient to test to the FPGA test interface.
The embodiment of the invention also provides a kind of flexible label coupling arrangement, is applied to the connection that field programmable logic device FPGA inside is used for each intermodule of data processing, and described device comprises:
First receiving element is used to receive the data that are input to FPGA inside, and described data are the data of encapsulation of data label;
Decapsulation unit is used for described data are carried out decapsulation;
Processing unit is used for the data after the described decapsulation unit decapsulation are carried out respective handling;
Second receiving element is used to receive the label substance that changes the described module output data flow direction;
Adding device is used for adding described label substance to the described data label of handling the back output data;
Encapsulation unit is used for interface mode according to the flexible label of the setting output data after to described interpolation label substance and encapsulates;
Transmitting element is used for the data after the described encapsulation unit encapsulation are outputed to the module that described label substance points to.
Preferably, also comprise:
The first in first out module is used for the connection between described each module, and according to the data of each resume module of order buffer memory of first in first out.
By such scheme as can be seen, be earlier the corresponding data label of each module generation of FPGA inside; The data and the described data label that will be input to FPGA inside again are packaged together, and the content of carrying described data label when changing each module output data is controlled the direction of described each module output data, finishes the transparent transmission of intermodule output data.Realized the state of each functional module of FPGA content is tested, this technical scheme under the situation that the technology of flexibly connecting and data tag technology combine, is finished the intermodular data transparent transmission and to the test of any functional module of FPGA inside with module.Realized additionally not taking chip internal resource and internal storage, do not changed under the original sequential prerequisite of internal signal, reached flexible, efficient test the FPGA inner function module.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The process flow diagram of the method for a kind of control data transparent transmission that Fig. 1 provides for the embodiment of the invention;
The synoptic diagram of the module of the FPGA content that Fig. 2 provides for the embodiment of the invention;
The process flow diagram of a kind of flexible label method of attachment that Fig. 3 provides for the embodiment of the invention;
The structural representation of the device of a kind of control data transparent transmission that Fig. 4 provides for the embodiment of the invention;
The structural representation of a kind of flexible label coupling arrangement that Fig. 5 provides for the embodiment of the invention;
The structural representation of the Speaker Identification FPGA built-in function that Fig. 6 provides for the embodiment of the invention;
FPGA inner structure synoptic diagram behind the interpolation FIFO that Fig. 7 provides for the embodiment of the invention;
The structural representation that Fig. 8 tests for the FPGA internal signal that the embodiment of the invention provides;
The structural representation of the FPGA data penetration transmission that Fig. 9 provides for the embodiment of the invention.
Embodiment
In the embodiment of the invention, the interface mode that connects based on flexible label is set between the FPGA inner function module earlier; Secondly, according to unified rule,, finish flexibly connecting of each intermodule for each functional module is provided with corresponding data label; At last, when needs are tested certain module, by changing the content of the corresponding data label of this module, make the output data of this module directly be sent to the FPGA test interface, finish test, that is to say, module under the situation that the technology of flexibly connecting and data tag technology combine, is finished the intermodular data transparent transmission and to the test of any functional module of FPGA inside.This implementation procedure is not additionally taking chip internal resource and internal storage, does not change under the original sequential prerequisite of internal signal, can test flexibly each functional module of FPGA inside.
In embodiments of the present invention, the transparent transmission technology of intermodular data is meant that former notebook data will be through transferring to next module after the processing of a certain module again, takes certain control technology to make data see through a certain module now and does not add to handle and transfer to next module.
Data label is meant additional one section excessive data section between originally continuous data segment, to indicate the attribute of this segment data.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the embodiment of the invention is described in detail below in conjunction with accompanying drawing.
See also Fig. 1, it is the process flow diagram of the method for a kind of control data transparent transmission provided by the invention, and this method is used to control the transparent transmission that field programmable logic device FPGA inside is used for each module output data of data processing, and described method comprises step:
Step 101: the interface mode that described each intermodule is set is the interface mode that flexible label connects; This step is optional mode, after being provided with, and follow-up can directly the use.
A kind of mode is: on the input interface for each module tag decoder is set, output interface is provided with code tag, and the form output data that connects according to the flexible label of setting.Wherein, the structural drawing that the increase flexible label connects between each functional module of former FPGA inside as shown in Figure 2.In the present embodiment, the functional module in the FPGA is an example with 3 modules, and promptly module 1.Module 2 and module 3.
As shown in Figure 2, each functional module outbound course is provided with encoding function, thereby can unify according to the flexible label form output data of setting; The module input interface of each function is provided with decoding function, the flexible label data layout that can decode and set.
Step 102: for described each module generates corresponding data label; That is to say, according to unified rule, for described each module generates corresponding data label.Wherein, described data label can be the data label of some bits, can comprise: frame effectively identifies, transparent transmission is handled sign and session field number, can also comprise reserved field etc.
A kind of embodiment that generates corresponding data label is to generate corresponding data label for each module by the control module of described programmable logic device (PLD) FPGA inside;
The another kind of embodiment that generates corresponding data label is: can generate corresponding data label for each module by the computing machine of described programmable logic device (PLD) FPGA outside.
Certainly, also can generate corresponding data label for each module, but be not limited to this by operating personnel.
Step 103: the data and the described data label that will be input to FPGA inside are packaged together;
Such as, described data label is the data label of some bits, can be with the plurality of data encapsulation, and encapsulation process can externally be carried out, and also can carry out in inside by the control module of FPGA inside.
Suppose, the data (D) of former input FPGA inside are: D1, D2, D3 ..., Dn ..., behind the encapsulation of data label (F) be: F1, D1, D2 ..., Di, F2, Di+1, Di+2 ..., Dj, F3, Dj+1, Dj+2 ..., Dk ....When being not limited to this.
Step 104: the content of carrying described data label when changing each module output data, control the direction of described each module output data, finish the transparent transmission of intermodule output data.
By changing the entrained data label content of each module output data, can control the direction of the output data of inner each module of FPGA flexibly, realize flexibly connecting of FPGA internal module; Such as, it is 3 bits that label (F) length is set, the first bit respective modules, 1, the second bit respective modules, 2, the three bit respective modules 3, and corresponding bit position these module normal process data of bit representation, this module transparent data is represented in zero clearing.Suppose that the F1 content is ' 111 ', representation module 1, module 2, module 3 be the normal process data successively; Suppose that the F2 content is ' 010 ', representation module 1, module 3 transparent data, module 2 normal process data; Suppose that the F3 content is ' 011 ', representation module 1 transparent data, module 2, module 3 normal process data; So, can finish intermodule and flexibly connect by data label (F) content is set.
Preferably, described method can also comprise: in the time need testing the output data of each module, generate the label substance of this module output data of transparent transmission, and control this module is added described label in the output after the processing content, so that the output data of this module, is convenient to test to the FPGA test interface.
That is to say, in the time need testing to certain module of FPGA inside, its corresponding data label only need be set, and (this belongs to the test data generation, can be rewritten by the outer computer software control or be write by the staff wage reform according to tag format, is perhaps finished by internal control module.) make this module output data directly deliver to the FPGA test interface, thereby additionally do not taking under the prerequisite of FPGA internal resource, realize conveniently test.As shown in Figure 2, suppose that the F2 content is ' 010 ', representation module 1, module 3 transparent data, module 2 normal process data can realize the direct transparent transmission of data to module 2, directly transparent transmission output then so can direct easily test module 2.
Also see also Fig. 3, the process flow diagram of a kind of flexible label method of attachment that provides for the embodiment of the invention is applied to the connection that field programmable logic device FPGA inside is used for each intermodule of data processing, and described method comprises:
Step 301: receive the data that are input to FPGA inside, described data are the data of encapsulation of data label;
Step 302: described data are carried out decapsulation, and the data after the decapsulation are carried out respective handling;
Step 303: receive the label substance that changes the described module output data flow direction;
Step 304: described label substance is added in the data label of described processing back output data;
Step 305: encapsulate according to the interface mode of the flexible label of the setting output data after to described interpolation label substance, and the data after will encapsulate output to the module of described label substance sensing.
Wherein, described interface mode according to the flexible label of setting is: export outside data layout to according to FPGA and set the interface mode that the flexible label of inner each intermodule of FPGA connects.
Preferably, described method can also comprise: the data way of output of described each intermodule of control is the way of output of first in first out.
The embodiment of the invention provides a kind of method and flexible label method of attachment of control data transparent transmission, can realize the transparent transmission of the output data of field programmable logic device FPGA internal module, and each state of each module output data is tested.This method is not additionally taking chip internal resource and internal storage, does not change under the original sequential prerequisite of internal signal, can carry out transparent transmission, test to each functional module of FPGA inside.That is to say that the embodiment of the invention is by intermodular data transparent transmission technology, finishes flexibly connecting of module, and the combination tag technology, reach flexible, efficient test the FPGA inner function module.
Implementation procedure based on said method, the device of a kind of control data transparent transmission that the embodiment of the invention provides, its structural representation sees Fig. 4 for details, and this device is used to control the transparent transmission that field programmable logic device FPGA inside is used for each module output data of data processing, comprising: unit 41 is set, data label generation unit 42, encapsulation unit 43 and control module 44, wherein
The described unit 41 that is provided with, the interface mode that is used to be provided with described each intermodule are the interface mode that flexible label connects; After the interface mode of each intermodule is provided with, follow-up direct use.Described data label generation unit 42 is used to each module to generate corresponding data label; Described encapsulation unit 43, the data and the described data label that are used for being input to FPGA inside are packaged together; Described control module 44 is used for the content of carrying described data label when changing each module output data, controls the direction of described each module output data, finishes the transparent transmission of intermodule output data.
Preferably, described device can also comprise: the label substance generation unit is used for generating the label substance of this module output data of transparent transmission in the time need testing the output data of a module of described each module; Described control module also is used to control this module is added described label in the output after the processing content, so that the output data of this module, is convenient to test to the FPGA test interface.
Also see also Fig. 5, the structural representation of a kind of flexible label coupling arrangement that provides for the embodiment of the invention, described device is applied to the connection that field programmable logic device FPGA inside is used for each intermodule of data processing, comprising: first receiving element 51, decapsulation unit 52, processing unit 53, second receiving element 54, adding device 55, encapsulation unit 56 and transmitting element 57, wherein
Described first receiving element 51 is used to receive the data that are input to FPGA inside, and described data are the data of encapsulation of data label; Described decapsulation unit 52 is used for described data are carried out decapsulation; Described processing unit 53 is used for the data after the described decapsulation unit decapsulation are carried out respective handling; Described second receiving element 54 is used to receive the label substance that changes the described module output data flow direction; Described adding device 55 is used for adding described label substance to the described data label of handling the back output data; Described encapsulation unit 56 is used for interface mode according to the flexible label of the setting output data after to described interpolation label substance and encapsulates; Described transmitting element 57 is used for the data after the described encapsulation unit encapsulation are outputed to the module that described label substance points to.
Preferably, described device can also comprise: the first in first out module, be used for the connection between described each module, and according to the data of each resume module of order buffer memory of first in first out.
In the embodiment of the invention, export the interface mode that outside data layout determines that the flexible label between inner each submodule of FPGA connects to according to FPGA earlier, then to sending into the data of FPGA inside, encapsulate according to described interface mode, after data enter into the module of FPGA inside, according to each module deblocking is carried out in the requirement of data, after the internal module processing finishes, control module generates the content of corresponding data label, and the corresponding module of the control content of adding this data label, according to described interface mode the data of adding the data label content are encapsulated again, deliver to corresponding module, finish different functions according to the difference of label substance.
Further, when the state of each module of FPGA inside is tested, according to testing requirement, by the data label (can realize by software or hardware etc.) that each module is set, need the data of the module of test to export the test interface of FPGA to control, test.
For the ease of those skilled in the art's understanding, illustrate with FPGA design example below in conjunction with voice (being the speaker) recognizer.
In Speaker Identification algorithm calculating process, after speech data frame entered FPGA inside, through exporting the result after five resume module such as pre-service, power spectrum computation, mel wave filter, logarithm operation and discrete cosine transform, its functional block diagram was seen accompanying drawing 6.
Discrete cosine transform output result's form is 1*32Bit speech channel label+12*32Bit MFCC supplemental characteristic, and the standard interface between inner each functional module of FPGA transmits with the form of 32 buses.For data cached when the inside modules deal with data, can between each functional module, add corresponding FIFO.FPGA inner structure behind the interpolation FIFO is seen accompanying drawing 7.
To sending into the voice data of Speaker Identification FPGA inside, the at first speech channel that is distributed according to this road speech number, and the sequence number of the frame that marks off produce the data label of 32 bits by control module for it, also can generate other data label, present embodiment is to be example with 32.The structure of its data label is as shown in table 1.
Table 1
Wherein, the coded format of this data label is as follows:
Bit31:En_Flag (frame effectively identifies)-' 1 ' valid frame; ' 0 ' invalid frame;
Bit30-24: transparent transmission is handled sign
0000001 carries out pretreatment module, other modules of transparent transmission;
0000010 carries out power spectrum module, other modules of transparent transmission;
0000100 carries out mel bank of filters, other modules of transparent transmission;
0001000 carries out logarithm operation unit, other modules of transparent transmission;
0010000 carries out discrete cosine transform unit, other modules of transparent transmission;
0011111 carries out whole modules.
Bit23-20: keep 2 fields, be defaulted as complete zero;
Bit19-0:Channel_Flag (speech channel field)-can identify the 1M speech channel;
When each resume module, can judge whether current data wants transparent transmission according to data label.For example, want the result of measured power spectrum module whether correct, can Bit30-24 in its data label be rewritten as ' 0000011 ' by control module, the input data will by with the processing of processing module and power spectrum module after, the output result will send by exporting FIFO.This moment, the built-in function of FPGA changed to shown in the accompanying drawing 8, and wherein each functional module in the slash square frame all is in the transparent transmission state.
Equally, based on label with flexibly connect technology, also can realize data penetration transmission between the functional module by label is set.Do not need in the current application to suppose mel bank of filters module, the label in the time of then only power spectrum need being exported is made as ' 0011011 ', and the output result of power spectrum will directly enter the logarithm operation unit.At this moment, the inner function module of Speaker Identification FPGA connects as accompanying drawing 9.
By the foregoing description as can be known, the purpose of the embodiment of the invention is to provide a kind of method, flexible label method of attachment and device thereof of control data transparent transmission, realization is tested the state of each functional module of FPGA content, this technical scheme under the situation that the technology of flexibly connecting and data tag technology combine, is finished the intermodular data transparent transmission and to the test of any functional module of FPGA inside with module.Realized additionally not taking chip internal resource and internal storage, do not changed under the original sequential prerequisite of internal signal, reached flexible, efficient test the FPGA inner function module.
Need to prove, one of ordinary skill in the art will appreciate that all or part of flow process that realizes in the foregoing description method, be to instruct relevant hardware to finish by computer program, described program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, described storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
More than the manner of execution and the device of a kind of response message provided by the present invention is described in detail, used specific embodiment herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. the method for a control data transparent transmission, be used to control the transparent transmission that field programmable logic device FPGA inside is used for each module output data of data processing, it is characterized in that the interface mode that described each intermodule is set is the interface mode that flexible label connects; Described method:
For each module generates corresponding data label;
The data and the described data label that are input to FPGA inside are packaged together;
The content of carrying described data label when changing each module output data is controlled the direction of described each module output data, finishes the transparent transmission of intermodule output data.
2. method according to claim 1 is characterized in that, described data label for each module generation correspondence comprises:
Control module in the described programmable logic device (PLD) FPGA generates corresponding data label for each module; Perhaps
The outer computing machine of described programmable logic device (PLD) FPGA generates corresponding data label for each module.
3. method according to claim 1 is characterized in that, described data label comprises: frame effectively identifies, transparent transmission is handled sign and session field number.
4. method according to claim 1 is characterized in that, the described interface mode that described each intermodule is set is that the interface mode that flexible label connects specifically comprises:
For the input interface of each module is provided with tag decoder, output interface is provided with code tag, and according to the form output data of the flexible label of setting.
5. method according to claim 1 is characterized in that, described method also comprises:
In the time need testing to the output data of each module, generate the label substance of this module output data of transparent transmission, and control this module is added described label in the output after the processing content, so that the output data of this module, is convenient to test to the FPGA test interface.
6. flexible label method of attachment is applied to the connection that field programmable logic device FPGA inside is used for each intermodule of data processing, it is characterized in that, comprising:
Reception is input to the data of FPGA inside, and described data are the data of encapsulation of data label;
Described data are carried out decapsulation, and the data after the decapsulation are carried out respective handling;
Receive and change the label substance that described module output data flows to;
Described label substance is added in the data label of described processing back output data;
Encapsulate according to the interface mode of the flexible label of the setting output data after to described interpolation label substance, and the data after will encapsulate output to the module of described label substance sensing.
7. method according to claim 6 is characterized in that, described interface mode according to the flexible label of setting is:
Export outside data layout to according to FPGA and set the interface mode that the flexible label of inner each intermodule of FPGA connects.
8. according to claim 6 or 7 described methods, it is characterized in that described method also comprises: the data way of output of described each intermodule of control is the way of output of first in first out.
9. the device of a control data transparent transmission is used to control the transparent transmission that field programmable logic device FPGA inside is used for each module output data of data processing, it is characterized in that, comprises
The unit is set, and the interface mode that is used to be provided with described each intermodule is the interface mode that flexible label connects;
The data label generation unit is used to each module to generate corresponding data label;
Encapsulation unit, the data and the described data label that are used for being input to FPGA inside are packaged together;
Control module is used for the content of carrying described data label when changing each module output data, controls the direction of described each module output data, finishes the transparent transmission of intermodule output data.
10. device according to claim 9 is characterized in that, also comprises:
The label substance generation unit is used for generating the label substance of this module output data of transparent transmission in the time need testing the output data of a module of described each module;
Described control module also is used to control this module is added described label in the output after the processing content, so that the output data of this module, is convenient to test to the FPGA test interface.
11. a flexible label coupling arrangement is applied to the connection that field programmable logic device FPGA inside is used for each intermodule of data processing, it is characterized in that, comprising:
First receiving element is used to receive the data that are input to FPGA inside, and described data are the data of encapsulation of data label;
Decapsulation unit is used for described data are carried out decapsulation;
Processing unit is used for the data after the described decapsulation unit decapsulation are carried out respective handling;
Second receiving element is used to receive the label substance that changes the described module output data flow direction;
Adding device is used for adding described label substance to the described data label of handling the back output data;
Encapsulation unit is used for interface mode according to the flexible label of the setting output data after to described interpolation label substance and encapsulates;
Transmitting element is used for the data after the described encapsulation unit encapsulation are outputed to the module that described label substance points to.
12. device according to claim 11 is characterized in that, also comprises:
The first in first out module is used for the connection between described each module, and according to the data of each resume module of order buffer memory of first in first out.
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| CN104639455A (en) * | 2015-02-16 | 2015-05-20 | 杭州华三通信技术有限公司 | Netstream processing method and device |
| CN104639455B (en) * | 2015-02-16 | 2018-02-09 | 新华三技术有限公司 | A kind of network flow treating method and apparatus |
| CN111314184A (en) * | 2018-12-12 | 2020-06-19 | 深圳市云海物联科技有限公司 | Control method and system based on transparent transmission mechanism |
| CN111314184B (en) * | 2018-12-12 | 2021-10-15 | 深圳市云海物联科技有限公司 | Control method and system based on transparent transmission mechanism |
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| CN102147447B (en) | 2013-06-05 |
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