CN109408445A - A kind of graphics processor board - Google Patents
A kind of graphics processor board Download PDFInfo
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- CN109408445A CN109408445A CN201811293216.6A CN201811293216A CN109408445A CN 109408445 A CN109408445 A CN 109408445A CN 201811293216 A CN201811293216 A CN 201811293216A CN 109408445 A CN109408445 A CN 109408445A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a kind of graphics processor boards, it include: multiple graphics processor units, it is two interconnected by high-speed bus two between multiple graphics processor units, multiple graphics processor units and the central processing unit composition heterogeneous processing system being set to outside graphics processor board；Field programmable gate array is signally attached to multiple graphics processor units by control, for carrying out logic control to multiple graphics processor units according to control signal；Connector is connected to multiple graphics processor units and field programmable gate array by PCIE bus, for making multiple graphics processor units and field programmable gate array signal and mainboard carry out signal transmission.Technical solution of the present invention can carry out effective and efficient management control work for different GPU or different types of GPU, improve board signal monitoring effect and efficiency, enhancing using flexible and scalability.
Description
Technical field
The present invention relates to computer fields, and more specifically, more particularly to a kind of graphics processor board.
Background technique
With stepping up for computation complexity, the not simple only CPU or GPU of the processing system that server uses,
GPU (graphics processor) is towards AI (artificial intelligence) now with CPU (central processing unit) the heterogeneous processing system framework combined
The mainstream framework of server.Two kinds of processors have his own strong points, and intensive processing task gives GPU, and complicated logical operation is given
CPU, collaborative work can be with the arithmetic speed of lifting system.Under the drive of AI process demand, heterogeneous system is more and more common, GPU
Market demand further expansion.
Embodiment in the prior art is that BMC (baseboard controller) and CPLD (complex programmable are integrated using cpu motherboard
Logical device)/FPGA (field programmable gate array) mould group, GPU board introduces system as component, after system integration solidification
The monitoring management signal of GPU board derives from and the management board of mainboard BMC and CPLD/FPGA or additional.This reality
Flexibility and the scalability for applying mode are poor；And a part of logic control signal is not easy to directly control by mainboard, and this increases
The difficulty of system administration is added.
For in the prior art by the effect of mainboard monitoring GPU board signal is poor, flexibility and scalability is low asks for shortage
Topic, there has been no effective solution schemes at present.
Summary of the invention
In view of this, the purpose of the embodiment of the present invention is to propose a kind of graphics processor board, different GPU can be directed to
Or different types of GPU controls work to carry out effective and efficient management, improves board signal monitoring effect and efficiency, enhancing
Using flexible and scalability.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of graphics processor board, comprising:
Multiple graphics processor units, it is two interconnected by high-speed bus two between multiple graphics processor units, it is more
A graphics processor unit and the central processing unit composition heterogeneous processing system being set to outside graphics processor board；
Field programmable gate array is signally attached to multiple graphics processor units by control, for being believed according to control
Number to multiple graphics processor units carry out logic control；
Connector is connected to multiple graphics processor units and field programmable gate array by PCIE bus, for making
Multiple graphics processor units and field programmable gate array signal and mainboard carry out signal transmission.
In some embodiments, logic control includes at least one of: upper and lower electric control, enabled, reset, alarm letter
Number management.
In some embodiments, also total by I2C between multiple graphics processor units and field programmable gate array
Line connection, field programmable gate array by the connection of I2C bus read multiple graphics processor units device version information and
Current Temperatures；Field programmable gate array also passes through I2C bus and is connected to the power supply being similarly provided on graphics processor board
Management module, board temperature sensor and board memory, be respectively used to read graphics processor board power consumption information, when
Preceding operating temperature and board firmware information.
In some embodiments, field programmable gate array, which also passes through I2C bus and is connected to, is set to graphics processor
At least one of is transferred to baseboard controller by the baseboard controller outside board, field programmable gate array: multiple figures
The device version information and Current Temperatures of processor unit, the power consumption information of graphics processor board, current operating temperature and plate
Holding firmware information.
In some embodiments, field programmable gate array also passes through control and is signally attached to mainboard, and mainboard passes through control
Signal processed makes field programmable gate array carry out logic control to multiple graphics processor units；Field programmable gate array is also logical
The power management module that control is signally attached to be similarly provided on graphics processor board is crossed, field programmable gate array passes through
It controls the output of signal control power supply management module and enables.
In some embodiments, board further includes graphics processor clock, logical between multiple graphics processor units
Courier uses graphics processor clock as reference clock；Multiple graphics processor units and field programmable gate array also pass through
PCIE bus is connected to the mainboard clock being set to outside graphics processor board, and multiple graphics processor units and scene can compile
Communication between journey gate array and mainboard uses mainboard clock as reference clock.
In some embodiments, board further includes the debugging interface for being connected to field programmable gate array, debugging interface
For being emulated to field programmable gate array, and configuration, programming firmware.
In some embodiments, board further includes the serial port chip for being connected to field programmable gate array, serial port chip
Firmware for being loaded to storage field programmable gate array when powering on and/or resetting.
The another aspect of the embodiment of the present invention additionally provides a kind of server, comprising:
The mainboard of central processing unit is installed；
Above-mentioned graphics processor board, graphics processor board are integrally plugged on mainboard and are connected by PCIE bus
To central processing unit.
The another aspect of the embodiment of the present invention additionally provides a kind of graphic processing method, comprising the following steps:
Receive the control signal from mainboard；
Logic control is carried out to multiple graphics processor units using above-mentioned graphics processor board according to control signal；
Mainboard is fed back by connector.
The present invention have following advantageous effects: graphics processor board provided in an embodiment of the present invention, pass through by
FPGA and GPU are integrated on same board, so that local FPGA can be with direct monitoring GPU without passing through mainboard and CPU
Technical solution, effective and efficient management control work can be carried out for different GPU or different types of GPU, is improved
Board signal monitoring effect and efficiency, enhancing using flexible and scalability.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other embodiments are obtained according to these attached drawings.
Fig. 1 is the architecture logic schematic diagram of graphics processor board provided by the invention；
Fig. 2 is the detailed block diagram of graphics processor board provided by the invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
It should be noted that all statements for using " first " and " second " are for differentiation two in the embodiment of the present invention
The non-equal entity of a same names or non-equal parameter, it is seen that " first ", " second " do not answer only for the convenience of statement
It is interpreted as the restriction to the embodiment of the present invention, subsequent embodiment no longer illustrates this one by one.
Based on above-mentioned purpose, the first aspect of the embodiment of the present invention, different GPU or difference can be directed to by proposing one kind
The GPU of type come carry out it is effective and it is efficient management control work board embodiment.Shown in fig. 1 is provided by the invention
The structural schematic diagram of the embodiment of graphics processor board.
The graphics processor board includes:
Multiple graphics processor units 11 are mutually interconnected by high-speed bus two-by-two between multiple graphics processor units 11
It connects, multiple graphics processor units 11 and the central processing unit composition isomery processing system being set to outside graphics processor board
System；
Field programmable gate array 12 is signally attached to multiple graphics processor units 11 by control, for according to control
Signal processed carries out logic control to multiple graphics processor units 11；
Connector 13 is connected to multiple graphics processor units 11 and field programmable gate array 12 by PCIE bus,
For making multiple graphics processor units 11 and 12 signal of field programmable gate array and mainboard carry out signal transmission.
The various example modules in conjunction with described in disclosure herein may be implemented as electronic hardware, computer software or
The combination of the two.In order to clearly demonstrate this interchangeability of hardware and software, with regard to the function of various exemplary modules
General description has been carried out to it.This function be implemented as software be also implemented as hardware depending on concrete application with
And it is applied to the design constraint of whole system.Those skilled in the art can realize in various ways for every kind of concrete application
The function, but this realization decision should not be interpreted as causing a departure from range disclosed by the embodiments of the present invention.
In some embodiments, field programmable gate array 12 is according to control signal to multiple graphics processor units 11
The logic control of progress includes at least one of: upper and lower electric control, enabled, reset, alarm signal management.
In some embodiments, also pass through between multiple graphics processor units 11 and field programmable gate array 12
The connection of I2C bus, field programmable gate array 12 read the equipment version of multiple graphics processor units 11 by the connection of I2C bus
This information and Current Temperatures；Field programmable gate array 12 is also connected to by I2C bus and is similarly provided at graphics processor plate
Power management module, board temperature sensor and board memory on card are respectively used to read the function of graphics processor board
Consume information, current operating temperature and board firmware information.
In some embodiments, field programmable gate array 12 is also connected to by I2C bus and is set to graphics process
At least one of is transferred to baseboard controller by the baseboard controller outside device board, field programmable gate array 12: multiple
The device version information and Current Temperatures of graphics processor unit 11, the power consumption information of graphics processor board, work at present temperature
Degree and board firmware information.
In some embodiments, field programmable gate array 12 is also signally attached to mainboard by control, and mainboard passes through
Control signal makes field programmable gate array 12 carry out logic control to multiple graphics processor units 11；Field-programmable gate array
Column 12 are also signally attached to the power management module being similarly provided on graphics processor board, field programmable gate by control
Array 12 is by controlling the output of signal control power supply management module and enabling.
The various example modules in conjunction with described in disclosure herein can use be designed to execute it is described here
The following component of function is realized or is executed: general processor, digital signal processor (DSP), specific integrated circuit (ASIC),
Field programmable gate array 12 or other programmable logic device, discrete gate or transistor logic, discrete hardware component or
Any combination of these components.General processor can be microprocessor, but alternatively, processor can be any tradition
Processor, controller, microcontroller or state machine.Processor also may be implemented as calculate equipment combination, for example, DSP and
Combination, multi-microprocessor, one or more microprocessors combination DSP and/or any other this configuration of microprocessor.
In some embodiments, board further includes graphics processor clock, between multiple graphics processor units 11
Communication uses graphics processor clock as reference clock；Multiple graphics processor units 11 and field programmable gate array 12 are also
It is connected to the mainboard clock being set to outside graphics processor board by PCIE bus, multiple graphics processor units 11 and existing
Communication between field programmable gate array 12 and mainboard uses mainboard clock as reference clock.
In some embodiments, board further includes the debugging interface for being connected to field programmable gate array 12, and debugging connects
Mouth is used to emulate field programmable gate array 12, and configuration, programming firmware.
In some embodiments, board further includes the serial port chip for being connected to field programmable gate array 12, serial ports core
Piece is used for the firmware loaded to storage field programmable gate array 12 when powering on and/or resetting.
It is to be understood that computer readable storage medium (such as various memories) as described herein can be volatibility
Memory or nonvolatile memory, or may include both volatile memory and nonvolatile memory.As an example
And not restrictive, nonvolatile memory may include read-only memory (ROM), programming ROM (PROM), electrically programmable
ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory.Volatile memory may include arbitrary access
Memory (RAM), the RAM can serve as external cache.As an example and not restrictive, RAM can be with more
Kind form obtains, such as synchronous random access memory (DRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate SDRAM
(DDR SDRAM), enhancing SDRAM (ESDRAM), synchronization link DRAM (SLDRAM) and directly Rambus RAM (DRRAM).
The storage equipment of disclosed aspect is intended to the memory of including but not limited to these and other suitable type.
Below according to Fig. 2 shows specific embodiment carry out the embodiment that the present invention is further explained.As shown in Fig. 2, making
Parallel computation module is formed with tetra- GPU units of GPU0/GPU1/GPU2/GPU3, it is internal to be interconnected by high speed interconnection,
It is interconnected by PCIe x16 and mainboard CPU or PCIe switch.GPU unit connects reference clock 1 (mainboard clock buffer) and makees
For PCIe reference clock.Clock generator generates reference clock 3 as in GPU mould group when the system reference of high speed interconnection
Clock.
FPGA is interconnected by PCIe x1 and mainboard CPU or PCIe switch.Mainboard realizes the pipe to FPGA by PCIe
Reason and control, and realize FPGA firmware upgrade functionality.(with the reference clock 1 identical or different mainboard of FPGA connection reference clock 2
Clock buffer) it is used as PCIe reference clock.
FPGA is interconnected by control signal group 1 with the CPLD/FPGA on mainboard.Mainboard is realized by control signal group 1
FPGA is enabled, is resetted, hot plug is enabled and resets operation.FPGA is realized by control signal group 2 to 12V HSC mould
Block, 5V power module are enabled and output controls.FPGA realizes the logic control to GPU, including power-on and power-off by control signal group 3
Control, enabled and reset, alarm signal management etc., this can simplify the management of mainboard BMC and CPLD/FPGA module.
FPGA module is also responsible for realizing extension I2C management and control signal.Wherein, FPGA is passed by I2C_1 and temperature
Sensor 0 interconnects, for reading 0 monitoring temperature of temperature sensor；FPGA is interconnected by I2C_1 and 12HSC and 12V_STBY HSC,
For monitoring power consumption；FPGA is interconnected by I2C_1 and EEPROM, for reading board information and firmware information.FPGA passes through
I2C_2 and temperature sensor 1 interconnect, for reading 1 monitoring temperature of temperature sensor.Wherein temperature sensor 0 is used for detection plate
Card air outlet temperature, temperature sensor 1 stick into draught temperature for detection plate.When board temperature generates exception, temperature sensing
Device module can generate alarm signal and notify FPGA.FPGA is interconnected by I2C_3 and GPU0/GPU1/GPU2/GPU3, for reading
Take GPU device version information and GPU temperature.Finally, FPGA is connected to BMC through I2C repeater, connector 13 by I2C_0,
BMC knows the above various data by reading FPGA internal register.
The management rate-determining steps in conjunction with described in disclosure herein can be directly contained in hardware, by processor execution
In software module or in combination of the two.Software module may reside within RAM memory, flash memory, ROM memory,
Eprom memory, eeprom memory, register, hard disk, removable disk, any other shape of CD-ROM or known in the art
In the storage medium of formula.Illustrative storage medium is coupled to processor, enables a processor to read from the storage medium
Win the confidence breath or to the storage medium be written information.In an alternative, the storage medium can be integral to the processor
Together.Pocessor and storage media may reside in ASIC.ASIC may reside in user terminal.In an alternative
In, it is resident in the user terminal that pocessor and storage media can be used as discrete assembly.
Debugging and development interface of JTAG (JTAG) module as FPGA module can be used, connect by this
Mouth may be implemented to FPGA module in-circuit emulation, configuration firmware programming SPI FLASH etc..SPI FLASH (serial port chip) is used as
FPGA firmware is stored, firmware can have been loaded from FLASH loading firmware, FPGA when FPGA is powered on or is resetted and realized relevant configuration.
EEPROM is for data board card information, including board type information, FPGA firmware information etc..
Power management module includes 12V HSC and 12V_STBY HS, for realizing Power Supply Hot Swap management.Wherein 12V
HSC module, 5V power module provide power supply for GPU.12V_STBY HSC module, 3.3V power module, 1.8V power module,
1.2V power module provides power supply for FPGA.Meanwhile 3.3V power module be also temperature sensor, EEPROM, SPI FLASH and
I2C repeater provides power supply.
In one or more exemplary designs, the function can be real in hardware, software, firmware or any combination thereof
It is existing.If realized in software, can be stored in using the function as one or more instruction or code computer-readable
It is transmitted on medium or by computer-readable medium.Computer-readable medium includes computer storage media and communication media,
The communication media includes any medium for helping for computer program to be transmitted to another position from a position.Storage medium
It can be any usable medium that can be accessed by a general purpose or special purpose computer.As an example and not restrictive, the computer
Readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc memory apparatus, disk storage equipment or other magnetic
Property storage equipment, or can be used for carry or storage form be instruct or data structure required program code and can
Any other medium accessed by general or specialized computer or general or specialized processor.In addition, any connection is ok
It is properly termed as computer-readable medium.For example, if using coaxial cable, optical fiber cable, twisted pair, digital subscriber line
(DSL) or such as wireless technology of infrared ray, radio and microwave to send software from website, server or other remote sources,
Then above-mentioned coaxial cable, optical fiber cable, twisted pair, DSL or such as wireless technology of infrared ray, radio and microwave are included in
The definition of medium.As used herein, disk and CD include compact disk (CD), laser disk, CD, digital versatile disc
(DVD), floppy disk, Blu-ray disc, wherein disk usually magnetically reproduce data, and CD using laser optics reproduce data.On
The combination for stating content should also be as being included in the range of computer-readable medium.
From above-described embodiment as can be seen that graphics processor board provided in an embodiment of the present invention, by by FPGA and GPU
It is integrated on same board, so that local FPGA can be with direct monitoring GPU without the technical side by mainboard and CPU
Case can carry out effective and efficient management control work for different GPU or different types of GPU, improve board signal
Monitoring effect and efficiency, enhancing using flexible and scalability.
It is important to note that each device in each embodiment of above-mentioned board can be according to art technology
The demand of personnel and be exchanged with each other, change position, increase, deleting, therefore, these reasonable permutation and combination transformation in board
Protection scope of the present invention should belong to, and protection scope of the present invention should not be confined on the embodiment.
Based on above-mentioned purpose, the second aspect of the embodiment of the present invention, different GPU or difference can be directed to by proposing one kind
The GPU of type come carry out it is effective and it is efficient management control work server embodiment.The server includes:
The mainboard of central processing unit is installed；
Above-mentioned graphics processor board, the grafting of graphics processor board entirety on the main board and pass through PCIE bus
It is connected to the central processing unit.
It can be various electric terminal equipments, such as mobile phone, a number that the embodiment of the present invention, which discloses described device, equipment etc.,
Word assistant (PDA), tablet computer (PAD), smart television etc., are also possible to large-scale terminal device, such as server, therefore this hair
Protection scope disclosed in bright embodiment should not limit as certain certain types of device, equipment.The embodiment of the present invention discloses described
Client can be with the combining form of electronic hardware, computer software or both be applied to any one of the above electric terminal
In equipment.
Based on above-mentioned purpose, the third aspect of the embodiment of the present invention, different GPU or difference can be directed to by proposing one kind
The GPU of type come carry out it is effective and it is efficient management control work method embodiment.It the described method comprises the following steps:
Receive the control signal from mainboard；
Logic control is carried out to multiple graphics processor units 11 using above-mentioned graphics processor board according to control signal
System；
Mainboard is fed back by connector 13.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, Ke Yitong
Computer program is crossed to instruct related hardware and complete, the program can be stored in a computer-readable storage medium,
The program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can for magnetic disk,
CD, read-only memory (ROM) or random access memory (RAM) etc..The embodiment of the computer program, Ke Yida
The effect identical or similar to corresponding aforementioned any means embodiment.
From above-described embodiment as can be seen that server provided in an embodiment of the present invention and method, by by FPGA and GPU collection
At on same board so that local FPGA can with direct monitoring GPU without the technical solution by mainboard and CPU,
Effective and efficient management control work can be carried out for different GPU or different types of GPU, improve board signal monitoring
Effect and efficiency, enhancing using flexible and scalability.
It is important to note that the embodiment of above-mentioned server and method uses the embodiment of board to illustrate
The course of work of each module and step, those skilled in the art can be it is readily conceivable that be applied to board for these technical characteristics
Other embodiments in.Certainly, since each device in board embodiment can be exchanged with each other, change position, increase, delete
Subtract, therefore, these reasonable permutation and combination transformation should also be as belonging to the scope of protection of the present invention in server and method, and
Protection scope of the present invention should not be confined on the embodiment.
It is exemplary embodiment disclosed by the invention above, it should be noted that in the sheet limited without departing substantially from claim
Under the premise of inventive embodiments scope of disclosure, it may be many modifications and modify.According to open embodiment described herein
The function of claim to a method, step and/or movement be not required to the execution of any particular order.In addition, although the present invention is implemented
Element disclosed in example can be described or be required in the form of individual, but be unless explicitly limited odd number, it is understood that be multiple.
It should be understood that it is used in the present context, unless the context clearly supports exceptions, singular " one
It is a " it is intended to also include plural form.It is to be further understood that "and/or" used herein refers to including one or one
Any and all possible combinations of a above project listed in association.The embodiment of the present invention discloses embodiment sequence number
Description, does not represent the advantages or disadvantages of the embodiments.
It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, not
It is intended to imply that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；In the think of of the embodiment of the present invention
Under road, it can also be combined between the technical characteristic in above embodiments or different embodiments, and exist as described above
Many other variations of the different aspect of the embodiment of the present invention, for simplicity, they are not provided in details.Therefore, all at this
Within the spirit and principle of inventive embodiments, any omission, modification, equivalent replacement, improvement for being made etc. should be included in this hair
Within the protection scope of bright embodiment.
Claims (10)
1. a kind of graphics processor board characterized by comprising
Multiple graphics processor units, two interconnected by high-speed bus two between the multiple graphics processor unit, institute
The central processing unit composition heterogeneous processing system stating multiple graphics processor units and being set to outside graphics processor board；
Field programmable gate array is signally attached to the multiple graphics processor unit by control, for being believed according to control
Number to the multiple graphics processor unit carry out logic control；
Connector is connected to the multiple graphics processor unit and the field programmable gate array by PCIE bus, uses
In making the multiple graphics processor unit and the field programmable gate array signal and mainboard carry out signal transmission.
2. graphics processor board according to claim 1, which is characterized in that the logic control include it is following at least it
One: upper and lower electric control, enabled, reset, alarm signal management.
3. graphics processor board according to claim 1, which is characterized in that the multiple graphics processor unit and institute
It states and is also connected by I2C bus between field programmable gate array, the field programmable gate array is read by the connection of I2C bus
Take the device version information and Current Temperatures of the multiple graphics processor unit；The field programmable gate array also passes through
I2C bus is connected to the power management module being similarly provided on graphics processor board, board temperature sensor and board and deposits
Reservoir is respectively used to read power consumption information, current operating temperature and the board firmware information of graphics processor board.
4. graphics processor board according to claim 3, which is characterized in that the field programmable gate array also passes through
I2C bus is connected to the baseboard controller being set to outside graphics processor board, and the field programmable gate array will be following
At least one be transferred to the baseboard controller: the device version information and Current Temperatures of the multiple graphics processor unit,
Power consumption information, current operating temperature and the board firmware information of graphics processor board.
5. graphics processor board according to claim 1, which is characterized in that the field programmable gate array also passes through
Control is signally attached to mainboard, the mainboard by control signal make the field programmable gate array to the multiple figure at
It manages device unit and carries out logic control；The field programmable gate array also passes through control and is signally attached to be similarly provided at figure
The power management module on device board is managed, the field programmable gate array controls the power management module by control signal
Output and enabled.
6. graphics processor board according to claim 1, which is characterized in that it further include graphics processor clock, it is described
Communication between multiple graphics processor units uses the graphics processor clock as reference clock；At the multiple figure
Reason device unit and the field programmable gate array, which also pass through PCIE bus and be connected to, to be set to outside graphics processor board
Mainboard clock, described in the communication use between the multiple graphics processor unit and the field programmable gate array and mainboard
Mainboard clock is as reference clock.
7. graphics processor board according to claim 1, which is characterized in that further include being connected to the field-programmable
The debugging interface of gate array, the debugging interface is for emulating the field programmable gate array, and configuration, programming are solid
Part.
8. graphics processor board according to claim 7, which is characterized in that further include being connected to the field-programmable
The serial port chip of gate array, the serial port chip are used for the storage field programmable gate array when powering on and/or resetting
The firmware loaded.
9. a kind of server characterized by comprising
The mainboard of central processing unit is installed；
Graphics processor board as described in any one of claim 1-8, the graphics processor board are integrally plugged on
The central processing unit is connected on the mainboard and by PCIE bus.
10. a kind of graphic processing method, which comprises the following steps:
Receive the control signal from mainboard；
Use the graphics processor board as described in any one of claim 1-8 to multiple figures according to the control signal
Processor unit carries out logic control；
The mainboard is fed back by connector.
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| CN201811293216.6A CN109408445A (en) | 2018-11-01 | 2018-11-01 | A kind of graphics processor board |
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| CN201811293216.6A CN109408445A (en) | 2018-11-01 | 2018-11-01 | A kind of graphics processor board |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN114115955A (en) * | 2021-10-19 | 2022-03-01 | 苏州浪潮智能科技有限公司 | Method, system, terminal and storage medium for upgrading server resource box FPGA firmware |
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