CN111176927A - Detection system and detection method for functional board card - Google Patents
Detection system and detection method for functional board card Download PDFInfo
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- CN111176927A CN111176927A CN201911176327.3A CN201911176327A CN111176927A CN 111176927 A CN111176927 A CN 111176927A CN 201911176327 A CN201911176327 A CN 201911176327A CN 111176927 A CN111176927 A CN 111176927A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
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Abstract
The embodiment of the invention discloses a detection system and a detection method of a functional board card, relating to the technical field of electronic product detection, wherein the detection system comprises: a DSP chip; the memory is stored with an identity resolution corresponding relation table; and the FPGA chip is used for acquiring the identity and the test data of the tested function board card through the DSP chip according to the detection instruction, analyzing the corresponding relation table according to the identity and the identity to obtain standard output data of the function board card, judging whether the function board card is normal according to the test data and the standard output data, and providing the judgment result for the upper computer. The invention can carry out chip-level calibration self-test on electronic circuit products, can conveniently carry out intelligent calibration and self-test on key signals, key voltages and key frequencies on the tested equipment by only leading out corresponding test points from key components on the tested equipment, and provides real-time detection data for analysis, thereby getting rid of the limitation that one equipment corresponds to one detection tool.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic product detection, in particular to a system and a method for detecting a functional board card.
Background
Currently, electronic products are equipped with their own unique detection software or tools for electronic circuits. For example, a PC fault diagnosis card integrating software and hardware is characterized in that a detection result of a self-checking program inside a BIOS in a mainboard is utilized, codes are displayed, the displayed codes need to be matched with a code meaning quick look-up table to find out computer faults, the detection method needs to be matched with the software in detected equipment, the basic principle is to show the hardware detection result of the equipment again, and the detection result has certain limitation.
Disclosure of Invention
Therefore, the embodiment of the invention provides a detection system and a detection method of a functional board card, so as to solve the problems of inconvenience in detection and high limitation of an electronic circuit in the prior art.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
an embodiment of a first aspect of the present invention discloses a system for detecting a functional board, including: a DSP (digital signal Processing) chip connected with a tested function board card, wherein the tested function board card stores an identity; the memory is used for storing an identity analysis corresponding relation table; the FPGA (field programmable Gate Array) chip is connected with the tested function board card and the memory, and is used for receiving a detection instruction sent by an upper computer, acquiring the identity and the test data through the DSP chip according to the detection instruction, analyzing a corresponding relation table according to the identity and the identity to obtain standard output data of the function board card, further detecting whether the function board card is normal according to the test data and the standard output data, and providing a detection result to the upper computer.
Further, the memory includes: the flash memory is used for storing the identity after the DSP chip acquires the identity; a DDR2(Double Data Rate) memory for storing interface information and Data of the functional board.
Further, the model of the DSP chip is DSP 2812.
Further, the test data includes at least one of a voltage, a level and a frequency of the tested functional board.
Furthermore, the FPGA chip is also used for calibrating the output voltage of the functional board card through the DSP chip.
An embodiment of a second aspect of the present invention discloses a method for detecting a functional board, including the system for detecting a functional board of the first aspect, the method for detecting a functional board including: acquiring the identity identification and the test data of the tested function board card; analyzing a corresponding relation table according to the identity and a prestored identity to obtain standard output data of the tested function board card; and detecting whether the tested functional board card is normal or not according to the test data and the standard output data.
Further, the detection result of the tested function board card is provided for an upper computer, so that the upper computer can diagnose the fault reason of the function board card when the tested function board card is abnormal.
Further, still include: and when the output voltage of the tested function board card is abnormal, calibrating the output voltage of the function board card.
The invention has the following advantages: the method can be used for carrying out chip-level calibration self-detection on electronic circuit products (function cards), and can conveniently carry out intelligent calibration and self-detection on key signals, key voltages and key frequencies on the tested equipment by only leading out corresponding test points from key components on the tested equipment, and provide real-time detection data for analysis, so that the limitation that one equipment corresponds to one detection tool is eliminated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art can understand and read the present invention, and do not limit the conditions for implementing the present invention, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the functions and purposes of the present invention, should still fall within the scope covered by the contents disclosed in the present invention.
Fig. 1 is a block diagram of a detection system for a functional board according to an embodiment of the present invention.
Fig. 2 is a schematic detection diagram of a detection system of a functional board according to an example of the present invention.
FIG. 3 is a timing diagram of four data read operations using DDR2 in one example of the invention.
FIG. 4 is a timing diagram for reading four data while busy using DDR2 read in one example of the invention.
FIG. 5 is a timing diagram of four data write operations using DDR2 in one example of the invention.
FIG. 6 is a timing diagram for writing four data while writing busy using DDR2 in one example of the invention.
Fig. 7 is a flowchart of a method for detecting a functional board according to an embodiment of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be noted that the terms "connected" and "connected," unless otherwise specifically stated or limited, are to be construed broadly, either directly or indirectly through intervening media. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Fig. 1 is a block diagram of a detection system for a functional board according to an embodiment of the present invention. As shown in fig. 1, the system for detecting a functional board according to an embodiment of the present invention includes: DSP chip, memory and FPGA chip.
Wherein, the DSP chip is connected with the tested function board card. The tested function board card stores an identity which is pre-input into the storage device of the tested function board card.
The memory stores an identity analysis corresponding relation table.
And the FPGA chip is connected with the tested function board card and the memory. The FPGA chip is used for receiving a detection instruction sent by the upper computer. The FPGA chip and the upper computer are communicated through a serial port, and the serial port communication completes the conversion and communication between a 232 serial port of the computer and the TTL level. And the FPGA chip acquires the identity and the test data through the DSP chip according to the detection instruction. The FPGA chip is further used for analyzing the corresponding relation table according to the identity and the identity to obtain standard output data of the functional board card, further detecting whether the functional board card is normal or not according to the test data and the standard output data, and providing a detection result for the upper computer.
In one embodiment of the invention, the memory includes flash memory and DDR2 memory. The flash memory is used for storing the identity after the DSP chip acquires the identity. The DDR2 memory is used for storing interface information and data of the functional board card. The DDR2 is used to store data for a large number of functional boards.
Fig. 2 is a schematic detection diagram of a detection system of a functional board according to an example of the present invention. As shown in fig. 2, due to the schematic diagram and the block diagram of the FPGA and the DDR2, the storage capacity of the FPGA itself is very small, and the data storage requirement of a large number of functional boards cannot be met, and to solve this problem, a hardware architecture of FPGA + DDR2 is adopted, and the storage control of the DDR2 is realized by the FPGA, so that the storage capacity of the system is greatly expanded. The interfaces of the ddr2 controller module can be divided into three categories:
the first type: the system interface comprises interfaces such as reset of a system or PLL, a clock and the like;
the second type: the interface starting with local is the interface between the DDR2 IP core and the user logic;
in the third category: the interface beginning with mem is the interface between the DDR2 IP core and the FPGA external DDR2 chip.
FIG. 3 is a timing diagram of four data read operations using DDR2 in one example of the invention. As shown in fig. 3, Local _ ready: a "1" indicates that the controller can accept the read/write parent request signal at this time.
Local _ burst _ gain: a local burst start signal.
Local _ read _ req: a read request signal. A read request can only be initiated when the Local _ ready signal is high.
Local _ size: local burst length, i.e. the number of consecutive reads or writes of Local _ data. The length cannot exceed the length of maximum avalon-mm burst length configured in the ddrip core.
Local _ addr: address signals for read operations.
Local _ rdata _ avild: the local read data valid flag, when high, can initiate a read request.
Local _ rdata: and reading data locally.
When four data are read using the DDR2, Local _ ready is first made high, and Local _ read _ req is made high, where Local _ size gives the length of data to be read and Local _ addr gives the address of data to be read. When Local _ rdata _ avild is high level, four data (data1, data2, data3, and data4) are read.
FIG. 4 is a timing diagram for reading four data while busy using DDR2 read in one example of the invention. As shown in fig. 4, while the read is busy, the local _ read _ req is kept high continuously, and the length and address of the read data are given while the local _ read _ req is high.
FIG. 5 is a timing diagram of four data write operations using DDR2 in one example of the invention. As shown in fig. 5, Local _ write _ req: a write operation request signal. Local _ wdata: and writing data locally. The local _ write _ req signal must be kept active throughout the process when writing data.
FIG. 6 is a timing diagram for writing four data while writing busy using DDR2 in one example of the invention. As shown in FIG. 6, while the write is busy, the hold _ write _ req signal is always active. Data is written when Local _ ready is at high level.
In one embodiment of the invention, the model of the DSP chip is DSP 2812. DSP2812 is a 32-bit fixed-point DSP of TMS320F2812 with powerful functions, is an upgraded version of TMS320LF2407A, and is characterized in that the speed is higher than TMS320LF2407A by a qualitative jump from 40M at the maximum to 150M of TMS320F2812, and the number of processed data bits is also increased from 16-bit fixed-point to 32-bit fixed-point. The biggest bright spot is that the motor has EVA and EVB event managers and matched 12-bit 16-channel AD data acquisition, so that the motor can be controlled easily. And abundant peripheral interfaces such as CAN, SCI, etc.
TMS320F2812 is a novel high-performance 32-bit fixed-point digital signal processor based on a C28x kernel with codes compatible with DSP codes of F24x/LF240x series and partial functions, the instruction execution period of the C28x kernel reaches 6.67ns, the highest operation frequency can reach 150MHz, and the control system is ensured to have enough operational capability.
In addition, F2812 integrates a plurality of peripherals to provide a whole set of system on chip, thereby reducing the system cost and realizing simpler and more efficient control. The on-chip peripheral mainly comprises 2 multiplied by 8 paths of 12-bit ADCs (fastest 80ns conversion time), 2 paths of SCIs, 1 path of SPIs, 1 path of McBSPs, 1 path of ECAN interfaces and the like, and is provided with two event management modules (EVA and EVB) which respectively comprise 6 paths of PWM/CMP, 2 paths of QEPs, 3 paths of CAPs and 2 paths of 16-bit timers (or TxPWM/TxCMP).
In addition, the device has 3 independent 32-bit CPU timers, and up to 56 independently programmed GPIO pins.
Therefore, the TMS320F2812 has excellent data processing capacity of a digital signal processor, has on-chip peripherals and interfaces suitable for control, and can be widely applied to various high-performance system controls.
TMS320F2812 is different from the F24xx series DSP, and adopts a uniform addressing mode. The chip has an 18K SARAM including 5 memory blocks of MO, M1, L0, L1 and H0. The storage blocks are kept independent, and different RAM blocks can be accessed in the same machine period, so that the pipeline delay is reduced.
In addition, the TMS320F2812 is internally provided with a FLASH with 128K words and an address space of 3D8000 h-3F 7FFFh, and is suitable for a control system with low power consumption and high performance.
In addition, F2812 provides an external memory expansion interface (XINTF), which facilitates system expansion and has an addressing space of up to 1 MB. F2812 has several optional power-on guide modes, and program guide control during DSP power-on can be performed by setting different states of GPIOF4, GPIOF12, GPIOF3 and GPIOF 2.
The AD in the DSP chip can collect the data, various voltages and levels of the tested functional board card. The FPGA chip collects frequency and level.
In addition, other configurations and functions of the detection system of the functional board card according to the embodiment of the present invention are known to those skilled in the art, and are not described in detail in order to reduce redundancy.
Fig. 7 is a flowchart of a method for detecting a functional board according to an embodiment of the present invention. As shown in fig. 7, a method for detecting a functional board according to an embodiment of the present invention includes the system for detecting a functional board according to the embodiment, where the method for detecting a functional board includes:
s1: and acquiring the identity and the test data of the tested function board card.
S2: and analyzing the corresponding relation table according to the identity and the pre-stored identity to obtain the standard output data of the tested function board card.
S3: and detecting whether the tested functional board card is normal or not according to the test data and the standard output data.
In an embodiment of the present invention, the method for detecting a functional board further includes: and providing the detection result of the tested function board card to the upper computer so that the upper computer can diagnose the fault reason of the function board card when the tested function board card is abnormal.
In an embodiment of the present invention, the method for detecting a functional board further includes: and when the output voltage of the tested function board card is abnormal, calibrating the output voltage of the function board card.
Specifically, when the functional board is powered on and the program is downloaded, the board ID is automatically read when the functional board is connected to the detection device. After the ID is read out to identify the tested function board card, the AD and FPGA chips of the DSP chip can acquire the voltage level frequency of the tested function board card, and the tested function board card is ensured to be set to a desired state. When the states are not aligned, the data are transmitted to the upper computer through the data line to judge where the data are not aligned. When the data are different, the voltage coming out through the DSP chip can calibrate the board card slightly, and the consistency of the board card is ensured. And storing the initial data of the board card, storing the data of the board card again after the maintenance of the board card, and transmitting the data to the upper computer software for judgment.
It should be understood that those skilled in the art can flexibly design the number of each chip according to the complexity of the function card and the port resources of the selected FPGA and DSP. When the function card is more complex and requires more chips than the present embodiment to complete the detection or maintenance task, more chips can be extended based on the above embodiments according to the same technical idea, and the invention is also within the scope of the present invention. In addition, the communication modes of the FPGA, the DSP, and the PC, and the models of the chips are not limited to those in the embodiments, and those skilled in the art can replace the communication modes within the scope of the technical idea disclosed in the present invention as long as the functions meet the requirements of the technical solution of the present invention, without affecting the implementation of the object of the present invention.
In the description herein, references to the description of "one embodiment" or "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (8)
1. The utility model provides a detecting system of function integrated circuit board which characterized in that includes:
the DSP chip is connected with the tested function board card, and the identity is stored in the tested function board card;
the memory is used for storing an identity analysis corresponding relation table;
the FPGA chip is used for receiving a detection instruction sent by an upper computer, acquiring the identity identification and the test data through the DSP chip according to the detection instruction, analyzing the corresponding relation table according to the identity identification and the identity identification to obtain standard output data of the function board card, detecting whether the function board card is normal according to the test data and the standard output data, and providing a detection result for the upper computer.
2. The system of claim 1, wherein the memory comprises:
the flash memory is used for storing the identity after the DSP chip acquires the identity;
and the DDR2 internal memory is used for storing interface information and the data of the functional board card.
3. The system for detecting the functional board card of claim 1, wherein the model of the DSP chip is DSP 2812.
4. The system of claim 1, wherein the test data includes at least one of a voltage, a level, and a frequency of the functional board under test.
5. The system of claim 1, wherein the FPGA chip is further configured to calibrate an output voltage of the functional board via the DSP chip.
6. A method for detecting a function board, comprising the system for detecting a function board according to any one of claims 1 to 5, the method comprising:
acquiring the identity identification and the test data of the tested function board card;
analyzing a corresponding relation table according to the identity and a prestored identity to obtain standard output data of the tested function board card;
and detecting whether the tested functional board card is normal or not according to the test data and the standard output data.
7. The method for detecting the functional board card according to claim 6, further comprising:
and providing the detection result of the tested function board card to an upper computer so that the upper computer can diagnose the fault reason of the function board card when the tested function board card is abnormal.
8. The method for detecting the functional board card according to claim 6, further comprising:
and when the output voltage of the tested function board card is abnormal, calibrating the output voltage of the function board card.
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