CN209728477U - A kind of multichannel temperature data acquisition circuit - Google Patents
A kind of multichannel temperature data acquisition circuit Download PDFInfo
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- CN209728477U CN209728477U CN201920744987.6U CN201920744987U CN209728477U CN 209728477 U CN209728477 U CN 209728477U CN 201920744987 U CN201920744987 U CN 201920744987U CN 209728477 U CN209728477 U CN 209728477U
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Abstract
The utility model discloses a kind of multichannel temperature data acquisition circuit, including fpga chip, fpga chip is connected by interface circuit with MPU communication chip；Fpga chip includes being sequentially connected the serial line interface host connect, data processing channel, temperature data RAM block, RX-RAM module and state machine；Temperature data RAM block is connected by interface circuit with MPU communication chip；One serial line interface host connects a data processing channel, and all data processing channels are connected with temperature data RAM block；There is all data processing channels structure with duplicate feature, only frame link to be added to add address byte of the channel to identify data source parallel.The Acquisition Circuit realizes multichannel temperature measurement, and measurement control, data transmission, temperature spot verification, small signal stabilization and intelligent management function.
Description
Technical field
The utility model belongs to data acquisition circuit technical field of structures, is related to a kind of multichannel temperature data acquisition electricity
Road.
Background technique
Temperature is main controlled parameter in Industry Control, and temperature detection is the important component of modern detecting,
What is characterized is the cold and hot degree of object.The measurement and control of temperature all directly and keep the safety in production, improve production efficiency, guarantee product
The important technicals such as quality, energy saving economic indicator is related.Most of temperature measurement is made with single-chip microcontroller in the prior art
For main control chip, a large amount of temperature data measurement is carried out.
With the fast development of electronic technology, in the place that some environmental requirements are stringent, by single-chip microcontroller as control centre
The method for carrying out temperature detection has been gradually backed out market.Consequent is using field programmable logic device FPGA as master
Chip to be controlled, temperature data is acquired, handle and is transmitted, this mode is used not only in the detection that temperature is carried out in air,
And it just gradually applies in vacuum environment.Temperature measurement is carried out using EP3C25E1447 as main control chip can make hardware system
Simplification, maintainability is good and at low cost, cost performance is high, not only improves efficiency, moreover it is possible to bring better benefit.
Summary of the invention
The purpose of the utility model is to provide a kind of multichannel temperature data acquisition circuits, solve the complexity of circuit system
Change, so that the acquisition, processing and transmission to temperature become simplified as, while making circuit structure that more there is stability.
To achieve the above object, the technical scheme adopted by the utility model is a kind of multichannel temperature data acquisition electricity
Road, including fpga chip, fpga chip are connected by SPI Slave interface circuit with MPU communication chip；
The fpga chip includes being sequentially connected the serial line interface host, data processing channel, temperature data RAM connect
Block, RX-RAM module and state machine；Temperature data RAM block is connected with SPI Slave interface circuit, SPI Slave interface circuit
It is connected to SPI interface with MPU communication chip by rear
Serial line interface host is made of at least six parallel serial line interface hosts；Data processing channel is by parallel quantity
Data processing channel composition identical with serial line interface host number；It is logical that one serial line interface host connects a data processing
Road, all data processing channels are connected with temperature data RAM block；All data processing channels have structure parallel with it is duplicate
Feature is only adding frame link to add address byte of the channel to identify data source；
One serial line interface host is connected by a forward direction SPI interface with an ADC chip.
The utility model multichannel temperature data acquisition circuit, not only becomes simplified as circuit structure, promotes data and passes
Defeated speed, and the I/O mouth of FPGA is extremely abundant, has the processing capacity of high speed to real time data.And design cost is lower, it can
Maintainability is good, can satisfy in each environment to the measurement of temperature data, and measurement control, data transmission, temperature spot school
It tests, small signal stabilization and intelligent management function
Detailed description of the invention
Fig. 1 is the structural block diagram of the utility model Acquisition Circuit.
Fig. 2 is the circuit block diagram of RX-RAM module in the utility model circuit circuit.
Fig. 3 is two kinds of working mode figures of the utility model SPI-Slave.
Fig. 4 is that the utility model Acquisition Circuit reads word specified by address byte from the temperature data T-RAM of FPGA
Save data mode figure.
Fig. 5 is processing of circuit flow chart in fpga chip in the utility model Acquisition Circuit.
In Fig. 1: 1. serial line interface hosts, 2. data processing channels, 3. temperature data RAM blocks, 4.SPI Slave interface electricity
Road, 5.MPU communication chip, 6.RX-RAM module, 7. state machines, 8.ADC chipset, 9.E2PROM chip, the selection of 10. data
Device, 11. memories, 12. first shift registers, 13. second shift registers, 14. address dates distribute decoder.
Specific embodiment
The utility model is described in further detail below with reference to specific example and attached drawing.
As shown in Figure 1, the utility model Acquisition Circuit, including fpga chip, fpga chip pass through SPI Slave interface electricity
Road 4 is connected with MPU communication chip 5.
Fpga chip include be sequentially connected the serial line interface host 1 connect, data processing channel 2, temperature data RAM block 3,
RX- RAM module 6 and state machine 7；Temperature data RAM block 3 is connected with SPI Slave interface circuit 4, SPI Slave interface electricity
Road 4 is connected to SPI interface with MPU communication chip 5 after passing through；
Serial line interface host 1 is by parallel serial line interface host I, serial line interface host II, serial line interface host III, serial
Interface Host IV, serial line interface host V and serial line interface host VI form；Data processing channel 2 is led to by parallel data processing
Road I, data processing channel II, data processing channel III, data processing channel IV, data processing channel V and data processing channel
VI composition；Serial line interface host I connects data processing channel I to SPI interface I by preceding, serial line interface host II by it is preceding to
SPI interface II connects data processing channel II, and serial line interface host III connects data processing channel to SPI interface III by preceding
III, serial line interface host IV connects data processing channel IV to SPI interface IV by preceding, serial line interface host V by it is preceding to
SPI interface V connects data processing channel V, and serial line interface host VI connects data processing channel to SPI interface VI by preceding
Ⅳ.Data processing channel I, data processing channel II, data processing channel III, data processing channel IV, data processing channel V
It is connected with temperature data RAM block 3 with data processing channel VI.
As shown in Fig. 2, the RX-RAM module 6 in the utility model Acquisition Circuit, including the address date point being sequentially connected
With decoder 14, memory 11 and data selector 10, data selector 10 respectively with ADC chipset 8, E2PROM chip 9 and
Second shift register 13 is connected, and the second shift register 13 is decoded with the first shift register 12 and address date distribution respectively
Device 14 is connected.
ADC chipset 8, E2PROM chip 9, memory 11 and address date distribution decoder 14 respectively with 7 phase of state machine
Even.Memory 11 is connected with SPI Slave interface circuit 4.
ADC chipset 8 includes ADC0 chip~ADC5 chip in Fig. 1.
SPI clock in Fig. 2 is the clock of SPI-slave communication protocol, mainly gives SPI-master and SPI-slave
Clock is provided.
Memory 11 includes T-RAM, P-RAM and F-RAM data read mode.
After the completion of fpga chip initialization, enter reading mode (R) mode at once.At reading mode (R), ADC chipset 8 is pressed
The initiation parameter of default works in data processing state and T-RAM fill state, and SPI communication interface is by T-RAM's and P-RAM
Address and data are opened to MPU communication chip 5.Read the temperature in T-RAM and P-RAM in the address that MPU communication chip 5 presses biography
Degree evidence or supplemental characteristic.It is to write mould by SPI communication pattern switching if the address for receiving the transmission of MPU communication chip 5 is FF
Formula (W) mode.At WriteMode (W), the related area RAM, which opens, to be write enabled, and the data from SPI can just be write according to leading address
Enter relevant range.As shown in Figure 3.
The main temperature upload realized in memory 11 of SPIslave interface circuit 4 based on SPI-slave communication protocol,
ADC parameter setting and RTD phasing meter update.Instruction (address/data) from MPU communication chip 5 passes through address date point
Switch the different flow directions of address and data with decoder 14, and translate the subsequent director data in special address, by modifying state
The value of register completes the control to FPGA state or mode, this partial circuit is made to be in two kinds of operating modes of R and W.Once electric
Road is in R mode (T-RAM, P-RAM data read mode), and the address T-RAM transmitted according to MPU communication chip 5 can be realized
Temperature data in data acquisition T-RAM, as shown in Figure 4.This mode keeps the transmission channels of temperature data most short, can reach
Higher spi bus speed.
MPU communication chip 5 sends the address T-RAM to be read by the MOSI signal of SPI, receives the address by MISO
Temperature data in T-RAM.Only data the latter byte cycle more stagnant than appropriate address, next address and a upper number are factually
Now transmitting-receiving exchange.Circuit design in FPGA in relation to the instruction is simplified, after the completion of the byte shift of a SPI, only need by
The address pointer of the value filling T-RAM of Sbuf (SPI buffers byte), is then backfilling into Sbuf for the value of address meaning again.
The SPI-Sbuf operation of MPU is similar, after the completion of the byte shift of a SPI, first removes the data in sbuf, then again
Sbuf is inserted into new address.
Fpga chip internal circuit has the function of temperature soft alignment, can pass through upper computer selecting phasing meter and setting calibration system
Number, while there is internal temperature numeric number filter function, the stability and precision of temperature data can be improved.
6 AD7193(B types of fpga chip interior circuit construction at least 6 forward direction SPI interface energy parallel drives) or
AD7124-8(A type) chip, including initialization, setting and the reading data to ADC chipset 8.1 and MPU communication chip 5
Connected SPI Slave interface circuit 4 is subjected to the instruction from MPU communication chip 5 and return data.To ADC chipset 8
Initialization or setting include data output rate setting, gain setting, channel selecting.
The interface rate of forward direction SPI in fpga chip must satisfy the data output rate of ADC chip highest 4.8KHz；
The rate of backward SPI interface must satisfy 24 sample point data sending time≤10ms.
The operating mode or working condition of signal processor fpga chip internal circuit are by rear end MPU communication chip
5 signal S0 and S1 control, CS [0], CS [1], CS [2], CS [3] signal inside fpga chip communicate core with rear end MPU
CS [0], CS [1], CS [2], CS [3] signal on piece 5 are as five spi bus chip selection signals.6 data of fpga chip
Treatment channel have structure parallel with duplicate feature, only on the ground to identify data source for adding frame link to add the channel
Location byte.
AD value stationary filtering and noise filtering function on signal processor fpga chip internal circuit, using effective filter
Wave algorithm removes the interference of sampling channel, improves the stability and precision of temperature data, while having port self-test and thermal resistance
Interface zero load automatic identification function (open circuit, short circuit, light condition that port can be judged according to resistance value or voltage value), can be automatic
Airborne interfaces exclusion is being measured except sequence, to improve temperature data acquisition efficiency, is improving Refresh Data frequency.
Process flow diagram inside fpga chip, as shown in Figure 5.Signal processing core devices fpga chip powers on completion and matches
Detection S0 signal and S1 signal condition is postponed, the not yet completion initialization or not yet of MPU communication chip 5 is then illustrated if " 11 "
Thread (state of S0, S1 are that convenient test can also be arranged on hardware by wire jumper)；Otherwise it is selected according to remaining three state values
The parameter sets K [n1, n2] that particular address is set in selecting property load E2PROM chip 9.K [n1] is related correction factor and selection point
The parameter sets of table are spent, K [n2] is the parameter sets initialized in relation to ADC chip 21.It is exported in the conversion of ADC chip 8 with data
State in, if backward SPI Slave interface circuit 4 receives the order of MPU communication chip 5, fpga chip is according in the order
Hold and executes 1,2, the different tasks such as x respectively.Task 1 is parameter setting, and the setting parameter received write-in E2PROM chip 9 is defaulted
In address, parameter sets K [n1, n2] is then reloaded, and makes the default parameter after powering on next time.Task 2 is attached most importance to
If the mode of ADC chip 8, the interim operating mode parameter for modifying ADC chip 8, and reinitialize ADC chip 8.Interim modification
Parameter will not become next time booting after default mode.Task X is other treatment processes, including self-test, port diagnosis, calibration
Etc. treatment processes.Port diagnostic operation may include in process of self-test, be to carry out distinguishing sensor open circuit according to measured value and threshold value
(zero load), short circuit lack the states such as line, exception, and automatically exclude unloaded port except acquisition channel sequence.For short circuit,
The data frame flag bit of abnormal is identified.It, generally can be under the control of MPU communication chip 5 after the completion of chip initiation
Complete a self-test operations.
SPI-salve interface circuit 4 is the communication interface of data collecting card fpga chip Yu MPU communication chip 5, by MPU
Communication chip 5 is determined by four chip selection signal CS [0..3] acquires cartoon letters with for which.After the completion of fpga chip initialization,
At once enter R mode.In the r-mode, ADC chip 8 works in data processing state by the initiation parameter of default and T-RAM is filled out
Write state, SPI communication interface open the address of T-RAM and P-RAM and data to MPU communication chip 5.MPU communication chip 5
Press the temperature data or supplemental characteristic in the address reading T-RAM and P-RAM of biography.If fpga chip receives MPU communication core
The address that piece 5 is sent is FF, then is W mode by SPI communication pattern switching.Under W mode, the related area RAM, which opens, to be write enabled, is come
Just relevant range can be written according to leading address from the data of SPI.
MPU communication chip 5 sends the address T-RAM to be read by the MOSI signal of SPI, receives the address by MISO
Temperature data in T-RAM.Only data the latter byte cycle more stagnant than appropriate address, next address and a upper number are factually
Now transmitting-receiving exchange.Circuit design in FPGA in relation to the instruction is simplified, after the completion of the byte shift of a SPI, only need by
Sbuf(SPI buffer byte) value filling T-RAM address pointer, the value of address meaning is then backfilling into Sbuf again.
The SPI-Sbuf operation of MPU communication chip 5 is similar, after the completion of the byte shift of a SPI, first moves the data in sbuf
It walks, Sbuf is then inserted into new address again.
Claims (4)
1. a kind of multichannel temperature data acquisition circuit, it is characterised in that: including fpga chip, fpga chip passes through SPI
Slave interface circuit (4) is connected with MPU communication chip (5)；
The fpga chip includes being sequentially connected the serial line interface host (1) connect, data processing channel (2), temperature data RAM
Block (3), RX-RAM module (6) and state machine (7)；Temperature data RAM block (3) is connected with SPI Slave interface circuit (4), SPI
Slave interface circuit (4) is connected to SPI interface with MPU communication chip (5) after passing through
Serial line interface host (1) is made of at least six parallel serial line interface hosts；Data processing channel (2) is by parallel number
Measure data processing channel composition identical with serial line interface host number；It is logical that one serial line interface host connects a data processing
Road, all data processing channels are connected with temperature data RAM block (3)；All data processing channels have structure parallel and again
Multiple feature is only adding frame link to add address byte of the channel to identify data source；
One serial line interface host is connected by a forward direction SPI interface with an ADC chip.
2. multichannel temperature data acquisition circuit according to claim 1, it is characterised in that: the RX-RAM module
It (6) include address date distribution decoder (14), memory (11) and the data selector (10) being sequentially connected, data selector
(10) it is connected respectively with ADC chip (8), E2PROM chip (9) and the second shift register (13), the second shift register (13)
It is connected respectively with the first shift register (12) and address date distribution decoder (14)；ADC chip (8), E2PROM chip
(9), memory (11) and address date distribution decoder (14) are connected with state machine (7) respectively, memory (11) and SPI
Slave interface circuit (4) is connected.
3. multichannel temperature data acquisition circuit according to claim 1, it is characterised in that: the forward direction SPI interface
Rate must meet the data output rate of ADC chip highest 4.8KHz.
4. multichannel temperature data acquisition circuit according to claim 1, it is characterised in that: the backward SPI interface
Rate must meet 24 sample point data sending time≤10ms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920744987.6U CN209728477U (en) | 2019-05-23 | 2019-05-23 | A kind of multichannel temperature data acquisition circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920744987.6U CN209728477U (en) | 2019-05-23 | 2019-05-23 | A kind of multichannel temperature data acquisition circuit |
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| CN209728477U true CN209728477U (en) | 2019-12-03 |
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| CN201920744987.6U Expired - Fee Related CN209728477U (en) | 2019-05-23 | 2019-05-23 | A kind of multichannel temperature data acquisition circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111487902A (en) * | 2020-04-03 | 2020-08-04 | 中机试验装备股份有限公司 | Testing machine system and multi-channel control equipment thereof |
| CN114647449A (en) * | 2020-12-17 | 2022-06-21 | 航天科工惯性技术有限公司 | Data processing method, device and system of terminal equipment |
-
2019
- 2019-05-23 CN CN201920744987.6U patent/CN209728477U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111487902A (en) * | 2020-04-03 | 2020-08-04 | 中机试验装备股份有限公司 | Testing machine system and multi-channel control equipment thereof |
| CN114647449A (en) * | 2020-12-17 | 2022-06-21 | 航天科工惯性技术有限公司 | Data processing method, device and system of terminal equipment |
| CN114647449B (en) * | 2020-12-17 | 2024-02-20 | 航天科工惯性技术有限公司 | Data processing method, device and system of terminal equipment |
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Granted publication date: 20191203 Termination date: 20210523 |