CN103558543B - A kind of volume production method of testing to CIS chip - Google Patents
A kind of volume production method of testing to CIS chip Download PDFInfo
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Abstract
A kind of volume production method of testing to CIS chip, is carried out based on FPGA module, including: the test system of the test carrier plate having test machine and be provided with MIPI bridging chip and FPGA module is provided；Test machine controls CIS chip and gathers image；View data is exported MIPI bridging chip with the pattern of high-speed serial signals by CIS chip；MIPI bridging chip reads high-speed serial signals under FPGA module control, is converted into parallel low speed data signal and is uploaded to FPGA module；FPGA module reads parallel low speed data signal, carries out technical finesse, it is thus achieved that result of calculation, result of calculation is uploaded under the control of test machine；Test machine carries out after reading result judging and the control of program circuit.The present invention changes the dependence avoiding the high speed signal port to test machine by the data of special MIPI bridging chip；Use the internal DSP data of FPGA to process simultaneously, improve the calculating speed of data, it is achieved multistation parallel data computing, shorten data processing time than the serial computing relying on test machine work station.
Description
Technical field
The present invention relates to integrated circuit volume production technical field of measurement and test, particularly to a kind of based on FPGA
CIS chip volume production method of testing for band MIPI port.
Background technology
Existing high-end CIS (CMOS Image Sensor) chip has reached more than 5,000,000 pixels
Resolution ratio, say, that each frame image data of its sampling all can comprise at least 500 groups with last
View data；And for improving the efficiency of transmission of data, chip mostly uses mobile communications industry to process
Device interface (Mobile Industry Processor Interface) MIPI is as leading to that view data is transmitted
Road, the speed of its data output is the highest can reach 1Gbps.
The test mode of traditional CIS chip volume production is usually and uses the high-end ATE of specialty automatically to survey
Examination equipment (Automatic Test Equipment) processes.Meet the survey of high-end CIS chip
Examination demand, these ATE equipment are necessary for meeting following condition:
(1) there is the work station at a high speed test view data for high speed processing magnanimity, with fall
The time that low test program performs；
(2) must have digital signal channel module at a high speed for accepting the figure from MIPI interface
As data；Typically require the data of test machine digital channel hardware to accept speed and at least can reach
500Mbps is the highest
(3) tester table itself needs have the special software and hardware for required for CIS chip testing
Module.
Consequently, it is possible to the price of tester table is the highest；It is additionally, since all data must upload
Being uniformly processed to work station, under the pattern of multistation chip parallel test, all data process
It is merely able to perform serially, seriously reduces the execution efficiency of test program, thus cause chip testing
Being substantially increased of cost, affects the competitiveness of product.
Summary of the invention
For above-mentioned problems of the prior art, it is an object of the invention to provide execution efficiency
Height, the CIS chip volume production test side for band MIPI port based on FPGA that testing cost is low
Method.
In order to realize foregoing invention purpose, the technical solution used in the present invention is as follows:
A kind of volume production method of testing to CIS chip, described CIS chip has mobile Industry Processor
Interface MIPI, described method is carried out based on on-site programmable gate array FPGA module, including as follows
Step:
Step 1: provide a kind of volume production to CIS chip to test system, including: test machine, tested
CIS chip, test carrier plate, wherein, test carrier plate is installed MIPI bridging chip and FPGA mould
Block；The pin of the MIPI port of tested CIS chip and the MIPI input port of MIPI bridging chip
Being connected, other signal ports of MIPI bridging chip are connected with FPGA module, by FPGA module
Control；
Step 2: test machine controls CIS chip by the digital channel direct-connected with tested CIS chip and adopts
Collection image；
View data is believed with high speed serialization after gathering image by step 3:CIS chip by MIPI port
Number pattern export MIPI bridging chip；
Step 4:MIPI bridging chip reads described high-speed serial signals under FPGA module control,
It is converted into parallel low speed data signal and is uploaded to FPGA module；
Step 5:FPGA module reads the parallel of MIPI bridging chip conversion by parallel data channels
Low speed data signal, carry out technical finesse, it is thus achieved that result of calculation；
Result of calculation is uploaded under the control of test machine by step 6:FPGA module；
Step 7: test machine carries out after reading result judging and the control of program circuit；
Step 8: after above-mentioned steps 2-7 completes, test machine send instruction allow tested CIS chip and
FPGA module returns to holding state, completes a test period.
Preferably, in the above-mentioned volume production method of testing to CIS chip, described FPGA module is with auxiliary
The pattern of peripheral circuit is helped to be directly installed on test carrier plate as a part for test carrier plate circuit.
Preferably, in the above-mentioned volume production method of testing to CIS chip, described FPGA module is by advance
First it is fabricated to circuit daughter board, is connected with test carrier plate by special connector or joint when application.
Further, in the above-mentioned volume production method of testing to CIS chip, in described FPGA module
Portion's unit includes: central control module, data computation module DSP, data cache module RAM,
Register module and clock module PLL, wherein,
Central control module for up test machine and the communication of descending MIPI bridging chip and number
According to exchange and control the collaborative work of whole FPGA module built-in system, the instruction of acceptance test machine,
Control the work of MIPI bridging chip, control internal element and data are processed accordingly, and will
Final calculation result uploads test machine；
DSP is used under the control of central control module the raw image data being stored in RAM
Carry out calculating process, and return result；Algorithm routine needed for all image procossing is all pre-stored in
In RAM, central control module it is responsible for selecting concrete function；
RAM is for storage two class data messages: the raw image data read from outside, DSP's
Result of calculation and intermediate data；The data of RAM and address port are controlled with central authorities by bus simultaneously
Molding block and DSP connect, in order to the initial data write of central control module and the data of DSP
Read and result writes back；
Register module is for preserving all kinds of parameter arranging FPGA module work, and FPGA mould
Block various results at work and status information；It is right that test machine can be realized by central control module
The random data read-write operation of register；
PLL is used for providing the various reference clocks needed for FPGA module inside and external circuit, with
Guarantee the uniformity of the clock zone of whole system；Clock source is respectively by the basis on test machine or test carrier plate
Ground crystal oscillator provides；It is same that the clock source provided by test machine guarantees that whole system and test machine strictly share
Clock zone；The clock source provided by the local crystal oscillator on test carrier plate guarantees precision and the low noise of clock zone
Characteristic；During work, PLL module is according to the concrete feature applied and demand, when selecting the reference being suitable for
Zhong Yuan.
Further, in the above-mentioned volume production method of testing to CIS chip, tested CIS chip and
FPGA module, the power supply of MIPI chip is provided by test machine.
Further, in the above-mentioned volume production method of testing to CIS chip, test machine is by direct-connected
Tested CIS chip is configured by data channel, it is ensured that CIS chip normally works, and gathers light source letter
Number and by the data of digital picture by high speed MIPI port send to test carrier plate.
Further, in the above-mentioned volume production method of testing to CIS chip, test machine is to FPGA mould
Block system configures, and register is carried out parameter read-in, arranges the work side of FPGA module system
Formula and condition of work.
Further, in the above-mentioned volume production method of testing to CIS chip, described step 5 includes:
Step 501:FPGA module after test machine receives clear and definite commencing signal, FPGA module
Internal central control module starts to read view data from parallel data port and be saved in RAM；
Step 502: after the view data that a frame is complete accepts, central control module starts
DSP；
Step 503:DSP according to the configuration information being pre-stored in register, the parameter needed for selection with
And the raw image data in RAM is processed by algorithmic function, and result is saved in the lump
Specific position in RAM；
Described step 6 includes: after data have calculated, the central control module of FPGA module
Test machine is notified by specific digital signal channel；
Described step 7 includes: test machine is linked up with FPGA module after receiving notification signal,
By the FPDP being connected with FPGA module, required calculating result is read test machine
Work station and carry out final judgement and Row control.
Further, in the above-mentioned volume production method of testing to CIS chip, described tested CIS chip
The signal port unrelated with MIPI port by test carrier plate directly and test machine want close hardware money
Source connects, so that it is guaranteed that all universal test projects of CIS chip can be done directly by test machine.
The present invention is changed by the data of special MIPI bridging chip and avoids the high speed to test machine
The dependence of signal port；Use the method that the data of the internal DSP of FPGA process the most simultaneously
Improve the calculating speed of data, and owing to being capable of multistation parallel data computing, compare former
The serial computing relying on test machine work station is greatly shortened data processing time.
Accompanying drawing explanation
Fig. 1 is that the CIS chip test system based on FPGA used in one embodiment of the invention shows
It is intended to；
Fig. 2 is FPGA module schematic diagram in one embodiment of the invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with enforcement
Example and accompanying drawing, be further elaborated to the present invention.Should be appreciated that described herein specifically
Embodiment only in order to explain the present invention, is not intended to limit the present invention.
The present invention relates to mobile communications industry processor interface MIPI(Mobile Industry
Processor Interface) high-speed port CIS (CMOS Image Sensor) chip volume production survey
Examination technology, this technology can use on-site programmable gate array FPGA (Field Programmable
Gate Array) chip and MIPI string turns and Data Bridge chip realize the volume production of CIS chip
Demand CP (Chip Probe) test and FT (Final Test) test.
Fig. 1 show used in one embodiment of the invention based on FPAG module (FPAG chip)
CIS chip test system, relate generally to the image data acquiring to CIS chip, change, store
Process with calculating and judge；FPGA module is responsible for master control and the data process of whole system, passes through
MIPI bridging chip gathers from the data of CIS chip, and carries out processing result is uploaded to test
Machine, thus realize the test of the image data portions of CIS chip.For some high-end FPGA at present
Chip, has had special programmable high-speed signal port, and MIPI bridgt circuit can be merged into
In fpga chip, realized by internal circuit, thus simplify whole system further.
As it is shown in figure 1, the power supply of tested CIS chip is provided by test machine, unrelated with MIPI port
Signal port also by test carrier plate directly and test machine want close hardware resource connection, so that it is guaranteed that
The all general test event of CIS chip still can be done directly by test machine, such as
The test events such as Open-short, Leakage, IDDQ and SCAN.
The pin relevant to CIS chip MIPI port and the MIPI bridge joint electricity being arranged on test carrier plate
Road (bridging chip) is connected；And MIPI bridgt circuit is connected with FPGA module, by FPGA mould
Block controls.
When test, test machine controls CIS chip by direct-connected digital channel and gathers image and pass through
View data is exported MIPI bridgt circuit with the pattern of high-speed serial signals by MIPI port.MIPI
Bridgt circuit reads this high speed signal under the control of FPGA module, and real-time synchronization ground is by serial at a high speed
Signal is converted into parallel low speed data signal, and is uploaded to FPGA module.MIPI bridgt circuit
There is provided by FPGA module is unified with the reference clock of the MIPI port of CIS chip, it is ensured that clock zone
Synchronization.FPGA module reads, by parallel data channels, the picture number that MIPI bridgt circuit converts
According to, data are carried out calculating process according to default algorithm, and obtains result of calculation.Final FPGA
Module can be uploaded after result judgement being processed under the control of test machine.Test machine is reading result
After carry out judging and the control of program circuit.
FPGA module internal element as in figure 2 it is shown, specifically include that central control module, data meter
Calculate module DSP, data cache module RAM, register (Register) module and clock module PLL.
Central control module (control unit) is responsible for controlling the collaborative of whole FPGA module built-in system
Work, the instruction of acceptance test machine, control the work of MIPI bridging chip, control FPGA module
Data are processed by each internal element accordingly, and final calculation result is uploaded test machine.?
In FPGA module, control unit is responsible for and up test machine and descending MIPI bridging chip simultaneously
Communication and data exchange.
Data computation module DSP(computing unit) mainly it is responsible under the control of middle control unit storage
Raw image data in RAM carries out calculating process, and returns result.All image procossing institutes
The algorithm routine needed all is pre-stored in the ROM that it is internal, control unit be responsible for selecting concrete letter
Number.
Data cache module RAM mainly stores two class data messages: from the original image of outside reading
Data, the result of calculation of DSP and intermediate data.Data and the address port of this module pass through bus
Connect with control unit and computing unit, in order to the initial data write of control unit and calculating simultaneously
Digital independent and the result of unit write back.
Register (Register) module mainly preserves all kinds of parameter arranging FPGA module work,
And FPGA module various results at work and status information.Test machine passes through general controls list
Unit can realize the random data read-write operation to register.
Clock module PLL is responsible for providing each seed ginseng needed for FPGA module inside and external circuit
Examine clock, to guarantee the uniformity of the clock zone of whole system.Its clock source can have two, and one
Individual is to be provided by test machine, it is ensured that whole system and test machine strict common clock territory；Another be by
Local crystal oscillator on test board provides, it is ensured that the precision of clock zone and low noise characteristic.During work, system
The reference clock source being suitable for can be selected according to the feature of concrete application and demand.
The test systematic difference mode of above-mentioned FPGA module mainly has two kinds:
(1) pattern of full custom circuit: FPGA module system is made with the pattern of ancillary peripheral circuit
A part for test carrier plate circuit is directly installed on test carrier plate.This pattern can realize circuit
Scale minimizes, the optimization of signal quality and minimumization of fault rate.
(2) special daughter board pattern: FPGA module system is fabricated to circuit daughter board in advance, is answering
Used time is connected by special connector or joint and test carrier plate (motherboard), and by motherboard and survey
Test-run a machine and tested CIS chip connect.This pattern can improve repeat usage the convenience of hardware
Maintenance and repair, reduces use cost.
Specifically, use the FPGA module shown in Fig. 2 that CIS chip carries out the work of volume production test
Make mode and flow process may include that
By test machine, FPGA module system is carried out appropriately configured, both corresponding register was joined
Number write, arranges working method and the condition of work of whole system.Simultaneously, if it is desired, test machine
A default reference clock signal can be provided, it is ensured that system is working properly to system；Control list simultaneously
Unit can arrange reference clock selection and the mode of operation of PLL according to the configuration parameter in register, and
Suitable clock signal is sent to MIPI bridgt circuit and tested CIS chip.
Tested CIS chip is configured by test machine by direct-connected data communication road (data wire),
Guarantee that CIS chip normally works, gather light signal and by the data of digital picture by high speed MIPI
Port is sent to test carrier plate.Meanwhile, the MIPI bridgt circuit on test carrier plate can be in real time
High-speed serial signals is converted into parallel data-signal.
After test machine receives clear and definite commencing signal, the control unit within FPGA module can start
Read raw image data from parallel data port and be saved in buffering area (RAM).When a frame is complete
View data accept after, control unit can start data processing unit, deposits according to being pre-stored in
Configuration information in device, parameter needed for selection and algorithmic function are to the original image number in buffer area
According to processing, and result is saved in the lump in buffer area specific position.
After data have calculated, the control unit in FPGA module can be by specific numeral letter
Number passage notice test machine.Test machine can carry out ditch with FPGA module after receiving notification signal
Logical, by the FPDP being connected with FPGA module, required calculating result is read test
The work station of machine also carries out final judgement and Row control.
After above-mentioned all working completes, test machine sends instruction and allows chip under test and FPGA module
System is returned to holding state, thus completes a test period.
In actual volume production test, often use multi-chip simultaneously for improving the execution efficiency of test
And the mode surveyed.But, owing to every chip under test is all the most independent, so for every core
Sheet is required for the test system of one group of independence, and the chip on each station must have the independent of correspondence
The bridging chip of high speed signal.In the present invention, FPGA module can be by making full use of internal money
Multiple system copies worked alone are configured at inside a FPGA module by the mode in source, thus carry
High circuit and the service efficiency of device.FPGA module each copy internal is aforementioned FPGA
One complete copy of inside modules system, it is possible to process each station independently of each other and concurrently
On the data of chip.
Above-described embodiment uses and configures with FPGA module and MIPI on the support plate of CP or FT test
Bridging chip is the localization data processing system of core, replaces and originally needs high-end test machine to perform
Data processing work, it is achieved that testing cost and the optimization of execution efficiency.
Embodiment described above only have expressed embodiments of the present invention, and it describes more concrete and detailed
Carefully, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, it is right
For those of ordinary skill in the art, without departing from the inventive concept of the premise, it is also possible to do
Going out some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, patent of the present invention
Protection domain should be as the criterion with claims.
Claims (9)
1. the volume production method of testing to CIS chip, it is characterised in that described CIS chip has
Having mobile communications industry processor interface MIPI, described method is based on on-site programmable gate array FPGA
Module is carried out, and comprises the steps:
Step 1: provide a kind of volume production to CIS chip to test system, including: test machine, tested
CIS chip, test carrier plate, wherein, test carrier plate is installed MIPI bridging chip and FPGA mould
Block；The pin of the MIPI port of tested CIS chip and the MIPI input port of MIPI bridging chip
Being connected, other signal port of MIPI bridging chip is connected with FPGA module, by FPGA module
Control；
Step 2: test machine controls CIS chip by the digital channel direct-connected with tested CIS chip and adopts
Collection image；
View data is believed with high speed serialization after gathering image by step 3:CIS chip by MIPI port
Number pattern export MIPI bridging chip；
Step 4:MIPI bridging chip reads described high-speed serial signals under FPGA module control,
It is converted into parallel low speed data signal and is uploaded to FPGA module；
Step 5:FPGA module reads the parallel of MIPI bridging chip conversion by parallel data channels
Low speed data signal, carry out technical finesse, it is thus achieved that result of calculation；
Result of calculation is uploaded under the control of test machine by step 6:FPGA module；
Step 7: test machine carries out after reading result judging and the control of program circuit；
Step 8: after above-mentioned steps 2-7 completes, test machine send instruction allow tested CIS chip and
FPGA module returns to holding state, completes a test period.
Volume production method of testing to CIS chip the most according to claim 1, it is characterised in that
Described FPGA module is direct as a part for test carrier plate circuit using the pattern of ancillary peripheral circuit
It is arranged on test carrier plate.
Volume production method of testing to CIS chip the most according to claim 1, it is characterised in that
Described FPGA module is fabricated to circuit daughter board in advance, passes through special connector when application or connects
Head is connected with test carrier plate.
4. according to the volume production method of testing to CIS chip described in Claims 2 or 3, its feature
Being, described FPGA module internal element includes: central control module, data computation module DSP,
Data cache module RAM, register module and clock module PLL, wherein,
Central control module for up test machine and the communication of descending MIPI bridging chip and number
According to exchange and control the collaborative work of whole FPGA module built-in system, the instruction of acceptance test machine,
Control the work of MIPI bridging chip, control internal element and data are processed accordingly, and will
Final calculation result uploads test machine；
Described data computation module DSP is for described to being stored under the control of central control module
Raw image data in data cache module RAM carries out calculating process, and returns result；All
Algorithm routine needed for image procossing is all pre-stored in described data cache module RAM, by central authorities
Control module is responsible for selecting concrete function；
Described data cache module RAM is for storage two class data messages: that reads from outside is original
View data, the result of calculation of described data computation module DSP and intermediate data；Described data are delayed
The data of storing module RAM and address port are by bus simultaneously and central control module and described
Data computation module DSP connects, in order to the initial data write of central control module and described data
Digital independent and the result of computing module DSP write back；
Described register module module is used for preserving all kinds of parameter arranging FPGA module work, and
FPGA module various results at work and status information；Test machine can by central control module
To realize the random data read-write operation to described register module；
Described clock module PLL is for providing FPGA module internal and each needed for external circuit
Plant reference clock, to guarantee the uniformity of the clock zone of whole system；Clock source respectively by test machine or
Local crystal oscillator on test carrier plate provides；The clock source provided by test machine guarantees whole system and test
Machine strictly shares same clock zone；The clock source provided by the local crystal oscillator on test carrier plate guarantees clock
The precision in territory and low noise characteristic；During work, described clock module PLL according to the feature of concrete application and
Demand, selects the reference clock source being suitable for.
Volume production method of testing to CIS chip the most according to claim 4, it is characterised in that
Tested CIS chip and FPGA module, the power supply of MIPI chip is provided by test machine.
Volume production method of testing to CIS chip the most according to claim 4, it is characterised in that
Tested CIS chip is configured by test machine by direct-connected data channel, it is ensured that CIS chip
Normal work, is gathered light signal and the data of digital picture is sent extremely by high speed MIPI port
Test carrier plate.
Volume production method of testing to CIS chip the most according to claim 4, it is characterised in that
FPGA module system is configured by test machine, and described register module is carried out parameter read-in, if
Put working method and the condition of work of FPGA module system.
Volume production method of testing to CIS chip the most according to claim 4, it is characterised in that
Described step 5 includes:
Step 501:FPGA module after test machine receives clear and definite commencing signal, FPGA module
Internal central control module starts to read view data from parallel data port and be saved in described number
According to cache module RAM；
Step 502: after the view data that a frame is complete accepts, central control module starts institute
State data computation module DSP；
Step 503: described data computation module DSP is according to being pre-stored in joining in described register module
Confidence ceases, former in described data cache module RAM of parameter needed for selection and algorithmic function
Beginning view data processes, and result is saved in spy in the lump in described data cache module RAM
Fixed position；
Described step 6 includes: after data have calculated, the central control module of FPGA module
Test machine is notified by specific digital signal channel；
Described step 7 includes: test machine is linked up with FPGA module after receiving notification signal,
By the FPDP being connected with FPGA module, required calculating result is read test machine
Work station and carry out final judgement and Row control.
Volume production method of testing to CIS chip the most according to claim 1, it is characterised in that
The signal port unrelated with MIPI port of described tested CIS chip directly and is surveyed by test carrier plate
The associated hardware resource of test-run a machine connects, so that it is guaranteed that all universal test projects of CIS chip can be by surveying
Test-run a machine is done directly, and wherein said associated hardware resource is for completing the hard of described universal test project
Part resource, described universal test project comprises in Open-short, Leakage, IDDQ and SCAN
At least one.
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