CN111077430A - Device and method for detecting CIS chip based on ATE - Google Patents
Device and method for detecting CIS chip based on ATE Download PDFInfo
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- CN111077430A CN111077430A CN201911294065.0A CN201911294065A CN111077430A CN 111077430 A CN111077430 A CN 111077430A CN 201911294065 A CN201911294065 A CN 201911294065A CN 111077430 A CN111077430 A CN 111077430A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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Abstract
The invention discloses a method for detecting a CIS chip based on ATE, which comprises the following steps: s01: serial image data in the CIS chip are transmitted to a data channel synchronous acquisition module; s02: the data channel synchronous acquisition module caches serial image data to the cache module according to a line sequence; s03: the conversion module sequentially converts the serial image data into parallel image data according to the row sequence; s04: the parallel image data are transmitted to the parallel output module, and the parallel output module adds an indication signal to the parallel image data; the indication signal and the parallel image data are transmitted to an ATE test platform; s05: and the ATE test platform tests the received parallel image data. According to the device and the method for detecting the CIS chip based on the ATE, provided by the invention, the ATE test platform can test and evaluate the serial working mode of the CIS chip through the FPGA transfer processing, so that the test cost is reduced, and the test efficiency is improved.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a device and a method for detecting a CIS chip based on ATE.
Background
In the CIS chip preparation process and after the preparation, chip test evaluation is required to enter a normal use link, and at present, the test evaluation of the CIS chip generally comprises the following three methods: (1) and packaging the CIS chip, performing FT (Final test) test on the packaged CIS chip, and judging the performance of the CIS chip according to an FT test result. Although the FT test result is accurate, the FT test can be carried out only after the CIS chip is packaged, defects in the CIS chip cannot be found early, and if the performance of the chip is detected to be not up to the standard at the stage, the early preparation and packaging of the chip are invalid. (2) And (3) performing CP (ChipProbe) test, namely, pricking the chip to the chip pin through a probe card at the wafer stage to perform performance and function test on the chip, wherein in most cases, particularly in China, the probe selected in the CP test is a cantilever probe at present. The needle of the type is long and suspended, and the control of signal integrity is very difficult, so the highest transmission rate of general data is only 100-400 Mbps, and the test of high-speed signals is almost impossible; in addition, the direct contact between the probe and the pad has a limitation in electrical performance, and leakage and contact resistance are easily generated, which also have a great influence on high-precision signal measurement. Therefore, the precision of the CP test is often not accurate enough, the test judgment standard needs to be properly relaxed, and only preliminary screening can be performed. (3) Before the CIS chip is not packaged, the Test is performed based on an ATE (automatic Test equipment) Test platform, the ATE Test platform can perform large-batch automatic tests, but the existing ATE Test platform is a parallel port Test, and the CIS chip generally has a serial working mode, so that the ATE Test platform cannot Test and evaluate the serial working mode of the CIS chip.
Disclosure of Invention
The invention aims to provide a device and a method for detecting a CIS chip based on ATE (automatic test equipment), which enable an ATE test platform to test and evaluate a serial working mode of the CIS chip through FPGA (field programmable gate array) transfer processing, reduce the test cost and improve the test efficiency.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for detecting a CIS chip based on ATE (automatic test equipment) is disclosed, wherein the CIS chip is connected to the ATE through an FPGA (field programmable gate array); the FPGA comprises a data channel synchronous acquisition module, a cache module, a conversion module and a parallel output module, and comprises the following steps:
s01: serial image data in the CIS chip are transmitted to a data channel synchronous acquisition module; the FPGA comprises a data channel synchronous acquisition module, a cache module, a conversion module and a parallel output module;
s02: the data channel synchronous acquisition module caches serial image data to the cache module according to a line sequence;
s03: the conversion module sequentially converts the serial image data into parallel image data according to the row sequence;
s04: the parallel image data are transmitted to the parallel output module, and the parallel output module adds an indication signal to the parallel image data; the indication signal and the parallel image data are transmitted to an ATE test platform;
s05: and the ATE test platform tests the received parallel image data and evaluates the serial working mode of the CIS chip according to the test result.
Further, serial image data in the CIS chip is transmitted to the data channel synchronous acquisition module through the LVDS interface.
Furthermore, the number of the LVDS interfaces is more than or equal to 1, and the serial image data transmitted by each LVDS interface is synchronous.
Further, the conversion module in step S03 converts the serial image data into parallel image data through the shift register.
Further, the indication signal is a frame signal and a row signal.
Further, before step S01, the ATE test platform sends a stimulus signal i and a stimulus signal ii to the CIS chip and the FPGA, respectively.
Further, in step S05, the ATE test platform performs noise calculation on the received parallel image data, and evaluates the serial operating mode of the CIS chip according to the calculation result.
Further, the noise calculation comprises one or more of row-column noise calculation, image mean calculation, image color separation mean calculation and DN standard deviation calculation.
A device for detecting a CIS chip based on ATE comprises a CIS chip, an FPGA and an ATE test platform, wherein the FPGA comprises a data channel synchronous acquisition module, a cache module, a conversion module and a parallel output module, the working mode of the CIS chip is a serial working mode, and the ATE test platform is a parallel port test platform;
serial image data in the CIS chip are transmitted to a data channel synchronous acquisition module; the data channel synchronous acquisition module caches serial image data to the cache module according to a line sequence; the conversion module sequentially converts the serial image data into parallel image data according to the row sequence; the parallel image data are transmitted to the parallel output module, and the parallel output module adds an indication signal to the parallel image data; the indication signal and the parallel image data are transmitted to an ATE test platform; and the ATE test platform tests the received parallel image data and evaluates the serial working mode of the CIS chip according to the test result.
Furthermore, the FPGA also comprises a serial image data sending module, and the serial image data sending module is connected with the data channel synchronous acquisition module.
The invention has the beneficial effects that: the invention carries out the conversion of serial image data based on the FPGA, so that the ATE test platform can test and evaluate the serial working mode of the CIS chip, thereby accurately testing the CIS chip before the CIS chip is not packaged, improving the test evaluation capability of the CIS chip at the CP stage based on the ATE test platform, simultaneously reducing the test cost and improving the production efficiency of the whole CIS chip.
Drawings
FIG. 1 is a schematic diagram of the framework of the device of the present invention.
FIG. 2 is a schematic structural diagram of an FPGA according to the present invention.
FIG. 3 is a timing diagram of the FPGA conversion operation of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
In the prior art, the CIS chip is directly connected to an ATE test platform for testing. Then the working mode of the CIS chip comprises a serial working mode and a parallel working mode, the image quality obtained by the CIS chip in the serial mode is good, the transmission of image data can reach more than 100fps, and the transmission of the image data in the parallel mode of the CIS chip is generally 10 fps. The CIS chip adopts a serial working mode, namely the mode of outputting image data is a serial output mode; the ATE test platform is a parallel port (parallel interface) test platform, namely the mode of acquiring image data is parallel acquisition; therefore, the ATE test platform cannot directly test the serial working mode of the CIS chip.
As shown in fig. 1, the device for detecting the CIS chip based on the ATE provided by the invention comprises a CIS chip, an FPGA and an ATE test platform, wherein the CIS chip is an unpackaged chip, the ATE test platform is a parallel port test platform, and the CIS chip is connected to the ATE test platform through the FPGA for testing.
As shown in fig. 2, the FPGA includes a data channel synchronous acquisition module, a buffer module, a conversion module and a parallel output module, and serial image data in the CIS chip is transmitted to the data channel synchronous acquisition module; the data channel synchronous acquisition module caches the serial image data to the cache module according to the line sequence; the conversion module sequentially converts the serial image data into parallel image data according to the row sequence; the parallel image data are transmitted to a parallel output module, and the parallel output module adds an indication signal to the parallel image data; the indication signal and the parallel image data are transmitted to an ATE test platform; and the ATE test platform tests the received parallel image data and evaluates the serial working mode of the CIS chip according to the test result. The FPGA further comprises a serial image data sending module, the serial image data sending module is connected with a data channel synchronous acquisition module, when the whole detection device does not work, the serial image data sending module can replace a CIS chip to generate test serial image data, whether a data transmission channel between the FPGA and an ATE test platform is normal or not is conveniently verified, at the moment, compared with the normal running state of the whole device, the serial image data sending module replaces the CIS chip and is used for sending the serial image data to the data channel synchronous acquisition module, the data channel synchronous acquisition module sequentially sends the received serial image data to a cache module, a conversion module and a parallel output module, and finally the parallel output module transmits the converted parallel data to the ATE test platform. The parallel image data received by the ATE test platform can detect whether transmission channels between each module in the FPGA and the ATE test platform are normal or not.
The method for detecting the received image data by the ATE test platform can be any detection method in the prior art. For example, after confirming that all image data of one frame of the CIS chip is input to the ATE test platform, the ATE performs an algorithm on the received image data by adopting various noise algorithms, and counts whether a calculation result meets an expectation or not, so as to judge whether the serial working mode of the CIS chip is normal or not. Wherein the noise algorithm and the expectation may be freely defined. The specific noise algorithm comprises one or more of row-column noise calculation, image mean calculation, image color separation mean calculation and DN (image Digital number) standard deviation calculation, for example, Pixel _ Defect _ Test is adopted to count Defect bad points in the image data; calculating row-column noise in the image data by adopting Illum _ FPN _ Test or FPN _ NoRank _ Test; counting Cluster (defect combination) of the image by adopting Illum _ Cluster _ Test; performing bloming statistics on the image by adopting Illum _ bloming _ Test; adopting a Shading _ Test to carry out Shading statistics on the image; calculating the blocking uniformity of the image under dark and illumination conditions by adopting DSNU _ Test; and comparing the image Color separation mean value by adopting Color _ Ratio _ Test, and calculating bad lines/columns in the image by adopting Partial _ Dead _ Line _ Test.
The invention provides a method for detecting a CIS chip based on ATE, which comprises the following steps:
s01: the ATE test platform sends an excitation signal I and an excitation signal II to the CIS chip and the FPGA respectively; and then, transmitting the serial image data in the CIS chip to a data channel synchronous acquisition module.
Specifically, the excitation signal i includes: the ATE test platform provides power supply, clock, delay, frame rate, required pin initialization state, register data written into the CIS chip through spi communication protocol and working timing sequence to the CIS chip.
The excitation signal ii includes: and the ATE test platform provides power supply and related relay states required by the FPGA during operation.
The serial image data in the CIS chip is transmitted to the data channel synchronous acquisition module through the LVDS interfaces, the number of the LVDS interfaces is larger than or equal to 1, and the serial image data transmitted by each LVDS interface is synchronous. In specific application, the FPGA realizes the synchronization of the serial protocols in each interface through the serial control channel protocol of the CIS chip, so that an input clock input to the LVDS interface is the same as an output clock output by the LVDS interface for outputting image data.
S02: and the data channel synchronous acquisition module caches the serial image data to the cache module according to the line sequence.
Specifically, the buffer module may be a DDR buffer, when the CIS chip transmits serial image data, the serial image data of multiple lines are sequentially transmitted to the buffer module according to the sequence of lines in the image, please refer to fig. 3, column 4-5 signals respectively represent that the data channel synchronization acquisition module writes the serial image data into a write request signal and a corresponding buffer address in the buffer module after completing synchronization of the LVDS channel, and the write process is valid when the write request signal is at a high level. Therefore, the serial image data stored in the buffer module is stored in the corresponding buffer address as a row unit.
S03: the conversion module converts serial image data into parallel image data sequentially through the shift register according to the row sequence, and the conversion module in the step is a conversion module from serial to parallel. Referring to fig. 3, the conversion module reads out an entire line of image data and performs serial-to-parallel operation, and column 1-3 signals respectively represent a read request, a read count, and a corresponding address signal for the conversion module to sequentially read out a line of image data from the buffer module, where the read request signal is high level and the read is valid. Column 6 is a line image data conversion completion flag, and a high level indicates that a line of image signals are converted in series and completed.
The conversion module in the invention takes the line image data in the cache module as a unit, and sequentially converts each line of image data, wherein the conversion sequence is sequentially carried out according to the line sequence in the image. The serial image data refers to a line of image data transmitted in a serial output mode; the parallel image data refers to one line of image data transmitted in a parallel output manner.
S04: the parallel image data are transmitted to a parallel output module, and the parallel output module adds an indication signal to the parallel image data; and transmitting the indication signal and the parallel image data to an ATE test platform.
Specifically, a line of image data is converted serially and then transmitted to the parallel output module, and the parallel output module adds a corresponding frame signal and a corresponding line signal at the front end of the line of image data and transmits the frame signal and the line signal to the ATE test platform, so that the image data received by the ATE test platform is ensured to be effective image data. Referring to fig. 3, columns 7-9 represent frame signals, line signals and corresponding parallel image data, respectively, wherein the corresponding parallel image data is valid data only when the frame signals and the line signals are both high level. Specifically, the parallel output module may be a DVP parallel output interface, and add corresponding frame signals and line signals to corresponding line image data by designing DVP parallel interface logic.
S05: and the ATE test platform tests the received parallel image data and evaluates the serial working mode of the CIS chip according to the test result. The ATE test platform performs idp (image data processor) processing on the received image data. And the ATE test platform performs noise calculation on the received parallel image data and judges the serial working mode of the CIS chip according to the calculation result. For example, after confirming that all image data of the CIS chip is input into an ATE test platform, the ATE performs various noise algorithms on the received image data and calculates results, and whether the calculation results meet expectations or not is counted so as to judge whether the serial working mode of the CIS chip is normal or not. The method is used for evaluating the serial working mode of the CIS chip, namely evaluating the performance of the CIS chip in the serial working mode, and mainly evaluating the serial working mode of the CIS chip by carrying out noise calculation on an image generated by the CIS chip in the serial working mode.
The invention carries out the conversion of serial image data based on the FPGA, so that the ATE test platform can test and evaluate the serial working mode of the CIS chip, thereby accurately testing the CIS chip before the CIS chip is not packaged, improving the test evaluation capability of the CIS chip at the CP stage based on the ATE test platform, simultaneously reducing the test cost and improving the production efficiency of the whole CIS chip.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (10)
1. The method for detecting the CIS chip based on the ATE is characterized in that the CIS chip is connected to the ATE through the FPGA; the FPGA comprises a data channel synchronous acquisition module, a cache module, a conversion module and a parallel output module, and comprises the following steps:
s01: serial image data in the CIS chip are transmitted to a data channel synchronous acquisition module;
s02: the data channel synchronous acquisition module caches serial image data to the cache module according to a line sequence;
s03: the conversion module sequentially converts the serial image data into parallel image data according to the row sequence;
s04: the parallel image data are transmitted to the parallel output module, and the parallel output module adds an indication signal to the parallel image data; the indication signal and the parallel image data are transmitted to an ATE test platform;
s05: and the ATE test platform tests the received parallel image data and evaluates the serial working mode of the CIS chip according to the test result.
2. The method for CIS chip detection based on ATE of claim 1, wherein the serial image data in the CIS chip is transmitted to the data channel synchronous acquisition module through LVDS interface.
3. The method for CIS chip detection based on ATE of claim 2, wherein the number of LVDS interfaces is greater than or equal to 1, and the serial image data transmitted by each LVDS interface is synchronous.
4. The method for CIS chip detection based on ATE of claim 1, wherein the conversion module in step S03 converts serial image data into parallel image data through a shift register.
5. The method for CIS chip detection based on ATE of claim 1, wherein the indication signal is a frame signal and a line signal.
6. The method for CIS chip detection based on ATE of claim 1, wherein before step S01, the ATE test platform sends stimulus signal I and stimulus signal II to CIS chip and FPGA, respectively.
7. The method of claim 1, wherein in step S05, the ATE test platform performs noise calculation on the received parallel image data, and evaluates the serial operation mode of the CIS chip according to the calculation result.
8. The method of claim 7, wherein the noise calculation comprises one or more of a row-column noise calculation, an image mean calculation, an image color separation mean calculation, and a DN standard deviation calculation.
9. The device for detecting the CIS chip based on the ATE is characterized by comprising the CIS chip, an FPGA and an ATE test platform, wherein the FPGA comprises a data channel synchronous acquisition module, a cache module, a conversion module and a parallel output module, the working mode of the CIS chip is a serial working mode, and the ATE test platform is a parallel port test platform;
serial image data in the CIS chip are transmitted to a data channel synchronous acquisition module; the data channel synchronous acquisition module caches serial image data to the cache module according to a line sequence; the conversion module sequentially converts the serial image data into parallel image data according to the row sequence; the parallel image data are transmitted to the parallel output module, and the parallel output module adds an indication signal to the parallel image data; the indication signal and the parallel image data are transmitted to an ATE test platform; and the ATE test platform tests the received parallel image data and evaluates the serial working mode of the CIS chip according to the test result.
10. The device for CIS chip detection based on ATE of claim 9, wherein the FPGA further comprises a serial image data transmission module, and the serial image data transmission module is connected with the data channel synchronous acquisition module.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116381468A (en) * | 2023-06-05 | 2023-07-04 | 浙江瑞测科技有限公司 | Method and device for supporting multi-chip parallel test by single image acquisition card |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625056A (en) * | 2012-03-30 | 2012-08-01 | 广东正业科技股份有限公司 | FPGA (Field-Programmable Gate Array)-based CIS (Contact Image Sensor) image acquisition system and acquisition method thereof |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| US20140145745A1 (en) * | 2012-11-26 | 2014-05-29 | Samsung Electronics Co., Ltd. | Test system for testing a cmos image sensor and a driving method thereof |
| CN104484885A (en) * | 2014-12-25 | 2015-04-01 | 上海华岭集成电路技术股份有限公司 | ATE test method for CIS chip YUV format output |
| CN105072359A (en) * | 2015-08-26 | 2015-11-18 | 中国科学院上海高等研究院 | CMOS (Complementary Metal Oxide Semiconductor) image sensor imaging system and method based on compressed sensing |
-
2019
- 2019-12-16 CN CN201911294065.0A patent/CN111077430A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625056A (en) * | 2012-03-30 | 2012-08-01 | 广东正业科技股份有限公司 | FPGA (Field-Programmable Gate Array)-based CIS (Contact Image Sensor) image acquisition system and acquisition method thereof |
| US20140145745A1 (en) * | 2012-11-26 | 2014-05-29 | Samsung Electronics Co., Ltd. | Test system for testing a cmos image sensor and a driving method thereof |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN104484885A (en) * | 2014-12-25 | 2015-04-01 | 上海华岭集成电路技术股份有限公司 | ATE test method for CIS chip YUV format output |
| CN105072359A (en) * | 2015-08-26 | 2015-11-18 | 中国科学院上海高等研究院 | CMOS (Complementary Metal Oxide Semiconductor) image sensor imaging system and method based on compressed sensing |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116381468A (en) * | 2023-06-05 | 2023-07-04 | 浙江瑞测科技有限公司 | Method and device for supporting multi-chip parallel test by single image acquisition card |
| CN116381468B (en) * | 2023-06-05 | 2023-08-22 | 浙江瑞测科技有限公司 | Method and device for supporting multi-chip parallel test by single image acquisition card |
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Application publication date: 20200428 |