CN105897350A - Method and apparatus for testing transmitter chip - Google Patents
Method and apparatus for testing transmitter chip Download PDFInfo
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- CN105897350A CN105897350A CN201610251278.5A CN201610251278A CN105897350A CN 105897350 A CN105897350 A CN 105897350A CN 201610251278 A CN201610251278 A CN 201610251278A CN 105897350 A CN105897350 A CN 105897350A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/101—Monitoring; Testing of transmitters for measurement of specific parameters of the transmitter or components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/15—Performance testing
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
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- Monitoring And Testing Of Transmission In General (AREA)
Abstract
The invention relates to a method and apparatus for testing a transmitter chip. The method comprises the steps: receiving a signal of a chip to be tested according to the transmitted test rate of a test firmware; sending the signal under the test rate to a digital signal processing chip so as to enable the digital signal processing chip to calculate and analyze the signal under the test rate to obtain the test result; and sending the test result to a testing machine. The method and apparatus for testing a transmitter chip utilize the chip to transmit and receive the signal of a chip to be tested and to analyze the signal so as to replace an instrument in a traditional calibration and testing mode, and can realize automatic calibration and testing through the firmware.
Description
Technical field
The present invention relates to Internet of Things WIFI chip field, particularly relate to the method for testing of a kind of transmitter chip
And device.
Background technology
Due in chip manufacturing proces the diversity of device and temperature and external environment condition for chip internal
The impact of device work, even if same series-produced radio frequency chip also has certain difference in performance
The opposite sex.In order to ensure the concordance of product, all can be to the simulation of WIFI radio frequency chip before product is paid
Circuit carries out direct current biasing, the calibration of homophase I/ orthogonal Q two-way phase and amplitude, to correct because manufacturing
During process deviation impact time analog circuit is worked, and also can carry out performance test and ensure
The product conformity energy requirement paid.
Specific instrument typically can be used radio frequency chip being calibrated and tests when to send and connect
The performance of radio frequency chip is measured by the radiofrequency signal of specific format.This method needs to be equipped with extra instrument
Device, adds the cost of test.Simultaneously instrument can only a corresponding radio frequency chip, if do not bought
Multiple stage instrument, it is impossible to accomplish that multi-disc is tested simultaneously, it is also difficult to promote calibration and the efficiency of test.
Summary of the invention
Technical problem
In view of this, the technical problem to be solved in the present invention is, how to provide the survey of a kind of transmitter chip
Method for testing and device, enable transmitter chip to test voluntarily.
Solution
For solving above technical problem, the present invention provides the test side of a kind of transmitter chip in first aspect
Method, including:
Receive chip to be measured according to the signal under the test rate of test firmware transmitting；
Signal under described test rate is sent to digital signal processing chip, so that described digital signal
Process chip calculates the signal under described test rate and parsing draws test result, and by described
Test result sends to tester table.
In a kind of possible implementation, in the survey that described reception chip to be measured is launched according to test firmware
After signal under examination speed, also include: when test item is error vector magnitude, described standard chips
Signal under the described test rate that will receive is demodulated in base band.
In a kind of possible implementation, described digital signal processing chip is under described test rate
Signal carries out calculating and parsing draws test result, including:
Described digital signal processing chip analyzes the frequency component of signal under described test rate, frequency spectrum mould
Plate, power and error vector magnitude.
In a kind of possible implementation, in the survey that described reception chip to be measured is launched according to test firmware
Before signal under examination speed, also include:
Receive the instruction of described tester table, with according to described instruction, enter test mode.
In a kind of possible implementation, described test result is being sent after tester table, also
Including:
Described tester table is given notice to described chip to be measured, so that the firmware root in described chip to be measured
Rate configuration is adjusted according to described test result.
For solving above technical problem, the present invention provides the test dress of a kind of transmitter chip in second aspect
Put, including:
Chip to be measured；
Standard chips, is connected with described chip to be measured, is used for receiving chip to be measured and launches according to test firmware
Test rate under signal, and by under described test rate signal send to digital signal processor core
Sheet；
Described digital signal processing chip, is connected with described standard chips, under described test rate
Signal carry out calculating and parsing draws test result, and described test result is sent to tester table.
In a kind of possible implementation, described standard chips is additionally operable to when test item is error vector width
When spending, the signal under the described test rate that will receive is demodulated in base band.
In a kind of possible implementation, described digital signal processing chip, for described test speed
Signal under rate carries out calculating and parsing draws test result, including: described digital signal processing chip,
For analyzing the frequency component of the signal under described test rate, spectrum mask, power and error vector width
Degree.
In a kind of possible implementation, described standard chips is additionally operable to receive the finger of described tester table
Order, with according to described instruction, enters test mode.
In a kind of possible implementation, this device also includes:
Described tester table, with described digital signal processing chip, described standard chips and described core to be measured
Sheet connects, for giving notice to described chip to be measured, so that the firmware in described chip to be measured is according to institute
State test result and adjust rate configuration.
Beneficial effect
The method of testing of the transmitter chip according to present invention offer and device, by receiving chip root to be measured
According to the signal under the test rate that test firmware is launched；Signal under described test rate is sent to numeral
Signal processing chip, so that the signal under described test rate is counted by described digital signal processing chip
Calculate and parsing draws test result, and described test result is sent to tester table, it is possible to utilize chip
Launch and receive the signal of chip to be measured and resolve, thus replacing in conventional calibration and test pattern
Instrument, and the automatization of test is realized by firmware.
The method of testing of a kind of transmitter chip according to present invention offer and device, by increasing standard core
Sheet (golden chip) can realize multi-plate chip rapidly and test simultaneously, improves testing efficiency and saves
Cost.
According to below with reference to the accompanying drawings to detailed description of illustrative embodiments, the further feature of the present invention and side
Face will be clear from.
Accompanying drawing explanation
The accompanying drawing of the part comprising in the description and constituting description together illustrates with description
The exemplary embodiment of the present invention, feature and aspect, and for explaining the principle of the present invention.
Fig. 1 illustrates the structural representation of the test device of the transmitter chip that the embodiment of the present invention provides；
Fig. 2 illustrates the flow chart of the method for testing of the transmitter chip that the embodiment of the present invention provides；
Fig. 3 illustrates the illustraton of model of transmitter；
Fig. 4 illustrates the illustraton of model of receiver；
Fig. 5 illustrates the schematic diagram of digital baseband receiving path.
Detailed description of the invention
Various exemplary embodiments, feature and the aspect of the present invention is described in detail below with reference to accompanying drawing.Attached
Reference identical in figure represents the same or analogous element of function.Although enforcement shown in the drawings
The various aspects of example, but unless otherwise indicated, it is not necessary to accompanying drawing drawn to scale.
The most special word " exemplary " means " as example, embodiment or illustrative ".Here as
Any embodiment illustrated by " exemplary " should not necessarily be construed as preferred or advantageous over other embodiments.
It addition, in order to better illustrate the present invention, detailed description of the invention below gives numerous
Detail.It will be appreciated by those skilled in the art that do not have some detail, the present invention is equally
Implement.In some instances, method well known to those skilled in the art, means, element are not made in detail
Thin description, in order to highlight the purport of the present invention.
Embodiment 1
Based on communication system for the requirement of cost, area, power consumption and integrated level, zero intermediate frequency transceiver with
It is relative to the simpler structure of super-heterodyne architecture transceiver, higher bandwidth, less area and lower
Power consumption receive in a communications system and use widely.
In 802.11 agreements, define radio circuit under different rates and modulation system should meet
Low index.For receiver, leading indicator is receiving sensitivity, leading indicator for transmitter
It is spectrum mask, error vector magnitude (EVM) and transmitting power.Every piece of WIFI chip pay with
Before be required for passing through performance test.
Fig. 1 illustrates the structural representation of the test device 1 of the transmitter chip that the embodiment of the present invention provides,
As it is shown in figure 1, this test device 1 includes: golden chip 11, tester table 12, chip to be measured
13, Digital Signal Processing dsp chip 14.
Standard chips, such as golden chip 11, be connected with chip 13 to be measured, dsp chip 14 with
Golden chip 11 connects, tester table 12 respectively with dsp chip 14, standard chips (such as golden
Chip 11) and chip to be measured 13 connect.
In a kind of possible implementation, tester table 12 can be directed into by specific pin
Row is launched signal specific or receives the operation of storage signal.The antenna end of chip 13 to be measured will and golden
The antenna end of chip 11 is connected, and communicates with golden chip 11 with reception signal to send.Tester table
12 can be communicated with synchronous calibration and test process with chip 13 to be measured by specific pin equally.Test
Dsp chip 15 in version then be used for calculate the signal that chip 13 to be measured sends or receives frequency,
The information such as amplitude, phase contrast, and feed back to tester table 12 to determine calibration and the survey of chip 13 to be measured
Test result.
Fig. 2 illustrates the flow chart of the method for testing of the transmitter chip that the embodiment of the present invention provides, such as Fig. 2
Shown in, the method may include that
Step S1, chip to be measured 13 launch the signal under test rate according to test firmware.
Step S2, golden chip 11 receive and store the signal under this test rate.
Signal under described test rate is sent to dsp chip 14 by step S3, golden chip 11.
Step S4, dsp chip 14 calculate the signal under described test rate and parsing draws survey
Test result, and test result is sent to tester table 12.
Analyze including dsp chip 14 frequency component of signal under described test rate, spectrum mask,
Power and error vector magnitude, and test result is sent to tester table 12, true by tester table 12
Whether location survey test result meets preset standard.
In a kind of possible implementation, receive chip to be measured at golden chip 11 solid according to test
Before signal under the test rate that part is launched, also include: golden chip 11 and chip to be measured 13 connect
The instruction of Acceptance Tests board 12, with according to described instruction, enters test mode；And
In a kind of possible implementation, described test result is being sent after tester table, also
Including: step S5, tester table 12 are given notice to chip 13 to be measured, so that in chip to be measured 13
Firmware according to described test result adjust rate configuration.
In a kind of possible implementation, golden chip 11 can leading to according to tester table 12
Know transmission signal.
The test device 1 of a kind of transmitter chip that the embodiment of the present invention provides and the embodiment of the present invention provide
The method of testing of transmitter chip, by receiving the test that chip 13 to be measured is launched according to test firmware
Signal under speed；Signal under described test rate is sent to dsp chip 14, so that described number
Signal under described test rate is calculated by word signal processing chip and parsing draws test result, and
Described test result is sent to tester table 12, it is possible to utilize chip emission and receive chip 13 to be measured
Signal and resolve, thus replace the instrument in conventional calibration and test pattern, and real by firmware
The automatization now tested.
The test device 1 of a kind of transmitter chip that the embodiment of the present invention provides and the embodiment of the present invention provide
The method of testing of transmitter chip, can by increasing standard chips (such as golden chip 11)
Realizing multi-plate chip rapidly to test, raising testing efficiency is the most cost-effective simultaneously.
Fig. 3 illustrates the illustraton of model of transmitter.The embodiment of the present invention is applicable to the transmitter shown in Fig. 3.As
Shown in Fig. 3, this transmitter 2 includes: first digital baseband the 21, first direct current biasing and IQ mismatch are mended
Repay circuit 22, digital-analog convertor the 23, first low pass filter the 24, first frequency mixer 25, merit
Rate amplifier 26.
Wherein, the first digital baseband 21, the data that will send for modulation so that data fit through
Wireless antenna sends.RF_BIST_MEM: be used for storing the sampling letter required for calibration and test computing
Number.(abbreviation: DC_ADJ) 22, by calibrating and joining for first direct current biasing and I/Q mismatch compensation circuit
Put the direct current biasing compensating in receiving path and IQ mismatch.Digital-analog convertor (English:
Digital-Analog Converter, abbreviation: DAC) 23 convert digital signals into analogue signal.The
One low pass filter (English: Low-Pass Filter, abbreviation: LPF) 24, it is used for suppressing out-of-band interference to believe
Number.First frequency mixer 25, uses local oscillation signal to be mixed data signal modulation to radio frequency with zero intermediate frequency signals
In frequency range.Power amplifier (English: Power Amplifier, abbreviation: PA) 26, frequency mixer is defeated
The signal amplifying power that goes out also is sent on antenna.
Zero-intermediate-frequency transmitter simple in construction, integrated level is high, but the quickest for direct current biasing and IQ mismatch
Sense.Direct current biasing can cause transmitting terminal local oscillator leakage occur, in carrier signal can with local frequency phase
Same signal, causes serious direct current biasing at receiving terminal, affects the performance of receiver.Therefore school is passed through
The direct current biasing of transmitter is done compensation and can be good at improving the transmission in whole communication system by quasi-circuit
Accuracy.And because signal is to be passed by orthogonal two paths of signals I road and Q road in zero-intermediate-frequency transmitter
Defeated, in two-way transmission circuit, device performance does not mates the width that likely can cause orthogonal two paths of signals
Degree and the mismatch of phase place, cause generating useless lower sideband signal in emission process, and impact receives circuit
Performance.Therefore, at transmitting terminal, I/Q mismatch is done compensation and can improve the performance of transmission channel.Sending out
Penetrating in machine structure, before DAC, DC_ADJ module is used for adjusting direct current biasing (the English DC of transmitter
And I/Q passage mismatch Offset).
Fig. 4 illustrates receiver module figure, and as shown in Figure 4, this receiver 3 includes: low-noise amplifier
31, local oscillator the 32, second frequency mixer the 33, second low pass filter 34, analog-digital converter
35, the second direct current biasing and I/Q mismatch compensation circuit the 36, second digital baseband 37.
Wherein, low-noise amplifier (English: Low-Noise Amplifier, abbreviation: LNA) 31,
Receive and amplify receive on radio-frequency antenna radiofrequency signal.Local oscillator 32 is (English: Local
Oscillator, abbreviation: LO).Local oscillator 32, is used for producing local oscillation signal.Second frequency mixer 33,
The radiofrequency signal using local oscillation signal and RF filter to receive carries out mixing and is transformed into zero intermediate frequency signals.The
Two low pass filters (English: Low-Pass Filter, abbreviation: LPF) 34, it is used for suppressing out-of-band interference
Signal.Analog-digital converter (English: Analog-Digital Converter, abbreviation: ADC) 35,
Analogue signal in zero intermediate frequency is converted into digital signal.Second direct current biasing and I/Q mismatch compensation circuit
(abbreviation: DC_ADJ) 36 compensates the direct current biasing in receiving path by calibration and configuration and IQ loses
Join.Second digital baseband 37, the signal that demodulation will receive on antenna, revert to the original of transmitter transmitting
Data.RF_BIST_MEM: be used for storing the sampled signal required for calibration and test computing.
Due to zero intermediate frequency reciver switching bandwith signal to zero intermediate frequency, too much bias voltage can deteriorate letter
Number, and the circuit after mixing can be caused saturated, such as LPF or ADC etc..Therefore compensating direct current is inclined
Put within circuit is operated in ideal operation region after ensure that mixing, thus improve receiver performance.
And IQ mismatch is also the key factor affecting zero-if architecture receiver performance.In zero intermediate frequency
In structure, as shown in Figure 4, the zero intermediate frequency signals of frequency mixer output can be divided into two-way to transmit, due to I/Q
Two-way delivering path median filter, the device such as amplifier and ADC there may exist the difference in performance,
Make there will be the problem of amplitude or phase mismatch by orthogonal two paths of signals, cause demodulated signal
The deterioration of planisphere.In receiver module, DC_ADJ module is also used to adjust the DC of recipient
Offset and I/Q passage mismatch.The number to I/Q two-way is carried out by calibration flow process configuration DC_ADJ
Word signal carries out the compensation in amplitude and phase place, can effectively improve the demodulation performance of digital baseband.
Preferably, when test item is error vector magnitude (EVM), golden chip 11 will receive
To described test rate under signal be demodulated in base band.Fig. 5 illustrates digital baseband receiving path
Schematic diagram, as it is shown in figure 5, radio circuit (English: Radio-Frequency, abbreviation: RF),
Receiving radio data from antenna, and be converted to digital signal.Preamble detecting, detection radio circuit transmission
Signal, if there is the frame head of the data defined in wireless transmission protocol/management frame, then notifies follow-up base band
Circuit starts demodulating data.Serioparallel exchange, is divided into the time domain letter that N road is parallel by ofdm signal stream
Number stream, each of which road time-domain signal is corresponding with a subcarrier in N number of orthogonal sub-carriers.
Fast fourier transform (English: Fast Fourier Transform, abbreviation: FFT), by N road also
The time-domain signal of row is converted into frequency-region signal and exports the frequency-region signal that N road is parallel.Channel estimation/all
Weighing apparatus, the transport channel parameters being wirelessly transferred according to transmission Signal estimation, and use the channel parameter pair of estimation
The data received compensate, with correction signal skew in wireless transmission channel.Demapping, will connect
The data received are mapped on planisphere and decode the data stream of correspondence according to planisphere.Output N road is parallel
Data stream.Parallel-serial conversion, is merged into a circuit-switched data stream by the N circuit-switched data stream that de-mapping device exports.Letter
Road coded demodulation, encodes according to predefined channel coding method demodulated channel in wireless transmission protocol,
Data stream recovery is become initial data.
Vector magnitude (English: Error Vector Magnitude, abbreviation: EVM) test-error to
Measure examination, specifically represent the IQ component and ideal signal component produced when signal is demodulated by receiver
Degree of closeness, be a kind of index considering modulated signal quality.Vector magnitude (EVM) is defined as
The ratio of the root-mean-square value of error vector average power signal and the root-mean-square value of ideal signal mean power, and
Represent with the form of percentage ratio.EVM is the least, and signal quality is the best.
Defined by EVM it can be seen that the initial data of EVM test is to enter the number before de-mapping device
According to, i.e. data stream after channel estimation/equalization, the therefore RF_BIST_MEM when testing EVM
The data of record need from channel estimation/equalization module with post-sampling and it needs to the receiving path of receiving terminal is just
Often work.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
In this, any those familiar with the art, can be easily in the technical scope that the invention discloses
Expect change or replace, all should contain within protection scope of the present invention.Therefore, the protection of the present invention
Scope should be as the criterion with described scope of the claims.
Claims (10)
1. the method for testing of a transmitter chip, it is characterised in that including:
Standard chips receives chip to be measured according to the signal under the test rate of test firmware transmitting；
Signal under described test rate is sent to digital signal processing chip by described standard chips, so that
Described digital signal processing chip calculates the signal under described test rate and parsing draws test
As a result, and by described test result send to tester table.
Method of testing the most according to claim 1, it is characterised in that at described reception core to be measured
After signal under the test rate that sheet is launched according to test firmware, also include: when test item be error to
During discharge amplitude, the signal under the described test rate that described standard chips will receive solves in base band
Adjust.
Method of testing the most according to claim 2, it is characterised in that described Digital Signal Processing
Chip calculates the signal under described test rate and parsing draws test result, including:
Described digital signal processing chip analyzes the frequency component of signal under described test rate, frequency spectrum mould
Plate, power and error vector magnitude.
Method of testing the most according to claim 3, it is characterised in that connect at described standard chips
Receive chip to be measured according to test firmware launch test rate under signal before, also include:
Receive the instruction of described tester table, with according to described instruction, enter test mode.
5. according to the method for testing according to any one of claim 1-4, it is characterised in that by institute
State test result to send after tester table, also include:
Described tester table is given notice to described chip to be measured, so that the firmware root in described chip to be measured
Rate configuration is adjusted according to described test result.
6. the test device of a transmitter chip, it is characterised in that including:
Chip to be measured；
Standard chips, is connected with described chip to be measured, is used for receiving chip to be measured and launches according to test firmware
Test rate under signal, and by under described test rate signal send to digital signal processor core
Sheet；
Described digital signal processing chip, is connected with described standard chips, under described test rate
Signal carry out calculating and parsing draws test result, and described test result is sent to tester table.
Test device the most according to claim 6, it is characterised in that described standard chips is also used
In when test item is error vector magnitude, the signal under the described test rate that will receive is in base band
It is demodulated.
Test device the most according to claim 7, it is characterised in that described Digital Signal Processing
Chip, for the signal under described test rate being calculated and parsing draws test result, including:
Described digital signal processing chip, is used for the frequency component of signal, the frequency spectrum analyzing under described test rate
Template, power and error vector magnitude.
Test device the most according to claim 8, it is characterised in that described standard chips is also used
In the instruction of the described tester table of reception, with according to described instruction, enter test mode.
10. according to the test device according to any one of claim 6-9, it is characterised in that also include:
Described tester table, with described digital signal processing chip, described standard chips and described core to be measured
Sheet connects, for giving notice to described chip to be measured, so that the firmware in described chip to be measured is according to institute
State test result and adjust rate configuration.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610251278.5A CN105897350A (en) | 2016-04-22 | 2016-04-22 | Method and apparatus for testing transmitter chip |
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| CN201610251278.5A CN105897350A (en) | 2016-04-22 | 2016-04-22 | Method and apparatus for testing transmitter chip |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106452613A (en) * | 2016-11-30 | 2017-02-22 | 贵州航天林泉电机有限公司 | Internal transmitter PCM (pulse code modulation) signal test system |
| CN110943791A (en) * | 2019-11-26 | 2020-03-31 | 北京中电华大电子设计有限责任公司 | Test platform and IQ mismatch test method for BLE radio frequency transceiver system |
| CN112612659A (en) * | 2020-12-15 | 2021-04-06 | 海光信息技术股份有限公司 | Chip testing method and device, electronic equipment and storage medium |
| CN114295963A (en) * | 2021-12-31 | 2022-04-08 | 龙迅半导体（合肥）股份有限公司 | Chip testing method and system |
| CN115021832A (en) * | 2022-06-02 | 2022-09-06 | 上海磐启微电子有限公司 | Chip communication test system with low cost and high isolation |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227693A (en) * | 2008-01-17 | 2008-07-23 | 中兴通讯股份有限公司 | Apparatus and method of wireless links loopback test |
| CN201919158U (en) * | 2010-12-03 | 2011-08-03 | 东南大学 | Multi-mode multi-band radio frequency onboard pico cellular communication system based on software radio |
| CN102788947A (en) * | 2011-05-17 | 2012-11-21 | 联咏科技股份有限公司 | Testing chip and chip testing system thereof |
| CN103414526A (en) * | 2013-07-24 | 2013-11-27 | 福建星网锐捷通讯股份有限公司 | Test system and test method of radio frequency identification index |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN103852714A (en) * | 2012-11-30 | 2014-06-11 | 联发科技股份有限公司 | Integrated circuit, test equipment and RF testing system |
| CN104394544A (en) * | 2014-12-19 | 2015-03-04 | 上海斐讯数据通信技术有限公司 | Automatic radio frequency test method for WiFi (Wireless Fidelity) product |
| US9035672B2 (en) * | 2008-11-20 | 2015-05-19 | Litepoint Corporation | Digital communications test system for multiple input, multiple output (MIMO) systems |
| CN105099580A (en) * | 2015-08-26 | 2015-11-25 | 北京朗波芯微技术有限公司 | Quadrature mismatch calibration system and method and radio frequency front-end chip |
| CN105162714A (en) * | 2015-10-22 | 2015-12-16 | 上海斐讯数据通信技术有限公司 | Performance detecting method and system of radio frequency terminal |
-
2016
- 2016-04-22 CN CN201610251278.5A patent/CN105897350A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101227693A (en) * | 2008-01-17 | 2008-07-23 | 中兴通讯股份有限公司 | Apparatus and method of wireless links loopback test |
| US9035672B2 (en) * | 2008-11-20 | 2015-05-19 | Litepoint Corporation | Digital communications test system for multiple input, multiple output (MIMO) systems |
| CN201919158U (en) * | 2010-12-03 | 2011-08-03 | 东南大学 | Multi-mode multi-band radio frequency onboard pico cellular communication system based on software radio |
| CN102788947A (en) * | 2011-05-17 | 2012-11-21 | 联咏科技股份有限公司 | Testing chip and chip testing system thereof |
| CN103852714A (en) * | 2012-11-30 | 2014-06-11 | 联发科技股份有限公司 | Integrated circuit, test equipment and RF testing system |
| CN103414526A (en) * | 2013-07-24 | 2013-11-27 | 福建星网锐捷通讯股份有限公司 | Test system and test method of radio frequency identification index |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN104394544A (en) * | 2014-12-19 | 2015-03-04 | 上海斐讯数据通信技术有限公司 | Automatic radio frequency test method for WiFi (Wireless Fidelity) product |
| CN105099580A (en) * | 2015-08-26 | 2015-11-25 | 北京朗波芯微技术有限公司 | Quadrature mismatch calibration system and method and radio frequency front-end chip |
| CN105162714A (en) * | 2015-10-22 | 2015-12-16 | 上海斐讯数据通信技术有限公司 | Performance detecting method and system of radio frequency terminal |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106452613A (en) * | 2016-11-30 | 2017-02-22 | 贵州航天林泉电机有限公司 | Internal transmitter PCM (pulse code modulation) signal test system |
| CN110943791A (en) * | 2019-11-26 | 2020-03-31 | 北京中电华大电子设计有限责任公司 | Test platform and IQ mismatch test method for BLE radio frequency transceiver system |
| CN110943791B (en) * | 2019-11-26 | 2022-10-14 | 北京中电华大电子设计有限责任公司 | Test platform and IQ mismatch test method for BLE radio frequency transceiver system |
| CN112612659A (en) * | 2020-12-15 | 2021-04-06 | 海光信息技术股份有限公司 | Chip testing method and device, electronic equipment and storage medium |
| CN114295963A (en) * | 2021-12-31 | 2022-04-08 | 龙迅半导体（合肥）股份有限公司 | Chip testing method and system |
| CN114295963B (en) * | 2021-12-31 | 2024-05-14 | 龙迅半导体（合肥）股份有限公司 | Chip testing method and system |
| CN115021832A (en) * | 2022-06-02 | 2022-09-06 | 上海磐启微电子有限公司 | Chip communication test system with low cost and high isolation |
| CN115021832B (en) * | 2022-06-02 | 2023-12-05 | 上海磐启微电子有限公司 | Chip communication test system with low cost and high isolation |
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Application publication date: 20160824 |