CN106647700B - A kind of FPGA configuration control system test method, control platform and verification platform - Google Patents
A kind of FPGA configuration control system test method, control platform and verification platform Download PDFInfo
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- CN106647700B CN106647700B CN201611132486.XA CN201611132486A CN106647700B CN 106647700 B CN106647700 B CN 106647700B CN 201611132486 A CN201611132486 A CN 201611132486A CN 106647700 B CN106647700 B CN 106647700B
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The present invention provides a kind of FPGA configuration control system test method, control platform and verification platform, by obtaining the test case tested the design to be measured of configuration control system, and according in test case test execution process and generate constraint condition generate test bit stream data be input to test execution platform, wherein, it is related to comprising the nominative testing data that are generated according to constraint condition and for testing process but the configuration data random test data generated without generation constraint condition in test bit stream data, corresponding write-in or reading clock signal are generated according to configuration interface message, the design to be measured for testing bit stream data write-in configuration control system is tested according to clock signal, since the test bit stream data of generation has randomness, therefore performance situation of the configuration control system under each situation can be verified, into And improve the accuracy and reliability of configuration control system functional verification.
Description
Technical field
The present invention relates to programmable integrated circuit design field more particularly to a kind of FPGA (Field Programmable
Gate Array, field programmable gate array) configuration control system test method, control platform and verification platform.
Background technique
With the growth requirement of information and date science and technology, programmable chip, especially field programmable gate array rely on it
The advantages that flexible in programming, system are stable, resourceful, integrated level is high, application field are extended from the original communications field
To extensive fields such as space flight, consumer electronics, Industry Control, test measurements, and there are also ever-expanding trend.However as
Continuous soaring, level of integrated system, programmable resource and device scale proposition of the people for programmable circuit of process node
Higher requirement.For FPGA system, the configuration information bit stream for needing to generate software configures control system by FPGA
System is loaded into the configuration memory cell SRAM of related circuit module in circuit system, to complete the configuration of corresponding function, therefore
FPGA configuration control system design rationality and practicability play the role of for user experience it is very important, for
The test of FPGA configuration control system is also very important a ring in design cycle.
It at present for the test of FPGA configuration control system, is carried out on FPGA configuration control system test and verification platform
, the test bit stream data needed is mainly generated by the software kit tool customization of FPGA, then configuration data stream is read
Device reads corresponding test bit stream data, is then input in driver and is handled by format conversion, while by default
Configuration interface message generate it is corresponding write-in or reading clock signal be input in driver, bit stream will be tested by driver
Data are tested according to the design to be measured that configuration control system is written in clock signal.In this process, software kit tool
Placement-and-routing's effect be it is fixed, interface is also fixed, therefore the test bit stream data that software kit tool generates is also
Fixed, do not have randomness, can not just authenticate to the case where FPGA configuration control system shows under random case, therefore yet
The accuracy for testing verifying is not high.
Summary of the invention
A kind of FPGA configuration control system test method, control platform and verification platform provided by the invention, mainly solve
The technical issues of be: in the prior art to FPGA configuration control system test when, the test bit stream data of generation does not have
Randomness can not verify the problem of FPGA configuration control system shows situation under random case.
In order to solve the above technical problems, the present invention provides a kind of FPGA configuration control system testing and control platform, comprising:
Case-based system device, for obtaining the test case tested the design to be measured of configuration control system, the survey
Examination example includes testing process, at least partly the generations constraint condition of configuration data and configures interface involved in testing process
Information；
Configuration data generator, for generating test position according to the test execution process and the generation constraint condition
Flow data is input to test execution platform；Nominative testing in the test bit stream data comprising being generated according to the constraint condition
Data and be related to for the testing process but without generate constraint condition configuration data random test data generated；
Interface sequence generator is configured, for generating corresponding write-in or reading timing letter according to the configuration interface message
Number it is input to the test execution platform, so that the configuration control system is written in the bit stream data by the test execution platform
Design to be measured tested.
Further, the present invention also provides a kind of FPGA to configure control system test and verification platform, which is characterized in that including
Test execution platform and above-mentioned FPGA configure control system testing and control platform；
The test execution platform is used to be matched by described according to the clock signal of the configuration interface sequence generator output
The test bit stream data for setting Data Generator output is written the design to be measured for configuring control system and is tested.
Further, the present invention also provides a kind of FPGA to configure control system test method characterized by comprising
The test case tested the design to be measured of configuration control system is obtained, the test case includes test stream
Involved in journey, testing process at least partly the generation constraint condition of configuration data and configuration interface message；
It is input to test according to the test execution process and generation constraint condition generation test bit stream data and holds
Row platform；Comprising the nominative testing data that generate according to the constraint condition and the survey is directed in the test bit stream data
Examination process is related to but without the configuration data random test data generated for generating constraint condition；
Corresponding write-in is generated according to the configuration interface message or reading clock signal is input to the test execution and puts down
Platform, so that the test execution platform tests the design to be measured that the configuration control system is written in the bit stream data；
According to the clock signal, the configuration is written into the test bit stream data of configuration data generator output and is controlled
The design to be measured of system processed is tested.
The beneficial effects of the present invention are:
FPGA configuration control system test method, control platform and the verification platform provided according to the present invention, passes through example
Getter obtains the test case tested the design to be measured of configuration control system, and configuration data generator is real according to test
Test execution process and generation constraint condition in example generate test bit stream data and are input to test execution platform, wherein survey
In examination bit stream data comprising the nominative testing data that are generated according to constraint condition and be related to for testing process but without generation about
The configuration data of beam condition random test data generated, configuration interface sequence generator connect according to the configuration in test case
Message breath generates corresponding write-in or reading clock signal is input to test execution platform, so that the test execution platform will be tested
The design to be measured of bit stream data write-in configuration control system is tested, the test bit stream number generated due to configuration data generator
According to randomness, therefore performance situation of the configuration control system under each situation can be verified, and then improve configuration control
The accuracy and reliability of system functional verification processed.
Detailed description of the invention
Fig. 1 is that the FPGA of the embodiment of the present invention one configures control system test method first pass schematic diagram；
Fig. 2 is that the FPGA of the embodiment of the present invention one configures control system test method second procedure schematic diagram；
Fig. 3 is that the FPGA of the embodiment of the present invention two configures the structural schematic diagram of control system testing and control platform；
Fig. 4 is the structural schematic diagram of the configuration data generator of the embodiment of the present invention two；
Fig. 5 is that the FPGA of the embodiment of the present invention three configures the first structure diagram of control system test and verification platform；
Fig. 6 is that the FPGA of the embodiment of the present invention three configures the second structural schematic diagram of control system test and verification platform；
Fig. 7 is that the FPGA of the embodiment of the present invention three configures the third structural schematic diagram of control system test and verification platform.
Specific embodiment
The embodiment of the present invention is described in further detail below by specific embodiment combination attached drawing.
Embodiment one:
In order to make the test for configuring control system to FPGA be no longer dependent on software kit tool, improves to configure FPGA and control
The accuracy that system processed is tested, the present embodiment provides a kind of FPGA to configure control system test method, can specifically join
As shown in Figure 1, comprising:
S101: the test case tested the design to be measured of configuration control system is obtained.
Test case in the present embodiment includes testing process, at least partly life of configuration data involved in testing process
At constraint condition and configuration interface message.And it should be noted that the design to be measured in the present embodiment can be to realize certain
The circuit design of function.Wherein, test case can be obtained by case-based system device in step S101.
S102: test bit stream data is generated according to testing process and constraint condition and is input to test execution platform.
It should be understood that in the present embodiment can by configuration data generator generate test bit stream data, this
Configuration data generator in embodiment can according in the test case that case-based system device is got testing process and life
At constraint condition, generates test bit stream data and be input to test execution platform.Wherein, the configuration data in the present embodiment is raw
The test bit stream data of generation of growing up to be a useful person includes the nominative testing data generated according to constraint condition, and is related to for testing process
But without the configuration data random test data generated for generating constraint condition.
It should be noted that the configuration data generator in the present embodiment may include at least one in following generator
Kind: configuration register automatically generate device, configuration storing data automatically generate device, clear data generator and configuration data identification in
Hold generator.
It that is to say, the configuration data generator in the present embodiment can only include any one in above-mentioned generator, or
Person may include any two kinds, three kinds in above-mentioned generator, or can also simultaneously include four kinds of above-mentioned generators.Example
Such as, the configuration data generator in the present embodiment may include that configuration register automatically generates device and configuration storing data from movable property
Raw device.
Therefore the configuration data generator in the present embodiment generate test bit stream data just include in following situations at least
It is a kind of:
Configuration register automatically generates device and generates specified configuration register data according to constraint condition is generated, and/or random
Generate random arrangement register data；
Configuration storing data automatically generates the specified number that device is configured to FPGA storage unit according to constraint condition generation is generated
According to, and/or the random data for being configured to FPGA storage unit is randomly generated；
Clear data generator is generated for clock handover configurations or the clear data waited for the time.
Configuration data identifies that Content Generator generates the mark data that bit stream data is tested described in unique identification.
It should be understood that the configuration register in the present embodiment automatically generates device can specify according to constraint condition generation
Configuration register data and random arrangement register data is randomly generated, can also only generate specified configuration register data or only
Generate random arrangement register data.Likewise, the configuration storing data in the present embodiment automatically generate device can be according to constraint
Condition generates the director data for being configured to FPGA storage unit and the random data for being configured to FPGA storage unit is randomly generated, or
Person can also only generate specified data or only generate random data.Clear data generator in the present embodiment can produce for when
Clock handover configurations or the clear data waited for the time, when so as to provide enough waitings for pattern switching data processing
Between, it should be appreciated that the size of the clear data in the present embodiment can be pre-set by developer, can also support
User is customized.The mark data that configuration data identification Content Generator in the present embodiment generates can be a fixed number
According to mainly playing mark action, identification data can be located at the head of test bit stream data, can also be located at test bit stream number
According to tail portion, naturally it is also possible to while be located at test bit stream data head and tail portion.
S103: corresponding write-in is generated according to configuration interface message or reading clock signal is input to test execution platform.
It should be noted that in the present embodiment clock signal can be generated by configuring interface sequence generator, and configure
Interface sequence generator can generate write-in according to the configuration interface message that case-based system device is got or read clock signal.
S104: according to clock signal, the test bit stream data that configuration data generator exports is written to configuration control system
The design to be measured of system is tested.
It should be understood that the present embodiment S104 step can be executed by test execution platform.
Below in the present embodiment to configuration control system design to be measured carry out test be described further.
Shown in Figure 2, the testing process executed in the present embodiment to the design to be measured of configuration control system includes:
S201: test bit stream data is respectively written by configuration the to be measured of control system according to the clock signal received and is set
In meter and simulator.
For S201, the above process can be realized by driver, and the configuration interface sequence hair in the present embodiment
The clock signal that raw device generates can input in driver, meanwhile, the test that the configuration data generator in the present embodiment generates
Bit stream data can also be input in driver.
S202: the reference model of the design to be measured comprising configuration control system in simulator, and according to the test position of input
Flow data generates simulation result and exports into checker.
S203: the design to be measured of configuration control system is obtained according to the operation result of test bit stream data output, and should
As a result it exports into checker.
It should be understood that the design to be measured of configuration control system can be obtained in the present embodiment by monitor according to survey
The operation result of bit stream data output is tried, the S202 and S203 in the present embodiment do not have successive point, can first carry out S203 again
Execute S202.
S204: checker carries out checking treatment to the simulation result and operation result received and obtains test result.
It furthermore it should also be noted that, can also be directly defeated by the design to be measured for asserting controller to configuration control system
Enter additional test and excitation, at this time assert controller can with configuration control system design to be measured in excitation input interface connect
It connects, it is to be understood that when by asserting that controller inputs additional test and excitation to the design to be measured of configuration control system,
Same additional test and excitation can be inputted into simulator.It is understood that the configuration data generator in the present embodiment
Random test data can be only generated, nominative testing data at this time can be by asserting controller to configuration control system
Design input to be measured, while the specified data will be also input in simulator.
Further, it is also possible to will assert that controller is connected with the monitoring position in the design to be measured for configuring control system, assert
The signal that controller can extract the monitoring position is monitored.
Furthermore it should also be noted that, storage unit in the design to be measured of the configuration control system in the present embodiment is retouched
Stating format can be for from the array descriptor format of array functional layer progress whole description, it is, for example, possible to use register types
Verilog (hardware description language) describing mode carries out the description of array storage unit, can so shorten emulation and compiling
Time, make processing speed in simulator faster, to improve simulation efficiency.
FPGA provided in an embodiment of the present invention configures control system test method, is generated and is tested by configuration data generator
Bit stream data is input to test execution platform, wherein test bit stream data in include nominative testing data and random test data,
So as to verify performance situation of the configuration control system under each situation, the standard of test verifying configuration control system is improved
True property, compared with the existing technology in by software kit tool generate test bit stream data can also save the regular hour.
Embodiment two:
The present embodiment provides a kind of FPGA to configure control system testing and control platform 30, specifically may refer to shown in Fig. 3,
Including case-based system device 31, configuration data generator 32 and configuration interface sequence generator 33.
Wherein, case-based system device 31 is used to obtain the test case tested the design to be measured of configuration control system.
Test case in the present embodiment includes testing process, at least partly generation constraint item of configuration data involved in testing process
Part and configuration interface message.And it should be noted that the design to be measured in the present embodiment can be the electricity of certain function of realization
Road design.
In the test case that configuration data generator 32 in the present embodiment is used to be got according to case-based system device 31
Testing process and generation constraint condition generate test bit stream data and are input to test execution platform；Test position in the present embodiment
It is related to comprising the nominative testing data that are generated according to constraint condition and for testing process but without generating constraint item in flow data
The configuration data of part random test data generated.
It should be noted that the configuration data generator 32 in the present embodiment includes at least one of following generator:
Configuration register automatically generates device, is used to generate specified configuration register data according to generation constraint condition, and/or
Random arrangement register data is randomly generated；
Configuration storing data automatically generates device, the finger for being configured to FPGA storage unit according to constraint condition generation is generated
Fixed number evidence, and/or the random data for being configured to FPGA storage unit is randomly generated；
Clear data generator；For generating for clock handover configurations or the clear data waited for the time.
Configuration data identifies Content Generator, for generating the mark data of unique identification test bit stream data.
It that is to say, the configuration data generator 32 in the present embodiment can only include any one in above-mentioned generator,
Perhaps it may include any two kinds, three kinds in above-mentioned generator or can also simultaneously include four kinds of above-mentioned generators.Example
Such as, the configuration data generator 32 in the present embodiment may include configuration register automatically generate device, configuration storing data it is automatic
Generator and configuration data identify Content Generator.Shown in Figure 4, Fig. 4 is when the configuration data in the present embodiment generates
Device 32 includes that configuration register automatically generates device 321, configuration storing data automatically generates device 322, clear data generator simultaneously
323 and configuration data identification Content Generator 324 when, the structural schematic diagram of four kinds of generators.
It should be understood that the configuration register in the present embodiment automatically generates device can specify according to constraint condition generation
Configuration register data and random arrangement register data is randomly generated, can also only generate specified configuration register data or only
Generate random arrangement register data.Specifically, the configuration register in the present embodiment automatically generate device can produce it is various
The content of configuration register, including control register, command register, bit wide identification register, user register and other
Register and customized register for identification etc. are mainly used for that the controlling party that bit wide identifies, configures storing data is arranged
Formula, interfaces mode, verification calculation, Read-write Catrol mode, encryption and decryption control mode etc., control control bit in register
Conditional combination mode can be carried out according to the principle not conflicted with command bit in command register be randomized generation controlling value.
Likewise, the configuration storing data in the present embodiment automatically generates device can be configured to according to constraint condition generation
It the director data of FPGA storage unit and is randomly generated the random data for being configured to FPGA storage unit, or can also only generate
Specified data only generate random data.
Clear data generator in the present embodiment can produce for clock handover configurations or the blank number waited for the time
It is filling content according to, clear data, without function, and when can reserve enough for processes such as clock switching, pattern switchings
Between complete to operate.It should be understood that the size and location of the clear data in the present embodiment can be preparatory by developer
It sets, can also support that user is customized.
The mark data that configuration data identification Content Generator in the present embodiment generates can be a fixed data,
Mark action is mainly played, identification data can be located at the head of test bit stream data, can also be located at test bit stream data
Tail portion, naturally it is also possible to while be located at test bit stream data head and tail portion.It should be understood that when to single configuration control
When the design to be measured of system processed is tested, it is also not necessary to configuration data identification Content Generators to generate mark data.When
It so, can be according to the corresponding production of setting of design to be measured in the FPGA configuration control system testing and control platform 30 in the present embodiment
Raw device, the combination of specific generator can be with flexible setting.
Configuration interface sequence generator 33 in the present embodiment is used to generate corresponding write according to the configuration interface message
Enter or read clock signal and be input to the test execution platform, so that the test execution platform writes the test bit stream data
The design to be measured for entering the configuration control system is tested.
FPGA configuration control system testing and control platform 30 provided in this embodiment can also include asserting controller.This reality
It applies and asserts controller in example for connecting with the excitation input interface in the design to be measured of configuration control system, for directly to matching
The design to be measured for setting control system inputs additional test and excitation；
And/or
Controller is asserted for connecting with the monitoring position in the design to be measured of configuration control system, for extracting monitoring position
The signal set is monitored.
It that is to say, controller can be used for the design to be measured input directly to configuration control system to asserting in the present embodiment
While additional test and excitation, it can be used for being monitored a certain monitoring position in design to be measured, can also have simultaneously
There is above-mentioned function.In this way, can more intuitive, more easily add additional test and excitation or increase monitoring position carry out it is more detailed
Thin signal detection, so that the quality of test verifying is preferably guaranteed.
Certainly, when what is provided through this embodiment asserts that controller inputs additional survey to the design to be measured of configuration control system
When examination excitation, same additional test and excitation can also be inputted into simulator.It is understood that the configuration in the present embodiment
Data Generator 32 can only generate random test data, and nominative testing data at this time can be by asserting controller to matching
The design to be measured input of control system is set, while the specified data will be also input in simulator.
The FPGA configuration control system testing and control platform 30 provided through this embodiment, can directly pass through configuration data
Generator 32 generates the test bit stream data for test, can promote testing efficiency, and due to the test bit stream number of generation
According to randomness, therefore the accuracy of configuration control system test verification result can be improved.
Embodiment three:
Shown in Figure 5, the present embodiment provides a kind of FPGA to configure control system test and verification platform 50, including test
It executes platform 34 and any one above-mentioned FPGA configures control system testing and control platform 30.
Herein, it should be noted that the FPGA configuration control system testing and control platform 30 in the present embodiment can integrate
In in FPGA configuration control system test and verification platform 50, the overall time of validation test can be saved in this way, this certain implementation
FPGA configuration control system testing and control platform 30 in example can also configure control system test and verification platform independently of FPGA
Additional setting other than 50.
Test execution platform 34 in the present embodiment is used for the clock signal exported according to configuration interface sequence generator 33,
The design to be measured that the test bit stream data that configuration data generator 32 exports is written to configuration control system is tested.
Shown in Figure 6, test execution platform 34 provided in this embodiment may include driver 341, simulator
342, monitor 344 and checker 345.
The clock signal that driver 341 in the present embodiment is used to be exported according to configuration interface sequence generator 33 will configure
The bit stream data that Data Generator 32 exports is respectively written into the design 343 to be measured of configuration control system and simulator 342.
The reference model of design to be measured comprising configuration control system in simulator 342, for the bit stream number according to input
It exports according to simulation result is generated to checker 345；
Monitor 344 is used to obtain the design to be measured of configuration control system according to the operation knot of test bit stream data output
Fruit, and operation result is exported to checker 345；
Checker 345 is used to carry out checking treatment to the simulation result and operation result received to obtain test result.
When including asserting controller 35 in FPGA provided in this embodiment configuration control system test and verification platform 50, this
FPGA configuration control system test and verification platform 50 in embodiment may refer to shown in Fig. 7.
Furthermore it should also be noted that, storage unit in the design to be measured of the configuration control system in the present embodiment is retouched
Stating format can be for from the array descriptor format of array functional layer progress whole description, it is, for example, possible to use register types
Verilog (hardware description language) describing mode carries out the description of array storage unit, in this way, verification platform 50 is in compiling
Better process of compilation and integrated treatment can be obtained, the netlist that synthesis obtains when simulation run can be made more simplified, greatly reduced
The system consumption of simulation software is tested so as to shorten the compilation time and simulation time of emulation so as to shorten whole test
The time is demonstrate,proved, and then improves simulation efficiency.
The FPGA configuration control system test and verification platform provided through this embodiment, generates the mode of test bit stream data
It is no longer dependent on software kit tool, it is possible to reduce software kit tool generates test bit stream data and read test bit stream number
According to time-consuming and laborious process, so as to reduce the time of test verifying, produced since device can be automatically generated by configuration data
Raw random test bit stream data, fixed test bit stream data can only be generated compared to software kit tool, enables to test
Platform validation is demonstrate,proved to the loophole at many dead angles of design to be measured, tests the standard that verifying configures control system design to be measured to improve
True property.
Obviously, those skilled in the art should be understood that each module of the embodiments of the present invention or each step can be used
General computing device realizes that they can be concentrated on a single computing device, or be distributed in multiple computing device institutes
On the network of composition, optionally, they can be realized with the program code that computing device can perform, it is thus possible to by them
It is stored in computer storage medium (ROM/RAM, magnetic disk, CD) and is performed by computing device, and in some cases, it can
With the steps shown or described are performed in an order that is different from the one herein, or they are fabricated to each integrated circuit dies
Block, or single integrated circuit module is maked multiple modules or steps in them to realize.So the present invention does not limit
It is combined in any specific hardware and software.
The above content is combining specific embodiment to be further described to made by the embodiment of the present invention, cannot recognize
Fixed specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs,
Without departing from the inventive concept of the premise, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention
Protection scope.
Claims (10)
1. a kind of FPGA configures control system testing and control platform characterized by comprising
Case-based system device, for obtaining the test case tested the design to be measured of configuration control system, the test is real
Example is believed including at least partly generation constraint condition of configuration data and configuration interface involved in testing process, testing process
Breath；
Configuration data generator, it is defeated for generating test bit stream data according to the testing process and the generation constraint condition
Enter to test execution platform；In the test bit stream data comprising the nominative testing data that are generated according to the constraint condition and
It is related to for the testing process but without the configuration data random test data generated for generating constraint condition；
Interface sequence generator is configured, for defeated according to the corresponding write-in of configuration interface message generation or reading clock signal
Enter to the test execution platform, so that the configuration control system is written in the test bit stream data by the test execution platform
Design to be measured tested.
2. FPGA as described in claim 1 configures control system testing and control platform, which is characterized in that the configuration data is raw
It grows up to be a useful person including at least one of following generator:
Configuration register automatically generates device, is used to generate specified configuration register data according to the generation constraint condition, and/or
Random arrangement register data is randomly generated；
Configuration storing data automatically generates device, for generating the finger for being configured to FPGA storage unit according to the generation constraint condition
Fixed number evidence, and/or the random data for being configured to FPGA storage unit is randomly generated；
Clear data generator, for generating for clock handover configurations or the clear data waited for the time；
Configuration data identifies Content Generator, for generating the mark data for testing bit stream data described in unique identification.
3. FPGA as described in claim 1 configures control system testing and control platform, which is characterized in that further include asserting control
Device；
It is described to assert controller for connecting with the excitation input interface in the design to be measured of the configuration control system, for straight
It connects to the design to be measured of the configuration control system and inputs additional test and excitation；
And/or
It is described to assert controller for connecting with the monitoring position in the design to be measured of the configuration control system, for extracting
The signal for stating monitoring position is monitored.
4. a kind of FPGA configures control system test and verification platform, which is characterized in that including test execution platform and such as right
It is required that the described in any item FPGA of 1-3 configure control system testing and control platform；
The test execution platform is used for the clock signal according to the configuration interface sequence generator output, by the configuration number
It is tested according to the design to be measured that the configuration control system is written in the test bit stream data that generator exports.
5. FPGA as claimed in claim 4 configures control system test and verification platform, which is characterized in that the test execution is flat
Platform includes driver, simulator, monitor and checker；
The driver is used to be generated the configuration data according to the clock signal of the configuration interface sequence generator output
The bit stream data of device output is respectively written into the design to be measured and simulator of the configuration control system；
The reference model of design to be measured comprising the configuration control system in the simulator, for the bit stream number according to input
It exports according to simulation result is generated to the checker；
The monitor is used to obtain the design to be measured of the configuration control system according to the fortune of the test bit stream data output
Row is as a result, and export the operation result to the checker；
The checker is used to carry out checking treatment to the simulation result and operation result received to obtain test result.
6. FPGA as described in claim 4 or 5 configures control system test and verification platform, which is characterized in that the configuration control
The descriptor format of storage unit in the design to be measured of system processed is the array description that whole description is carried out from array functional layer
Format.
7. a kind of FPGA configures control system test method characterized by comprising
Obtain the test case tested of design to be measured to configuration control system, the test case include testing process,
Involved in testing process at least partly the generation constraint condition of configuration data and configuration interface message；
Test bit stream data, which is generated, according to the testing process and the generation constraint condition is input to test execution platform；Institute
It states in test bit stream data comprising the nominative testing data that are generated according to the constraint condition and is related to for the testing process
And but without the configuration data random test data generated for generating constraint condition；
Corresponding write-in or reading clock signal are generated according to the configuration interface message；
According to the clock signal, configuration control system is written into the test bit stream data of configuration data generator output
The design to be measured of system is tested.
8. FPGA as claimed in claim 7 configures control system test method, which is characterized in that the configuration data generator
Generating test bit stream data according to the testing process and the generation constraint condition includes at least one of following situations:
Configuration register automatically generates device and generates specified configuration register data according to the generation constraint condition, and/or random
Generate random arrangement register data；
Configuration storing data automatically generates device and generates the specified number for being configured to FPGA storage unit according to the generation constraint condition
According to, and/or the random data for being configured to FPGA storage unit is randomly generated；
Clear data generator is generated for clock handover configurations or the clear data waited for the time；
Configuration data identifies that Content Generator generates the mark data that bit stream data is tested described in unique identification.
9. FPGA as claimed in claim 7 configures control system test method, which is characterized in that further include:
By it is described configuration control system design to be measured in excitation input interface directly to it is described configure control system to
It surveys design and inputs additional test and excitation；
And/or
The signal for extracting the monitoring position in the design to be measured of the configuration control system is monitored.
10. as the described in any item FPGA of claim 7-9 configure control system test method, which is characterized in that according to described
The design to be measured of the configuration control system is written in the test bit stream data that the configuration data generator exports by clock signal
Carrying out test includes:
According to the clock signal by it is described test bit stream data be respectively written into it is described configuration control system design to be measured and
Simulator, the reference model of the design to be measured comprising the configuration control system in the simulator；
The simulator generates simulation result according to the test bit stream data of input and exports to checker；
The design to be measured of the configuration control system is obtained according to the operation result of the test bit stream data output, and will be described
Operation result is exported to the checker；
Checker carries out checking treatment to the simulation result and operation result received and obtains test result.
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